111731Sjason@lowepower.comRedirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout
211731Sjason@lowepower.comRedirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr
311731Sjason@lowepower.comgem5 Simulator System.  http://gem5.org
411731Sjason@lowepower.comgem5 is copyrighted software; use the --copyright option for details.
511731Sjason@lowepower.com
612137Sar4jc@virginia.edugem5 compiled Jul 13 2017 17:09:45
712137Sar4jc@virginia.edugem5 started Jul 13 2017 17:09:50
812137Sar4jc@virginia.edugem5 executing on boldrock, pid 1346
912137Sar4jc@virginia.educommand line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing
1011731Sjason@lowepower.com
1111731Sjason@lowepower.comGlobal frequency set at 1000000000000 ticks per second
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3712137Sar4jc@virginia.eduamoadd.d: PASS
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4612137Sar4jc@virginia.eduamomaxu.d: PASS
4712137Sar4jc@virginia.eduExiting @ tick 250490500 because exiting with last active thread context
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