config.json revision 11731:c473ca7cc650
1{
2    "name": null, 
3    "sim_quantum": 0, 
4    "system": {
5        "kernel": "", 
6        "mmap_using_noreserve": false, 
7        "kernel_addr_check": true, 
8        "membus": {
9            "point_of_coherency": true, 
10            "system": "system", 
11            "response_latency": 2, 
12            "cxx_class": "CoherentXBar", 
13            "forward_latency": 4, 
14            "clk_domain": "system.clk_domain", 
15            "width": 16, 
16            "eventq_index": 0, 
17            "default_p_state": "UNDEFINED", 
18            "p_state_clk_gate_max": 1000000000000, 
19            "master": {
20                "peer": [
21                    "system.physmem.port"
22                ], 
23                "role": "MASTER"
24            }, 
25            "type": "CoherentXBar", 
26            "frontend_latency": 3, 
27            "slave": {
28                "peer": [
29                    "system.system_port", 
30                    "system.cpu.l2cache.mem_side"
31                ], 
32                "role": "SLAVE"
33            }, 
34            "p_state_clk_gate_min": 1000, 
35            "snoop_filter": {
36                "name": "snoop_filter", 
37                "system": "system", 
38                "max_capacity": 8388608, 
39                "eventq_index": 0, 
40                "cxx_class": "SnoopFilter", 
41                "path": "system.membus.snoop_filter", 
42                "type": "SnoopFilter", 
43                "lookup_latency": 1
44            }, 
45            "power_model": null, 
46            "path": "system.membus", 
47            "snoop_response_latency": 4, 
48            "name": "membus", 
49            "p_state_clk_gate_bins": 20, 
50            "use_default_range": false
51        }, 
52        "symbolfile": "", 
53        "readfile": "", 
54        "thermal_model": null, 
55        "cxx_class": "System", 
56        "work_begin_cpu_id_exit": -1, 
57        "load_offset": 0, 
58        "work_begin_exit_count": 0, 
59        "p_state_clk_gate_min": 1000, 
60        "memories": [
61            "system.physmem"
62        ], 
63        "work_begin_ckpt_count": 0, 
64        "clk_domain": {
65            "name": "clk_domain", 
66            "clock": [
67                1000
68            ], 
69            "init_perf_level": 0, 
70            "voltage_domain": "system.voltage_domain", 
71            "eventq_index": 0, 
72            "cxx_class": "SrcClockDomain", 
73            "path": "system.clk_domain", 
74            "type": "SrcClockDomain", 
75            "domain_id": -1
76        }, 
77        "mem_ranges": [], 
78        "eventq_index": 0, 
79        "default_p_state": "UNDEFINED", 
80        "p_state_clk_gate_max": 1000000000000, 
81        "dvfs_handler": {
82            "enable": false, 
83            "name": "dvfs_handler", 
84            "sys_clk_domain": "system.clk_domain", 
85            "transition_latency": 100000000, 
86            "eventq_index": 0, 
87            "cxx_class": "DVFSHandler", 
88            "domains": [], 
89            "path": "system.dvfs_handler", 
90            "type": "DVFSHandler"
91        }, 
92        "work_end_exit_count": 0, 
93        "type": "System", 
94        "voltage_domain": {
95            "name": "voltage_domain", 
96            "eventq_index": 0, 
97            "voltage": [
98                "1.0"
99            ], 
100            "cxx_class": "VoltageDomain", 
101            "path": "system.voltage_domain", 
102            "type": "VoltageDomain"
103        }, 
104        "cache_line_size": 64, 
105        "boot_osflags": "a", 
106        "system_port": {
107            "peer": "system.membus.slave[0]", 
108            "role": "MASTER"
109        }, 
110        "physmem": {
111            "range": "0:134217727:0:0:0:0", 
112            "latency": 30000, 
113            "name": "physmem", 
114            "p_state_clk_gate_min": 1000, 
115            "eventq_index": 0, 
116            "p_state_clk_gate_bins": 20, 
117            "default_p_state": "UNDEFINED", 
118            "kvm_map": true, 
119            "clk_domain": "system.clk_domain", 
120            "power_model": null, 
121            "latency_var": 0, 
122            "bandwidth": "73.000000", 
123            "conf_table_reported": true, 
124            "cxx_class": "SimpleMemory", 
125            "p_state_clk_gate_max": 1000000000000, 
126            "path": "system.physmem", 
127            "null": false, 
128            "type": "SimpleMemory", 
129            "port": {
130                "peer": "system.membus.master[0]", 
131                "role": "SLAVE"
132            }, 
133            "in_addr_map": true
134        }, 
135        "power_model": null, 
136        "work_cpus_ckpt_count": 0, 
137        "thermal_components": [], 
138        "path": "system", 
139        "cpu_clk_domain": {
140            "name": "cpu_clk_domain", 
141            "clock": [
142                500
143            ], 
144            "init_perf_level": 0, 
145            "voltage_domain": "system.voltage_domain", 
146            "eventq_index": 0, 
147            "cxx_class": "SrcClockDomain", 
148            "path": "system.cpu_clk_domain", 
149            "type": "SrcClockDomain", 
150            "domain_id": -1
151        }, 
152        "work_end_ckpt_count": 0, 
153        "mem_mode": "timing", 
154        "name": "system", 
155        "init_param": 0, 
156        "p_state_clk_gate_bins": 20, 
157        "load_addr_mask": 1099511627775, 
158        "cpu": [
159            {
160                "do_statistics_insts": true, 
161                "numThreads": 1, 
162                "itb": {
163                    "name": "itb", 
164                    "eventq_index": 0, 
165                    "cxx_class": "RiscvISA::TLB", 
166                    "path": "system.cpu.itb", 
167                    "type": "RiscvTLB", 
168                    "size": 64
169                }, 
170                "system": "system", 
171                "icache": {
172                    "cpu_side": {
173                        "peer": "system.cpu.icache_port", 
174                        "role": "SLAVE"
175                    }, 
176                    "clusivity": "mostly_incl", 
177                    "prefetcher": null, 
178                    "system": "system", 
179                    "write_buffers": 8, 
180                    "response_latency": 2, 
181                    "cxx_class": "Cache", 
182                    "size": 131072, 
183                    "type": "Cache", 
184                    "clk_domain": "system.cpu_clk_domain", 
185                    "max_miss_count": 0, 
186                    "eventq_index": 0, 
187                    "default_p_state": "UNDEFINED", 
188                    "p_state_clk_gate_max": 1000000000000, 
189                    "mem_side": {
190                        "peer": "system.cpu.toL2Bus.slave[0]", 
191                        "role": "MASTER"
192                    }, 
193                    "mshrs": 4, 
194                    "writeback_clean": true, 
195                    "p_state_clk_gate_min": 1000, 
196                    "tags": {
197                        "size": 131072, 
198                        "tag_latency": 2, 
199                        "name": "tags", 
200                        "p_state_clk_gate_min": 1000, 
201                        "eventq_index": 0, 
202                        "p_state_clk_gate_bins": 20, 
203                        "default_p_state": "UNDEFINED", 
204                        "clk_domain": "system.cpu_clk_domain", 
205                        "power_model": null, 
206                        "sequential_access": false, 
207                        "assoc": 2, 
208                        "cxx_class": "LRU", 
209                        "p_state_clk_gate_max": 1000000000000, 
210                        "path": "system.cpu.icache.tags", 
211                        "block_size": 64, 
212                        "type": "LRU", 
213                        "data_latency": 2
214                    }, 
215                    "tgts_per_mshr": 20, 
216                    "demand_mshr_reserve": 1, 
217                    "power_model": null, 
218                    "addr_ranges": [
219                        "0:18446744073709551615:0:0:0:0"
220                    ], 
221                    "is_read_only": true, 
222                    "prefetch_on_access": false, 
223                    "path": "system.cpu.icache", 
224                    "data_latency": 2, 
225                    "tag_latency": 2, 
226                    "name": "icache", 
227                    "p_state_clk_gate_bins": 20, 
228                    "sequential_access": false, 
229                    "assoc": 2
230                }, 
231                "function_trace": false, 
232                "do_checkpoint_insts": true, 
233                "cxx_class": "TimingSimpleCPU", 
234                "max_loads_all_threads": 0, 
235                "clk_domain": "system.cpu_clk_domain", 
236                "function_trace_start": 0, 
237                "cpu_id": 0, 
238                "checker": null, 
239                "eventq_index": 0, 
240                "default_p_state": "UNDEFINED", 
241                "p_state_clk_gate_max": 1000000000000, 
242                "toL2Bus": {
243                    "point_of_coherency": false, 
244                    "system": "system", 
245                    "response_latency": 1, 
246                    "cxx_class": "CoherentXBar", 
247                    "forward_latency": 0, 
248                    "clk_domain": "system.cpu_clk_domain", 
249                    "width": 32, 
250                    "eventq_index": 0, 
251                    "default_p_state": "UNDEFINED", 
252                    "p_state_clk_gate_max": 1000000000000, 
253                    "master": {
254                        "peer": [
255                            "system.cpu.l2cache.cpu_side"
256                        ], 
257                        "role": "MASTER"
258                    }, 
259                    "type": "CoherentXBar", 
260                    "frontend_latency": 1, 
261                    "slave": {
262                        "peer": [
263                            "system.cpu.icache.mem_side", 
264                            "system.cpu.dcache.mem_side"
265                        ], 
266                        "role": "SLAVE"
267                    }, 
268                    "p_state_clk_gate_min": 1000, 
269                    "snoop_filter": {
270                        "name": "snoop_filter", 
271                        "system": "system", 
272                        "max_capacity": 8388608, 
273                        "eventq_index": 0, 
274                        "cxx_class": "SnoopFilter", 
275                        "path": "system.cpu.toL2Bus.snoop_filter", 
276                        "type": "SnoopFilter", 
277                        "lookup_latency": 0
278                    }, 
279                    "power_model": null, 
280                    "path": "system.cpu.toL2Bus", 
281                    "snoop_response_latency": 1, 
282                    "name": "toL2Bus", 
283                    "p_state_clk_gate_bins": 20, 
284                    "use_default_range": false
285                }, 
286                "do_quiesce": true, 
287                "type": "TimingSimpleCPU", 
288                "profile": 0, 
289                "icache_port": {
290                    "peer": "system.cpu.icache.cpu_side", 
291                    "role": "MASTER"
292                }, 
293                "p_state_clk_gate_bins": 20, 
294                "p_state_clk_gate_min": 1000, 
295                "interrupts": [
296                    {
297                        "eventq_index": 0, 
298                        "path": "system.cpu.interrupts", 
299                        "type": "RiscvInterrupts", 
300                        "name": "interrupts", 
301                        "cxx_class": "RiscvISA::Interrupts"
302                    }
303                ], 
304                "dcache_port": {
305                    "peer": "system.cpu.dcache.cpu_side", 
306                    "role": "MASTER"
307                }, 
308                "socket_id": 0, 
309                "power_model": null, 
310                "max_insts_all_threads": 0, 
311                "l2cache": {
312                    "cpu_side": {
313                        "peer": "system.cpu.toL2Bus.master[0]", 
314                        "role": "SLAVE"
315                    }, 
316                    "clusivity": "mostly_incl", 
317                    "prefetcher": null, 
318                    "system": "system", 
319                    "write_buffers": 8, 
320                    "response_latency": 20, 
321                    "cxx_class": "Cache", 
322                    "size": 2097152, 
323                    "type": "Cache", 
324                    "clk_domain": "system.cpu_clk_domain", 
325                    "max_miss_count": 0, 
326                    "eventq_index": 0, 
327                    "default_p_state": "UNDEFINED", 
328                    "p_state_clk_gate_max": 1000000000000, 
329                    "mem_side": {
330                        "peer": "system.membus.slave[1]", 
331                        "role": "MASTER"
332                    }, 
333                    "mshrs": 20, 
334                    "writeback_clean": false, 
335                    "p_state_clk_gate_min": 1000, 
336                    "tags": {
337                        "size": 2097152, 
338                        "tag_latency": 20, 
339                        "name": "tags", 
340                        "p_state_clk_gate_min": 1000, 
341                        "eventq_index": 0, 
342                        "p_state_clk_gate_bins": 20, 
343                        "default_p_state": "UNDEFINED", 
344                        "clk_domain": "system.cpu_clk_domain", 
345                        "power_model": null, 
346                        "sequential_access": false, 
347                        "assoc": 8, 
348                        "cxx_class": "LRU", 
349                        "p_state_clk_gate_max": 1000000000000, 
350                        "path": "system.cpu.l2cache.tags", 
351                        "block_size": 64, 
352                        "type": "LRU", 
353                        "data_latency": 20
354                    }, 
355                    "tgts_per_mshr": 12, 
356                    "demand_mshr_reserve": 1, 
357                    "power_model": null, 
358                    "addr_ranges": [
359                        "0:18446744073709551615:0:0:0:0"
360                    ], 
361                    "is_read_only": false, 
362                    "prefetch_on_access": false, 
363                    "path": "system.cpu.l2cache", 
364                    "data_latency": 20, 
365                    "tag_latency": 20, 
366                    "name": "l2cache", 
367                    "p_state_clk_gate_bins": 20, 
368                    "sequential_access": false, 
369                    "assoc": 8
370                }, 
371                "path": "system.cpu", 
372                "max_loads_any_thread": 0, 
373                "switched_out": false, 
374                "workload": [
375                    {
376                        "uid": 100, 
377                        "pid": 100, 
378                        "kvmInSE": false, 
379                        "cxx_class": "LiveProcess", 
380                        "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64a/insttest", 
381                        "drivers": [], 
382                        "system": "system", 
383                        "gid": 100, 
384                        "eventq_index": 0, 
385                        "env": [], 
386                        "input": "cin", 
387                        "ppid": 99, 
388                        "type": "LiveProcess", 
389                        "cwd": "", 
390                        "simpoint": 0, 
391                        "euid": 100, 
392                        "path": "system.cpu.workload", 
393                        "max_stack_size": 67108864, 
394                        "name": "workload", 
395                        "cmd": [
396                            "insttest"
397                        ], 
398                        "errout": "cerr", 
399                        "useArchPT": false, 
400                        "egid": 100, 
401                        "output": "cout"
402                    }
403                ], 
404                "name": "cpu", 
405                "dtb": {
406                    "name": "dtb", 
407                    "eventq_index": 0, 
408                    "cxx_class": "RiscvISA::TLB", 
409                    "path": "system.cpu.dtb", 
410                    "type": "RiscvTLB", 
411                    "size": 64
412                }, 
413                "simpoint_start_insts": [], 
414                "max_insts_any_thread": 0, 
415                "progress_interval": 0, 
416                "branchPred": null, 
417                "dcache": {
418                    "cpu_side": {
419                        "peer": "system.cpu.dcache_port", 
420                        "role": "SLAVE"
421                    }, 
422                    "clusivity": "mostly_incl", 
423                    "prefetcher": null, 
424                    "system": "system", 
425                    "write_buffers": 8, 
426                    "response_latency": 2, 
427                    "cxx_class": "Cache", 
428                    "size": 262144, 
429                    "type": "Cache", 
430                    "clk_domain": "system.cpu_clk_domain", 
431                    "max_miss_count": 0, 
432                    "eventq_index": 0, 
433                    "default_p_state": "UNDEFINED", 
434                    "p_state_clk_gate_max": 1000000000000, 
435                    "mem_side": {
436                        "peer": "system.cpu.toL2Bus.slave[1]", 
437                        "role": "MASTER"
438                    }, 
439                    "mshrs": 4, 
440                    "writeback_clean": false, 
441                    "p_state_clk_gate_min": 1000, 
442                    "tags": {
443                        "size": 262144, 
444                        "tag_latency": 2, 
445                        "name": "tags", 
446                        "p_state_clk_gate_min": 1000, 
447                        "eventq_index": 0, 
448                        "p_state_clk_gate_bins": 20, 
449                        "default_p_state": "UNDEFINED", 
450                        "clk_domain": "system.cpu_clk_domain", 
451                        "power_model": null, 
452                        "sequential_access": false, 
453                        "assoc": 2, 
454                        "cxx_class": "LRU", 
455                        "p_state_clk_gate_max": 1000000000000, 
456                        "path": "system.cpu.dcache.tags", 
457                        "block_size": 64, 
458                        "type": "LRU", 
459                        "data_latency": 2
460                    }, 
461                    "tgts_per_mshr": 20, 
462                    "demand_mshr_reserve": 1, 
463                    "power_model": null, 
464                    "addr_ranges": [
465                        "0:18446744073709551615:0:0:0:0"
466                    ], 
467                    "is_read_only": false, 
468                    "prefetch_on_access": false, 
469                    "path": "system.cpu.dcache", 
470                    "data_latency": 2, 
471                    "tag_latency": 2, 
472                    "name": "dcache", 
473                    "p_state_clk_gate_bins": 20, 
474                    "sequential_access": false, 
475                    "assoc": 2
476                }, 
477                "isa": [
478                    {
479                        "eventq_index": 0, 
480                        "path": "system.cpu.isa", 
481                        "type": "RiscvISA", 
482                        "name": "isa", 
483                        "cxx_class": "RiscvISA::ISA"
484                    }
485                ], 
486                "tracer": {
487                    "eventq_index": 0, 
488                    "path": "system.cpu.tracer", 
489                    "type": "ExeTracer", 
490                    "name": "tracer", 
491                    "cxx_class": "Trace::ExeTracer"
492                }
493            }
494        ], 
495        "multi_thread": false, 
496        "exit_on_work_items": false, 
497        "work_item_id": -1, 
498        "num_work_ids": 16
499    }, 
500    "time_sync_period": 100000000000, 
501    "eventq_index": 0, 
502    "time_sync_spin_threshold": 100000000, 
503    "cxx_class": "Root", 
504    "path": "root", 
505    "time_sync_enable": false, 
506    "type": "Root", 
507    "full_system": false
508}