stats.txt revision 11440:76b5639162af
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25580500 # Number of ticks simulated 5final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 50796 # Simulator instruction rate (inst/s) 8host_op_rate 50792 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 98611945 # Simulator tick rate (ticks/s) 10host_mem_usage 229596 # Number of bytes of host memory used 11host_seconds 0.25 # Real time elapsed on the host 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory 18system.physmem.bytes_read::total 61504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39680 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 620 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 961 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1551181564 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 853149860 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2404331424 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1551181564 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1551181564 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1551181564 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 853149860 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2404331424 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 962 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 962 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 61568 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 61568 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 83 # Per bank write bursts 45system.physmem.perBankRdBursts::1 150 # Per bank write bursts 46system.physmem.perBankRdBursts::2 78 # Per bank write bursts 47system.physmem.perBankRdBursts::3 59 # Per bank write bursts 48system.physmem.perBankRdBursts::4 86 # Per bank write bursts 49system.physmem.perBankRdBursts::5 46 # Per bank write bursts 50system.physmem.perBankRdBursts::6 32 # Per bank write bursts 51system.physmem.perBankRdBursts::7 50 # Per bank write bursts 52system.physmem.perBankRdBursts::8 41 # Per bank write bursts 53system.physmem.perBankRdBursts::9 37 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 34 # Per bank write bursts 56system.physmem.perBankRdBursts::12 15 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 67 # Per bank write bursts 59system.physmem.perBankRdBursts::15 36 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 25549500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 962 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 350 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 315 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 281.722488 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 176.924618 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 290.527007 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 69 33.01% 33.01% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 64 30.62% 63.64% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 20 9.57% 73.21% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 12 5.74% 78.95% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 11 5.26% 84.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 8 3.83% 88.04% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 9 4.31% 92.34% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 4 1.91% 94.26% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 12 5.74% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation 203system.physmem.totQLat 12704750 # Total ticks spent queuing 204system.physmem.totMemAccLat 30742250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 4810000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 13206.60 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 31956.60 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2406.83 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2406.83 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 18.80 # Data bus utilization in percentage 215system.physmem.busUtilRead 18.80 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 2.38 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 743 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 26558.73 # Average gap between requests 224system.physmem.pageHitRate 77.23 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 824040 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 449625 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 4453800 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 23400705 # Total energy per rank (pJ) 233system.physmem_0.averagePower 990.768140 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 694500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 733320 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 400125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 2683200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 15873930 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 21463005 # Total energy per rank (pJ) 247system.physmem_1.averagePower 908.727388 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 326750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 4883 # Number of BP lookups 254system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 3812 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 1143 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 29.984260 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 681 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 53 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 814 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 150 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 664 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dtb.fetch_hits 0 # ITB hits 268system.cpu.dtb.fetch_misses 0 # ITB misses 269system.cpu.dtb.fetch_acv 0 # ITB acv 270system.cpu.dtb.fetch_accesses 0 # ITB accesses 271system.cpu.dtb.read_hits 4166 # DTB read hits 272system.cpu.dtb.read_misses 75 # DTB read misses 273system.cpu.dtb.read_acv 0 # DTB read access violations 274system.cpu.dtb.read_accesses 4241 # DTB read accesses 275system.cpu.dtb.write_hits 1988 # DTB write hits 276system.cpu.dtb.write_misses 49 # DTB write misses 277system.cpu.dtb.write_acv 0 # DTB write access violations 278system.cpu.dtb.write_accesses 2037 # DTB write accesses 279system.cpu.dtb.data_hits 6154 # DTB hits 280system.cpu.dtb.data_misses 124 # DTB misses 281system.cpu.dtb.data_acv 0 # DTB access violations 282system.cpu.dtb.data_accesses 6278 # DTB accesses 283system.cpu.itb.fetch_hits 3823 # ITB hits 284system.cpu.itb.fetch_misses 51 # ITB misses 285system.cpu.itb.fetch_acv 0 # ITB acv 286system.cpu.itb.fetch_accesses 3874 # ITB accesses 287system.cpu.itb.read_hits 0 # DTB read hits 288system.cpu.itb.read_misses 0 # DTB read misses 289system.cpu.itb.read_acv 0 # DTB read access violations 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_acv 0 # DTB write access violations 294system.cpu.itb.write_accesses 0 # DTB write accesses 295system.cpu.itb.data_hits 0 # DTB hits 296system.cpu.itb.data_misses 0 # DTB misses 297system.cpu.itb.data_acv 0 # DTB access violations 298system.cpu.itb.data_accesses 0 # DTB accesses 299system.cpu.workload0.num_syscalls 17 # Number of system calls 300system.cpu.workload1.num_syscalls 17 # Number of system calls 301system.cpu.numCycles 51162 # number of cpu cycles simulated 302system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 303system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 304system.cpu.fetch.icacheStallCycles 749 # Number of cycles fetch is stalled on an Icache miss 305system.cpu.fetch.Insts 28166 # Number of instructions fetch has processed 306system.cpu.fetch.Branches 4883 # Number of branches that fetch encountered 307system.cpu.fetch.predictedBranches 1974 # Number of branches that fetch has predicted taken 308system.cpu.fetch.Cycles 9785 # Number of cycles fetch has run and was not squashing or blocked 309system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing 310system.cpu.fetch.MiscStallCycles 559 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 311system.cpu.fetch.CacheLines 3823 # Number of cache lines fetched 312system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed 313system.cpu.fetch.rateDist::samples 26518 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::mean 1.062146 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::stdev 2.446390 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::0 21410 80.74% 80.74% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::1 517 1.95% 82.69% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::2 399 1.50% 84.19% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::3 426 1.61% 85.80% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::4 581 2.19% 87.99% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::5 343 1.29% 89.28% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::6 470 1.77% 91.06% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::7 262 0.99% 92.04% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::8 2110 7.96% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::total 26518 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.branchRate 0.095442 # Number of branch fetches per cycle 331system.cpu.fetch.rate 0.550526 # Number of inst fetches per cycle 332system.cpu.decode.IdleCycles 35549 # Number of cycles decode is idle 333system.cpu.decode.BlockedCycles 11706 # Number of cycles decode is blocked 334system.cpu.decode.RunCycles 4004 # Number of cycles decode is running 335system.cpu.decode.UnblockCycles 486 # Number of cycles decode is unblocking 336system.cpu.decode.SquashCycles 721 # Number of cycles decode is squashing 337system.cpu.decode.BranchResolved 379 # Number of times decode resolved a branch 338system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction 339system.cpu.decode.DecodedInsts 24714 # Number of instructions handled by decode 340system.cpu.decode.SquashedInsts 389 # Number of squashed instructions handled by decode 341system.cpu.rename.SquashCycles 721 # Number of cycles rename is squashing 342system.cpu.rename.IdleCycles 35923 # Number of cycles rename is idle 343system.cpu.rename.BlockCycles 4419 # Number of cycles rename is blocking 344system.cpu.rename.serializeStallCycles 1518 # count of cycles rename stalled for serializing inst 345system.cpu.rename.RunCycles 4115 # Number of cycles rename is running 346system.cpu.rename.UnblockCycles 5770 # Number of cycles rename is unblocking 347system.cpu.rename.RenamedInsts 23686 # Number of instructions processed by rename 348system.cpu.rename.ROBFullEvents 47 # Number of times rename has blocked due to ROB full 349system.cpu.rename.IQFullEvents 451 # Number of times rename has blocked due to IQ full 350system.cpu.rename.LQFullEvents 687 # Number of times rename has blocked due to LQ full 351system.cpu.rename.SQFullEvents 4626 # Number of times rename has blocked due to SQ full 352system.cpu.rename.RenamedOperands 17749 # Number of destination operands rename has renamed 353system.cpu.rename.RenameLookups 29662 # Number of register rename lookups that rename has made 354system.cpu.rename.int_rename_lookups 29644 # Number of integer rename lookups 355system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 356system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed 357system.cpu.rename.UndoneMaps 8595 # Number of HB maps that are undone due to squashing 358system.cpu.rename.serializingInsts 57 # count of serializing insts renamed 359system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed 360system.cpu.rename.skidInsts 1784 # count of insts added to the skid buffer 361system.cpu.memDep0.insertedLoads 2582 # Number of loads inserted to the mem dependence unit. 362system.cpu.memDep0.insertedStores 1268 # Number of stores inserted to the mem dependence unit. 363system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. 364system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 365system.cpu.memDep1.insertedLoads 1972 # Number of loads inserted to the mem dependence unit. 366system.cpu.memDep1.insertedStores 1081 # Number of stores inserted to the mem dependence unit. 367system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. 368system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 369system.cpu.iq.iqInstsAdded 21922 # Number of instructions added to the IQ (excludes non-spec) 370system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ 371system.cpu.iq.iqInstsIssued 19305 # Number of instructions issued 372system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued 373system.cpu.iq.iqSquashedInstsExamined 9201 # Number of squashed instructions iterated over during squash; mainly for profiling 374system.cpu.iq.iqSquashedOperandsExamined 4899 # Number of squashed operands that are examined and possibly removed from graph 375system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 376system.cpu.iq.issued_per_cycle::samples 26518 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::mean 0.727996 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::stdev 1.455439 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::0 19215 72.46% 72.46% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::1 2319 8.75% 81.21% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::2 1762 6.64% 87.85% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::3 1149 4.33% 92.18% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::4 1009 3.80% 95.99% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::5 611 2.30% 98.29% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::6 303 1.14% 99.43% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::7 94 0.35% 99.79% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::8 56 0.21% 100.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::total 26518 # Number of insts issued each cycle 393system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntAlu 25 8.33% 8.33% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntMult 0 0.00% 8.33% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntDiv 0 0.00% 8.33% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.33% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.33% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.33% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMult 0 0.00% 8.33% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.33% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.33% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.33% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.33% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.33% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.33% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.33% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.33% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMult 0 0.00% 8.33% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.33% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShift 0 0.00% 8.33% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.33% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.33% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.33% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.33% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.33% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.33% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.33% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.33% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.33% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.33% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.33% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemRead 198 66.00% 74.33% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemWrite 77 25.67% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 428system.cpu.iq.FU_type_0::IntAlu 6801 65.70% 65.72% # Type of FU issued 429system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.73% # Type of FU issued 430system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.73% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.75% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.75% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.75% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.75% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.75% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.75% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.75% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.75% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.75% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.75% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.75% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.75% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued 457system.cpu.iq.FU_type_0::MemRead 2445 23.62% 89.36% # Type of FU issued 458system.cpu.iq.FU_type_0::MemWrite 1101 10.64% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::total 10352 # Type of FU issued 462system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 463system.cpu.iq.FU_type_1::IntAlu 5921 66.13% 66.16% # Type of FU issued 464system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued 465system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued 466system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued 467system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued 468system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued 469system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued 470system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued 471system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued 472system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued 473system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued 474system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued 475system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued 476system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued 477system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued 478system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued 479system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued 480system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued 481system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued 482system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued 483system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued 484system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued 485system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued 486system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued 487system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued 488system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued 489system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued 490system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued 491system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued 492system.cpu.iq.FU_type_1::MemRead 2023 22.60% 88.79% # Type of FU issued 493system.cpu.iq.FU_type_1::MemWrite 1004 11.21% 100.00% # Type of FU issued 494system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 495system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 496system.cpu.iq.FU_type_1::total 8953 # Type of FU issued 497system.cpu.iq.FU_type::total 19305 0.00% 0.00% # Type of FU issued 498system.cpu.iq.rate 0.377331 # Inst issue rate 499system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested 500system.cpu.iq.fu_busy_cnt::1 140 # FU busy when requested 501system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested 502system.cpu.iq.fu_busy_rate::0 0.008288 # FU busy rate (busy events/executed inst) 503system.cpu.iq.fu_busy_rate::1 0.007252 # FU busy rate (busy events/executed inst) 504system.cpu.iq.fu_busy_rate::total 0.015540 # FU busy rate (busy events/executed inst) 505system.cpu.iq.int_inst_queue_reads 65432 # Number of integer instruction queue reads 506system.cpu.iq.int_inst_queue_writes 31184 # Number of integer instruction queue writes 507system.cpu.iq.int_inst_queue_wakeup_accesses 17495 # Number of integer instruction queue wakeup accesses 508system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 509system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 510system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 511system.cpu.iq.int_alu_accesses 19579 # Number of integer alu accesses 512system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 513system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores 514system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 515system.cpu.iew.lsq.thread0.squashedLoads 1397 # Number of loads squashed 516system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 517system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 518system.cpu.iew.lsq.thread0.squashedStores 403 # Number of stores squashed 519system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 520system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 521system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 522system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked 523system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores 524system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 525system.cpu.iew.lsq.thread1.squashedLoads 787 # Number of loads squashed 526system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 527system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations 528system.cpu.iew.lsq.thread1.squashedStores 216 # Number of stores squashed 529system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 530system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 531system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 532system.cpu.iew.lsq.thread1.cacheBlocked 280 # Number of times an access to memory failed due to the cache being blocked 533system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 534system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing 535system.cpu.iew.iewBlockCycles 2770 # Number of cycles IEW is blocking 536system.cpu.iew.iewUnblockCycles 755 # Number of cycles IEW is unblocking 537system.cpu.iew.iewDispatchedInsts 22107 # Number of instructions dispatched to IQ 538system.cpu.iew.iewDispSquashedInsts 169 # Number of squashed instructions skipped by dispatch 539system.cpu.iew.iewDispLoadInsts 4554 # Number of dispatched load instructions 540system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions 541system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions 542system.cpu.iew.iewIQFullEvents 22 # Number of times the IQ has become full, causing a stall 543system.cpu.iew.iewLSQFullEvents 722 # Number of times the LSQ has become full, causing a stall 544system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations 545system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly 546system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly 547system.cpu.iew.branchMispredicts 771 # Number of branch mispredicts detected at execute 548system.cpu.iew.iewExecutedInsts 18606 # Number of executed instructions 549system.cpu.iew.iewExecLoadInsts::0 2294 # Number of load instructions executed 550system.cpu.iew.iewExecLoadInsts::1 1956 # Number of load instructions executed 551system.cpu.iew.iewExecLoadInsts::total 4250 # Number of load instructions executed 552system.cpu.iew.iewExecSquashedInsts 699 # Number of squashed instructions skipped in execute 553system.cpu.iew.exec_swp::0 0 # number of swp insts executed 554system.cpu.iew.exec_swp::1 0 # number of swp insts executed 555system.cpu.iew.exec_swp::total 0 # number of swp insts executed 556system.cpu.iew.exec_nop::0 68 # number of nop insts executed 557system.cpu.iew.exec_nop::1 67 # number of nop insts executed 558system.cpu.iew.exec_nop::total 135 # number of nop insts executed 559system.cpu.iew.exec_refs::0 3353 # number of memory reference insts executed 560system.cpu.iew.exec_refs::1 2946 # number of memory reference insts executed 561system.cpu.iew.exec_refs::total 6299 # number of memory reference insts executed 562system.cpu.iew.exec_branches::0 1561 # Number of branches executed 563system.cpu.iew.exec_branches::1 1400 # Number of branches executed 564system.cpu.iew.exec_branches::total 2961 # Number of branches executed 565system.cpu.iew.exec_stores::0 1059 # Number of stores executed 566system.cpu.iew.exec_stores::1 990 # Number of stores executed 567system.cpu.iew.exec_stores::total 2049 # Number of stores executed 568system.cpu.iew.exec_rate 0.363668 # Inst execution rate 569system.cpu.iew.wb_sent::0 9443 # cumulative count of insts sent to commit 570system.cpu.iew.wb_sent::1 8345 # cumulative count of insts sent to commit 571system.cpu.iew.wb_sent::total 17788 # cumulative count of insts sent to commit 572system.cpu.iew.wb_count::0 9266 # cumulative count of insts written-back 573system.cpu.iew.wb_count::1 8249 # cumulative count of insts written-back 574system.cpu.iew.wb_count::total 17515 # cumulative count of insts written-back 575system.cpu.iew.wb_producers::0 4880 # num instructions producing a value 576system.cpu.iew.wb_producers::1 4386 # num instructions producing a value 577system.cpu.iew.wb_producers::total 9266 # num instructions producing a value 578system.cpu.iew.wb_consumers::0 6580 # num instructions consuming a value 579system.cpu.iew.wb_consumers::1 5911 # num instructions consuming a value 580system.cpu.iew.wb_consumers::total 12491 # num instructions consuming a value 581system.cpu.iew.wb_rate::0 0.181111 # insts written-back per cycle 582system.cpu.iew.wb_rate::1 0.161233 # insts written-back per cycle 583system.cpu.iew.wb_rate::total 0.342344 # insts written-back per cycle 584system.cpu.iew.wb_fanout::0 0.741641 # average fanout of values written-back 585system.cpu.iew.wb_fanout::1 0.742006 # average fanout of values written-back 586system.cpu.iew.wb_fanout::total 0.741814 # average fanout of values written-back 587system.cpu.commit.commitSquashedInsts 9276 # The number of squashed insts skipped by commit 588system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 589system.cpu.commit.branchMispredicts 642 # The number of times a branch was mispredicted 590system.cpu.commit.committed_per_cycle::samples 26498 # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::mean 0.483206 # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::stdev 1.376058 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::0 21430 80.87% 80.87% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::1 2543 9.60% 90.47% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::2 900 3.40% 93.87% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::3 463 1.75% 95.61% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::4 308 1.16% 96.78% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::5 165 0.62% 97.40% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::6 178 0.67% 98.07% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::7 141 0.53% 98.60% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::8 370 1.40% 100.00% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::total 26498 # Number of insts commited each cycle 607system.cpu.commit.committedInsts::0 6402 # Number of instructions committed 608system.cpu.commit.committedInsts::1 6402 # Number of instructions committed 609system.cpu.commit.committedInsts::total 12804 # Number of instructions committed 610system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed 611system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed 612system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed 613system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 614system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 615system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 616system.cpu.commit.refs::0 2050 # Number of memory references committed 617system.cpu.commit.refs::1 2050 # Number of memory references committed 618system.cpu.commit.refs::total 4100 # Number of memory references committed 619system.cpu.commit.loads::0 1185 # Number of loads committed 620system.cpu.commit.loads::1 1185 # Number of loads committed 621system.cpu.commit.loads::total 2370 # Number of loads committed 622system.cpu.commit.membars::0 0 # Number of memory barriers committed 623system.cpu.commit.membars::1 0 # Number of memory barriers committed 624system.cpu.commit.membars::total 0 # Number of memory barriers committed 625system.cpu.commit.branches::0 1056 # Number of branches committed 626system.cpu.commit.branches::1 1056 # Number of branches committed 627system.cpu.commit.branches::total 2112 # Number of branches committed 628system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 629system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 630system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 631system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions. 632system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions. 633system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions. 634system.cpu.commit.function_calls::0 127 # Number of function calls committed. 635system.cpu.commit.function_calls::1 127 # Number of function calls committed. 636system.cpu.commit.function_calls::total 254 # Number of function calls committed. 637system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 638system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction 639system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction 640system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction 641system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction 642system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction 643system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction 644system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction 645system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 667system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 668system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 669system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 670system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 671system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 672system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction 673system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction 674system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction 675system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction 676system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction 677system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction 678system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction 679system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction 680system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction 681system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 682system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction 683system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 684system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction 685system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction 686system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction 687system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction 688system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction 689system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 690system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction 691system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 692system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 693system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 694system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 695system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 696system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 697system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 698system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 699system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 700system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 701system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 702system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction 703system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_1::total 6402 # Class of committed instruction 707system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction 708system.cpu.commit.bw_lim_events 370 # number cycles where commit BW limit reached 709system.cpu.rob.rob_reads 113336 # The number of ROB reads 710system.cpu.rob.rob_writes 45860 # The number of ROB writes 711system.cpu.timesIdled 410 # Number of times that the entire CPU went into an idle state and unscheduled itself 712system.cpu.idleCycles 24644 # Total number of cycles that the CPU has spent unscheduled due to idling 713system.cpu.committedInsts::0 6385 # Number of Instructions Simulated 714system.cpu.committedInsts::1 6385 # Number of Instructions Simulated 715system.cpu.committedInsts::total 12770 # Number of Instructions Simulated 716system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated 717system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated 718system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated 719system.cpu.cpi::0 8.012843 # CPI: Cycles Per Instruction 720system.cpu.cpi::1 8.012843 # CPI: Cycles Per Instruction 721system.cpu.cpi_total 4.006421 # CPI: Total CPI of All Threads 722system.cpu.ipc::0 0.124800 # IPC: Instructions Per Cycle 723system.cpu.ipc::1 0.124800 # IPC: Instructions Per Cycle 724system.cpu.ipc_total 0.249599 # IPC: Total IPC of All Threads 725system.cpu.int_regfile_reads 23495 # number of integer regfile reads 726system.cpu.int_regfile_writes 13160 # number of integer regfile writes 727system.cpu.fp_regfile_reads 16 # number of floating regfile reads 728system.cpu.fp_regfile_writes 4 # number of floating regfile writes 729system.cpu.misc_regfile_reads 2 # number of misc regfile reads 730system.cpu.misc_regfile_writes 2 # number of misc regfile writes 731system.cpu.dcache.tags.replacements::0 0 # number of replacements 732system.cpu.dcache.tags.replacements::1 0 # number of replacements 733system.cpu.dcache.tags.replacements::total 0 # number of replacements 734system.cpu.dcache.tags.tagsinuse 216.394211 # Cycle average of tags in use 735system.cpu.dcache.tags.total_refs 4263 # Total number of references to valid blocks. 736system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks. 737system.cpu.dcache.tags.avg_refs 12.501466 # Average number of references to valid blocks. 738system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 739system.cpu.dcache.tags.occ_blocks::cpu.data 216.394211 # Average occupied blocks per requestor 740system.cpu.dcache.tags.occ_percent::cpu.data 0.052831 # Average percentage of cache occupancy 741system.cpu.dcache.tags.occ_percent::total 0.052831 # Average percentage of cache occupancy 742system.cpu.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 743system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 744system.cpu.dcache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id 745system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id 746system.cpu.dcache.tags.tag_accesses 10889 # Number of tag accesses 747system.cpu.dcache.tags.data_accesses 10889 # Number of data accesses 748system.cpu.dcache.ReadReq_hits::cpu.data 3245 # number of ReadReq hits 749system.cpu.dcache.ReadReq_hits::total 3245 # number of ReadReq hits 750system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits 751system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits 752system.cpu.dcache.demand_hits::cpu.data 4263 # number of demand (read+write) hits 753system.cpu.dcache.demand_hits::total 4263 # number of demand (read+write) hits 754system.cpu.dcache.overall_hits::cpu.data 4263 # number of overall hits 755system.cpu.dcache.overall_hits::total 4263 # number of overall hits 756system.cpu.dcache.ReadReq_misses::cpu.data 299 # number of ReadReq misses 757system.cpu.dcache.ReadReq_misses::total 299 # number of ReadReq misses 758system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses 759system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses 760system.cpu.dcache.demand_misses::cpu.data 1011 # number of demand (read+write) misses 761system.cpu.dcache.demand_misses::total 1011 # number of demand (read+write) misses 762system.cpu.dcache.overall_misses::cpu.data 1011 # number of overall misses 763system.cpu.dcache.overall_misses::total 1011 # number of overall misses 764system.cpu.dcache.ReadReq_miss_latency::cpu.data 23300000 # number of ReadReq miss cycles 765system.cpu.dcache.ReadReq_miss_latency::total 23300000 # number of ReadReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::cpu.data 52494934 # number of WriteReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::total 52494934 # number of WriteReq miss cycles 768system.cpu.dcache.demand_miss_latency::cpu.data 75794934 # number of demand (read+write) miss cycles 769system.cpu.dcache.demand_miss_latency::total 75794934 # number of demand (read+write) miss cycles 770system.cpu.dcache.overall_miss_latency::cpu.data 75794934 # number of overall miss cycles 771system.cpu.dcache.overall_miss_latency::total 75794934 # number of overall miss cycles 772system.cpu.dcache.ReadReq_accesses::cpu.data 3544 # number of ReadReq accesses(hits+misses) 773system.cpu.dcache.ReadReq_accesses::total 3544 # number of ReadReq accesses(hits+misses) 774system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 775system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 776system.cpu.dcache.demand_accesses::cpu.data 5274 # number of demand (read+write) accesses 777system.cpu.dcache.demand_accesses::total 5274 # number of demand (read+write) accesses 778system.cpu.dcache.overall_accesses::cpu.data 5274 # number of overall (read+write) accesses 779system.cpu.dcache.overall_accesses::total 5274 # number of overall (read+write) accesses 780system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084368 # miss rate for ReadReq accesses 781system.cpu.dcache.ReadReq_miss_rate::total 0.084368 # miss rate for ReadReq accesses 782system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses 783system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses 784system.cpu.dcache.demand_miss_rate::cpu.data 0.191695 # miss rate for demand accesses 785system.cpu.dcache.demand_miss_rate::total 0.191695 # miss rate for demand accesses 786system.cpu.dcache.overall_miss_rate::cpu.data 0.191695 # miss rate for overall accesses 787system.cpu.dcache.overall_miss_rate::total 0.191695 # miss rate for overall accesses 788system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77926.421405 # average ReadReq miss latency 789system.cpu.dcache.ReadReq_avg_miss_latency::total 77926.421405 # average ReadReq miss latency 790system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73728.839888 # average WriteReq miss latency 791system.cpu.dcache.WriteReq_avg_miss_latency::total 73728.839888 # average WriteReq miss latency 792system.cpu.dcache.demand_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency 793system.cpu.dcache.demand_avg_miss_latency::total 74970.261128 # average overall miss latency 794system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency 795system.cpu.dcache.overall_avg_miss_latency::total 74970.261128 # average overall miss latency 796system.cpu.dcache.blocked_cycles::no_mshrs 5977 # number of cycles access was blocked 797system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked 799system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 800system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked 801system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 802system.cpu.dcache.fast_writes 0 # number of fast writes performed 803system.cpu.dcache.cache_copies 0 # number of cache copies performed 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits 808system.cpu.dcache.demand_mshr_hits::cpu.data 669 # number of demand (read+write) MSHR hits 809system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits 810system.cpu.dcache.overall_mshr_hits::cpu.data 669 # number of overall MSHR hits 811system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits 812system.cpu.dcache.ReadReq_mshr_misses::cpu.data 196 # number of ReadReq MSHR misses 813system.cpu.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses 814system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 815system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 816system.cpu.dcache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses 817system.cpu.dcache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 818system.cpu.dcache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses 819system.cpu.dcache.overall_mshr_misses::total 342 # number of overall MSHR misses 820system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17233500 # number of ReadReq MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_latency::total 17233500 # number of ReadReq MSHR miss cycles 822system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12825986 # number of WriteReq MSHR miss cycles 823system.cpu.dcache.WriteReq_mshr_miss_latency::total 12825986 # number of WriteReq MSHR miss cycles 824system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30059486 # number of demand (read+write) MSHR miss cycles 825system.cpu.dcache.demand_mshr_miss_latency::total 30059486 # number of demand (read+write) MSHR miss cycles 826system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30059486 # number of overall MSHR miss cycles 827system.cpu.dcache.overall_mshr_miss_latency::total 30059486 # number of overall MSHR miss cycles 828system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055305 # mshr miss rate for ReadReq accesses 829system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055305 # mshr miss rate for ReadReq accesses 830system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 831system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 832system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for demand accesses 833system.cpu.dcache.demand_mshr_miss_rate::total 0.064846 # mshr miss rate for demand accesses 834system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for overall accesses 835system.cpu.dcache.overall_mshr_miss_rate::total 0.064846 # mshr miss rate for overall accesses 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408 # average ReadReq mshr miss latency 837system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408 # average ReadReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178 # average WriteReq mshr miss latency 839system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178 # average WriteReq mshr miss latency 840system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency 842system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency 844system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 845system.cpu.icache.tags.replacements::0 7 # number of replacements 846system.cpu.icache.tags.replacements::1 0 # number of replacements 847system.cpu.icache.tags.replacements::total 7 # number of replacements 848system.cpu.icache.tags.tagsinuse 317.276824 # Cycle average of tags in use 849system.cpu.icache.tags.total_refs 2916 # Total number of references to valid blocks. 850system.cpu.icache.tags.sampled_refs 623 # Sample count of references to valid blocks. 851system.cpu.icache.tags.avg_refs 4.680578 # Average number of references to valid blocks. 852system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 853system.cpu.icache.tags.occ_blocks::cpu.inst 317.276824 # Average occupied blocks per requestor 854system.cpu.icache.tags.occ_percent::cpu.inst 0.154920 # Average percentage of cache occupancy 855system.cpu.icache.tags.occ_percent::total 0.154920 # Average percentage of cache occupancy 856system.cpu.icache.tags.occ_task_id_blocks::1024 616 # Occupied blocks per task id 857system.cpu.icache.tags.age_task_id_blocks_1024::0 237 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id 859system.cpu.icache.tags.occ_task_id_percent::1024 0.300781 # Percentage of cache occupancy per task id 860system.cpu.icache.tags.tag_accesses 8261 # Number of tag accesses 861system.cpu.icache.tags.data_accesses 8261 # Number of data accesses 862system.cpu.icache.ReadReq_hits::cpu.inst 2916 # number of ReadReq hits 863system.cpu.icache.ReadReq_hits::total 2916 # number of ReadReq hits 864system.cpu.icache.demand_hits::cpu.inst 2916 # number of demand (read+write) hits 865system.cpu.icache.demand_hits::total 2916 # number of demand (read+write) hits 866system.cpu.icache.overall_hits::cpu.inst 2916 # number of overall hits 867system.cpu.icache.overall_hits::total 2916 # number of overall hits 868system.cpu.icache.ReadReq_misses::cpu.inst 903 # number of ReadReq misses 869system.cpu.icache.ReadReq_misses::total 903 # number of ReadReq misses 870system.cpu.icache.demand_misses::cpu.inst 903 # number of demand (read+write) misses 871system.cpu.icache.demand_misses::total 903 # number of demand (read+write) misses 872system.cpu.icache.overall_misses::cpu.inst 903 # number of overall misses 873system.cpu.icache.overall_misses::total 903 # number of overall misses 874system.cpu.icache.ReadReq_miss_latency::cpu.inst 69936495 # number of ReadReq miss cycles 875system.cpu.icache.ReadReq_miss_latency::total 69936495 # number of ReadReq miss cycles 876system.cpu.icache.demand_miss_latency::cpu.inst 69936495 # number of demand (read+write) miss cycles 877system.cpu.icache.demand_miss_latency::total 69936495 # number of demand (read+write) miss cycles 878system.cpu.icache.overall_miss_latency::cpu.inst 69936495 # number of overall miss cycles 879system.cpu.icache.overall_miss_latency::total 69936495 # number of overall miss cycles 880system.cpu.icache.ReadReq_accesses::cpu.inst 3819 # number of ReadReq accesses(hits+misses) 881system.cpu.icache.ReadReq_accesses::total 3819 # number of ReadReq accesses(hits+misses) 882system.cpu.icache.demand_accesses::cpu.inst 3819 # number of demand (read+write) accesses 883system.cpu.icache.demand_accesses::total 3819 # number of demand (read+write) accesses 884system.cpu.icache.overall_accesses::cpu.inst 3819 # number of overall (read+write) accesses 885system.cpu.icache.overall_accesses::total 3819 # number of overall (read+write) accesses 886system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.236449 # miss rate for ReadReq accesses 887system.cpu.icache.ReadReq_miss_rate::total 0.236449 # miss rate for ReadReq accesses 888system.cpu.icache.demand_miss_rate::cpu.inst 0.236449 # miss rate for demand accesses 889system.cpu.icache.demand_miss_rate::total 0.236449 # miss rate for demand accesses 890system.cpu.icache.overall_miss_rate::cpu.inst 0.236449 # miss rate for overall accesses 891system.cpu.icache.overall_miss_rate::total 0.236449 # miss rate for overall accesses 892system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77449.053156 # average ReadReq miss latency 893system.cpu.icache.ReadReq_avg_miss_latency::total 77449.053156 # average ReadReq miss latency 894system.cpu.icache.demand_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency 895system.cpu.icache.demand_avg_miss_latency::total 77449.053156 # average overall miss latency 896system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency 897system.cpu.icache.overall_avg_miss_latency::total 77449.053156 # average overall miss latency 898system.cpu.icache.blocked_cycles::no_mshrs 3083 # number of cycles access was blocked 899system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 900system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked 901system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 902system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked 903system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 904system.cpu.icache.fast_writes 0 # number of fast writes performed 905system.cpu.icache.cache_copies 0 # number of cache copies performed 906system.cpu.icache.writebacks::writebacks 7 # number of writebacks 907system.cpu.icache.writebacks::total 7 # number of writebacks 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits 914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses 915system.cpu.icache.ReadReq_mshr_misses::total 623 # number of ReadReq MSHR misses 916system.cpu.icache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses 917system.cpu.icache.demand_mshr_misses::total 623 # number of demand (read+write) MSHR misses 918system.cpu.icache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses 919system.cpu.icache.overall_mshr_misses::total 623 # number of overall MSHR misses 920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50404995 # number of ReadReq MSHR miss cycles 921system.cpu.icache.ReadReq_mshr_miss_latency::total 50404995 # number of ReadReq MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50404995 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::total 50404995 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50404995 # number of overall MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::total 50404995 # number of overall MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for ReadReq accesses 927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163132 # mshr miss rate for ReadReq accesses 928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for demand accesses 929system.cpu.icache.demand_mshr_miss_rate::total 0.163132 # mshr miss rate for demand accesses 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.163132 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.l2cache.tags.replacements::0 0 # number of replacements 940system.cpu.l2cache.tags.replacements::1 0 # number of replacements 941system.cpu.l2cache.tags.replacements::total 0 # number of replacements 942system.cpu.l2cache.tags.tagsinuse 438.773475 # Cycle average of tags in use 943system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 944system.cpu.l2cache.tags.sampled_refs 815 # Sample count of references to valid blocks. 945system.cpu.l2cache.tags.avg_refs 0.012270 # Average number of references to valid blocks. 946system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 947system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.771557 # Average occupied blocks per requestor 948system.cpu.l2cache.tags.occ_blocks::cpu.data 121.001918 # Average occupied blocks per requestor 949system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009698 # Average percentage of cache occupancy 950system.cpu.l2cache.tags.occ_percent::cpu.data 0.003693 # Average percentage of cache occupancy 951system.cpu.l2cache.tags.occ_percent::total 0.013390 # Average percentage of cache occupancy 952system.cpu.l2cache.tags.occ_task_id_blocks::1024 815 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id 955system.cpu.l2cache.tags.occ_task_id_percent::1024 0.024872 # Percentage of cache occupancy per task id 956system.cpu.l2cache.tags.tag_accesses 8737 # Number of tag accesses 957system.cpu.l2cache.tags.data_accesses 8737 # Number of data accesses 958system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 959system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 960system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 961system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 962system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 963system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 964system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 965system.cpu.l2cache.overall_hits::total 3 # number of overall hits 966system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 967system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 968system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 620 # number of ReadCleanReq misses 969system.cpu.l2cache.ReadCleanReq_misses::total 620 # number of ReadCleanReq misses 970system.cpu.l2cache.ReadSharedReq_misses::cpu.data 196 # number of ReadSharedReq misses 971system.cpu.l2cache.ReadSharedReq_misses::total 196 # number of ReadSharedReq misses 972system.cpu.l2cache.demand_misses::cpu.inst 620 # number of demand (read+write) misses 973system.cpu.l2cache.demand_misses::cpu.data 342 # number of demand (read+write) misses 974system.cpu.l2cache.demand_misses::total 962 # number of demand (read+write) misses 975system.cpu.l2cache.overall_misses::cpu.inst 620 # number of overall misses 976system.cpu.l2cache.overall_misses::cpu.data 342 # number of overall misses 977system.cpu.l2cache.overall_misses::total 962 # number of overall misses 978system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12598500 # number of ReadExReq miss cycles 979system.cpu.l2cache.ReadExReq_miss_latency::total 12598500 # number of ReadExReq miss cycles 980system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 49432000 # number of ReadCleanReq miss cycles 981system.cpu.l2cache.ReadCleanReq_miss_latency::total 49432000 # number of ReadCleanReq miss cycles 982system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16931000 # number of ReadSharedReq miss cycles 983system.cpu.l2cache.ReadSharedReq_miss_latency::total 16931000 # number of ReadSharedReq miss cycles 984system.cpu.l2cache.demand_miss_latency::cpu.inst 49432000 # number of demand (read+write) miss cycles 985system.cpu.l2cache.demand_miss_latency::cpu.data 29529500 # number of demand (read+write) miss cycles 986system.cpu.l2cache.demand_miss_latency::total 78961500 # number of demand (read+write) miss cycles 987system.cpu.l2cache.overall_miss_latency::cpu.inst 49432000 # number of overall miss cycles 988system.cpu.l2cache.overall_miss_latency::cpu.data 29529500 # number of overall miss cycles 989system.cpu.l2cache.overall_miss_latency::total 78961500 # number of overall miss cycles 990system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) 991system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) 992system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 993system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 994system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 623 # number of ReadCleanReq accesses(hits+misses) 995system.cpu.l2cache.ReadCleanReq_accesses::total 623 # number of ReadCleanReq accesses(hits+misses) 996system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 196 # number of ReadSharedReq accesses(hits+misses) 997system.cpu.l2cache.ReadSharedReq_accesses::total 196 # number of ReadSharedReq accesses(hits+misses) 998system.cpu.l2cache.demand_accesses::cpu.inst 623 # number of demand (read+write) accesses 999system.cpu.l2cache.demand_accesses::cpu.data 342 # number of demand (read+write) accesses 1000system.cpu.l2cache.demand_accesses::total 965 # number of demand (read+write) accesses 1001system.cpu.l2cache.overall_accesses::cpu.inst 623 # number of overall (read+write) accesses 1002system.cpu.l2cache.overall_accesses::cpu.data 342 # number of overall (read+write) accesses 1003system.cpu.l2cache.overall_accesses::total 965 # number of overall (read+write) accesses 1004system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1005system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1006system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995185 # miss rate for ReadCleanReq accesses 1007system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995185 # miss rate for ReadCleanReq accesses 1008system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1009system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 1010system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995185 # miss rate for demand accesses 1011system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 1012system.cpu.l2cache.demand_miss_rate::total 0.996891 # miss rate for demand accesses 1013system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995185 # miss rate for overall accesses 1014system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 1015system.cpu.l2cache.overall_miss_rate::total 0.996891 # miss rate for overall accesses 1016system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86291.095890 # average ReadExReq miss latency 1017system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86291.095890 # average ReadExReq miss latency 1018system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79729.032258 # average ReadCleanReq miss latency 1019system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79729.032258 # average ReadCleanReq miss latency 1020system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86382.653061 # average ReadSharedReq miss latency 1021system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86382.653061 # average ReadSharedReq miss latency 1022system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency 1023system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency 1024system.cpu.l2cache.demand_avg_miss_latency::total 82080.561331 # average overall miss latency 1025system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency 1026system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331 # average overall miss latency 1028system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1033system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1034system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1035system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1036system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 1037system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 1038system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses 1039system.cpu.l2cache.ReadCleanReq_mshr_misses::total 620 # number of ReadCleanReq MSHR misses 1040system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 196 # number of ReadSharedReq MSHR misses 1041system.cpu.l2cache.ReadSharedReq_mshr_misses::total 196 # number of ReadSharedReq MSHR misses 1042system.cpu.l2cache.demand_mshr_misses::cpu.inst 620 # number of demand (read+write) MSHR misses 1043system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses 1044system.cpu.l2cache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses 1045system.cpu.l2cache.overall_mshr_misses::cpu.inst 620 # number of overall MSHR misses 1046system.cpu.l2cache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses 1047system.cpu.l2cache.overall_mshr_misses::total 962 # number of overall MSHR misses 1048system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11138500 # number of ReadExReq MSHR miss cycles 1049system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11138500 # number of ReadExReq MSHR miss cycles 1050system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43232000 # number of ReadCleanReq MSHR miss cycles 1051system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43232000 # number of ReadCleanReq MSHR miss cycles 1052system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14981000 # number of ReadSharedReq MSHR miss cycles 1053system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14981000 # number of ReadSharedReq MSHR miss cycles 1054system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43232000 # number of demand (read+write) MSHR miss cycles 1055system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26119500 # number of demand (read+write) MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::total 69351500 # number of demand (read+write) MSHR miss cycles 1057system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43232000 # number of overall MSHR miss cycles 1058system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26119500 # number of overall MSHR miss cycles 1059system.cpu.l2cache.overall_mshr_miss_latency::total 69351500 # number of overall MSHR miss cycles 1060system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995185 # mshr miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for demand accesses 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::total 0.996891 # mshr miss rate for demand accesses 1069system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for overall accesses 1070system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 1071system.cpu.l2cache.overall_mshr_miss_rate::total 0.996891 # mshr miss rate for overall accesses 1072system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76291.095890 # average ReadExReq mshr miss latency 1073system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76291.095890 # average ReadExReq mshr miss latency 1074system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69729.032258 # average ReadCleanReq mshr miss latency 1075system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69729.032258 # average ReadCleanReq mshr miss latency 1076system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469 # average ReadSharedReq mshr miss latency 1077system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469 # average ReadSharedReq mshr miss latency 1078system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1079system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1080system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency 1081system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1082system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1083system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency 1084system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1085system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter. 1086system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1087system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1088system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1091system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution 1092system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 1093system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 1094system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 1095system.cpu.toL2Bus.trans_dist::ReadCleanReq 623 # Transaction distribution 1096system.cpu.toL2Bus.trans_dist::ReadSharedReq 196 # Transaction distribution 1097system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253 # Packet count per connected master and slave (bytes) 1098system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) 1099system.cpu.toL2Bus.pkt_count::total 1936 # Packet count per connected master and slave (bytes) 1100system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40320 # Cumulative packet size per connected master and slave (bytes) 1101system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes) 1102system.cpu.toL2Bus.pkt_size::total 62144 # Cumulative packet size per connected master and slave (bytes) 1103system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1104system.cpu.toL2Bus.snoop_fanout::samples 965 # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::mean 0.002073 # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::stdev 0.045502 # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::0 963 99.79% 99.79% # Request fanout histogram 1109system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram 1110system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1111system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1112system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1113system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1114system.cpu.toL2Bus.snoop_fanout::total 965 # Request fanout histogram 1115system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) 1116system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 1117system.cpu.toL2Bus.respLayer0.occupancy 934500 # Layer occupancy (ticks) 1118system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%) 1119system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks) 1120system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 1121system.membus.trans_dist::ReadResp 815 # Transaction distribution 1122system.membus.trans_dist::ReadExReq 146 # Transaction distribution 1123system.membus.trans_dist::ReadExResp 146 # Transaction distribution 1124system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution 1125system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1923 # Packet count per connected master and slave (bytes) 1126system.membus.pkt_count::total 1923 # Packet count per connected master and slave (bytes) 1127system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61504 # Cumulative packet size per connected master and slave (bytes) 1128system.membus.pkt_size::total 61504 # Cumulative packet size per connected master and slave (bytes) 1129system.membus.snoops 0 # Total snoops (count) 1130system.membus.snoop_fanout::samples 962 # Request fanout histogram 1131system.membus.snoop_fanout::mean 0 # Request fanout histogram 1132system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1133system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1134system.membus.snoop_fanout::0 962 100.00% 100.00% # Request fanout histogram 1135system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1136system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1137system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1138system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1139system.membus.snoop_fanout::total 962 # Request fanout histogram 1140system.membus.reqLayer0.occupancy 1181000 # Layer occupancy (ticks) 1141system.membus.reqLayer0.utilization 4.6 # Layer utilization (%) 1142system.membus.respLayer1.occupancy 5115750 # Layer occupancy (ticks) 1143system.membus.respLayer1.utilization 20.0 # Layer utilization (%) 1144 1145---------- End Simulation Statistics ---------- 1146