stats.txt revision 11156:a37dda0f0202
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000025 # Number of seconds simulated 4sim_ticks 24832500 # Number of ticks simulated 5final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 79921 # Simulator instruction rate (inst/s) 8host_op_rate 79915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 155707227 # Simulator tick rate (ticks/s) 10host_mem_usage 297588 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host 12sim_insts 12744 # Number of instructions simulated 13sim_ops 12744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory 18system.physmem.bytes_read::total 62464 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 976 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 976 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 62464 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 84 # Per bank write bursts 45system.physmem.perBankRdBursts::1 152 # Per bank write bursts 46system.physmem.perBankRdBursts::2 78 # Per bank write bursts 47system.physmem.perBankRdBursts::3 59 # Per bank write bursts 48system.physmem.perBankRdBursts::4 88 # Per bank write bursts 49system.physmem.perBankRdBursts::5 48 # Per bank write bursts 50system.physmem.perBankRdBursts::6 33 # Per bank write bursts 51system.physmem.perBankRdBursts::7 50 # Per bank write bursts 52system.physmem.perBankRdBursts::8 42 # Per bank write bursts 53system.physmem.perBankRdBursts::9 39 # Per bank write bursts 54system.physmem.perBankRdBursts::10 29 # Per bank write bursts 55system.physmem.perBankRdBursts::11 34 # Per bank write bursts 56system.physmem.perBankRdBursts::12 15 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 68 # Per bank write bursts 59system.physmem.perBankRdBursts::15 37 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 24688000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 976 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation 203system.physmem.totQLat 12728500 # Total ticks spent queuing 204system.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 4880000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 19.65 # Data bus utilization in percentage 215system.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 749 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 25295.08 # Average gap between requests 224system.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ) 233system.physmem_0.averagePower 997.862715 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ) 247system.physmem_1.averagePower 912.772063 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 6978 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 988 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.fetch_hits 0 # ITB hits 264system.cpu.dtb.fetch_misses 0 # ITB misses 265system.cpu.dtb.fetch_acv 0 # ITB acv 266system.cpu.dtb.fetch_accesses 0 # ITB accesses 267system.cpu.dtb.read_hits 4756 # DTB read hits 268system.cpu.dtb.read_misses 94 # DTB read misses 269system.cpu.dtb.read_acv 0 # DTB read access violations 270system.cpu.dtb.read_accesses 4850 # DTB read accesses 271system.cpu.dtb.write_hits 2093 # DTB write hits 272system.cpu.dtb.write_misses 69 # DTB write misses 273system.cpu.dtb.write_acv 0 # DTB write access violations 274system.cpu.dtb.write_accesses 2162 # DTB write accesses 275system.cpu.dtb.data_hits 6849 # DTB hits 276system.cpu.dtb.data_misses 163 # DTB misses 277system.cpu.dtb.data_acv 0 # DTB access violations 278system.cpu.dtb.data_accesses 7012 # DTB accesses 279system.cpu.itb.fetch_hits 5404 # ITB hits 280system.cpu.itb.fetch_misses 57 # ITB misses 281system.cpu.itb.fetch_acv 0 # ITB acv 282system.cpu.itb.fetch_accesses 5461 # ITB accesses 283system.cpu.itb.read_hits 0 # DTB read hits 284system.cpu.itb.read_misses 0 # DTB read misses 285system.cpu.itb.read_acv 0 # DTB read access violations 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_acv 0 # DTB write access violations 290system.cpu.itb.write_accesses 0 # DTB write accesses 291system.cpu.itb.data_hits 0 # DTB hits 292system.cpu.itb.data_misses 0 # DTB misses 293system.cpu.itb.data_acv 0 # DTB access violations 294system.cpu.itb.data_accesses 0 # DTB accesses 295system.cpu.workload0.num_syscalls 17 # Number of system calls 296system.cpu.workload1.num_syscalls 17 # Number of system calls 297system.cpu.numCycles 49666 # number of cpu cycles simulated 298system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 299system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 300system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss 301system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed 302system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered 303system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken 304system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked 305system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing 306system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 307system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched 308system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed 309system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle 327system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle 328system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle 329system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked 330system.cpu.decode.RunCycles 5112 # Number of cycles decode is running 331system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking 332system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing 333system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch 334system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction 335system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode 336system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode 337system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing 338system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle 339system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking 340system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst 341system.cpu.rename.RunCycles 5150 # Number of cycles rename is running 342system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking 343system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename 344system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full 345system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full 346system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full 347system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full 348system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed 349system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made 350system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups 351system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 352system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed 353system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing 354system.cpu.rename.serializingInsts 60 # count of serializing insts renamed 355system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed 356system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer 357system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 358system.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit. 359system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 360system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 361system.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit. 362system.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit. 363system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads. 364system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 365system.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec) 366system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ 367system.cpu.iq.iqInstsIssued 22338 # Number of instructions issued 368system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued 369system.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling 370system.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph 371system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 372system.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle 389system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available 392system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available 419system.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 422system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 423system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 424system.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued 425system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued 426system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued 453system.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued 454system.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 457system.cpu.iq.FU_type_0::total 11090 # Type of FU issued 458system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued 459system.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued 460system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued 461system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued 462system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued 463system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued 464system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued 465system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued 466system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued 467system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued 468system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued 469system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued 470system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued 471system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued 472system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued 473system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued 474system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued 475system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued 476system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued 477system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued 478system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued 479system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued 480system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued 481system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued 482system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued 483system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued 484system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued 485system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued 486system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued 487system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued 488system.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued 489system.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued 490system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 491system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued 492system.cpu.iq.FU_type_1::total 11248 # Type of FU issued 493system.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued 494system.cpu.iq.rate 0.449764 # Inst issue rate 495system.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested 496system.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested 497system.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested 498system.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst) 499system.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst) 500system.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst) 501system.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads 502system.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes 503system.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses 504system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 505system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 506system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses 507system.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses 508system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses 509system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores 510system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 511system.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed 512system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 513system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 514system.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed 515system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 516system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 517system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 518system.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked 519system.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores 520system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address 521system.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed 522system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 523system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations 524system.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed 525system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 526system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 527system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled 528system.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked 529system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 530system.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing 531system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking 532system.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking 533system.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ 534system.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch 535system.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions 536system.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions 537system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions 538system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall 539system.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall 540system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations 541system.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly 542system.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly 543system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute 544system.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions 545system.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed 546system.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed 547system.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed 548system.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute 549system.cpu.iew.exec_swp::0 0 # number of swp insts executed 550system.cpu.iew.exec_swp::1 0 # number of swp insts executed 551system.cpu.iew.exec_swp::total 0 # number of swp insts executed 552system.cpu.iew.exec_nop::0 74 # number of nop insts executed 553system.cpu.iew.exec_nop::1 72 # number of nop insts executed 554system.cpu.iew.exec_nop::total 146 # number of nop insts executed 555system.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed 556system.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed 557system.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed 558system.cpu.iew.exec_branches::0 1644 # Number of branches executed 559system.cpu.iew.exec_branches::1 1639 # Number of branches executed 560system.cpu.iew.exec_branches::total 3283 # Number of branches executed 561system.cpu.iew.exec_stores::0 1067 # Number of stores executed 562system.cpu.iew.exec_stores::1 1111 # Number of stores executed 563system.cpu.iew.exec_stores::total 2178 # Number of stores executed 564system.cpu.iew.exec_rate 0.423871 # Inst execution rate 565system.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit 566system.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit 567system.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit 568system.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back 569system.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back 570system.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back 571system.cpu.iew.wb_producers::0 5189 # num instructions producing a value 572system.cpu.iew.wb_producers::1 5256 # num instructions producing a value 573system.cpu.iew.wb_producers::total 10445 # num instructions producing a value 574system.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value 575system.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value 576system.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value 577system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ 578system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ 579system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ 580system.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle 581system.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle 582system.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle 583system.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back 584system.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back 585system.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back 586system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ 587system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ 588system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ 589system.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit 590system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 591system.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted 592system.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle 609system.cpu.commit.committedInsts::0 6389 # Number of instructions committed 610system.cpu.commit.committedInsts::1 6389 # Number of instructions committed 611system.cpu.commit.committedInsts::total 12778 # Number of instructions committed 612system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed 613system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed 614system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed 615system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 616system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 617system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed 618system.cpu.commit.refs::0 2048 # Number of memory references committed 619system.cpu.commit.refs::1 2048 # Number of memory references committed 620system.cpu.commit.refs::total 4096 # Number of memory references committed 621system.cpu.commit.loads::0 1183 # Number of loads committed 622system.cpu.commit.loads::1 1183 # Number of loads committed 623system.cpu.commit.loads::total 2366 # Number of loads committed 624system.cpu.commit.membars::0 0 # Number of memory barriers committed 625system.cpu.commit.membars::1 0 # Number of memory barriers committed 626system.cpu.commit.membars::total 0 # Number of memory barriers committed 627system.cpu.commit.branches::0 1050 # Number of branches committed 628system.cpu.commit.branches::1 1050 # Number of branches committed 629system.cpu.commit.branches::total 2100 # Number of branches committed 630system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 631system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 632system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. 633system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. 634system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. 635system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. 636system.cpu.commit.function_calls::0 127 # Number of function calls committed. 637system.cpu.commit.function_calls::1 127 # Number of function calls committed. 638system.cpu.commit.function_calls::total 254 # Number of function calls committed. 639system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 640system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 641system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 642system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 643system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 644system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 645system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 669system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 670system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 671system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 672system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 673system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 674system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction 675system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction 676system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction 677system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction 678system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction 679system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction 680system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction 681system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction 682system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction 683system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 684system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction 685system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 686system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction 687system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction 688system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction 689system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction 690system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction 691system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 692system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction 693system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 694system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 695system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 696system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 697system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 698system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 699system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 700system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 701system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 702system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 703system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 704system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction 705system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 707system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_1::total 6389 # Class of committed instruction 709system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction 710system.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached 711system.cpu.rob.rob_reads 129836 # The number of ROB reads 712system.cpu.rob.rob_writes 57114 # The number of ROB writes 713system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself 714system.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling 715system.cpu.committedInsts::0 6372 # Number of Instructions Simulated 716system.cpu.committedInsts::1 6372 # Number of Instructions Simulated 717system.cpu.committedInsts::total 12744 # Number of Instructions Simulated 718system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated 719system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated 720system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated 721system.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction 722system.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction 723system.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads 724system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle 725system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle 726system.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads 727system.cpu.int_regfile_reads 26491 # number of integer regfile reads 728system.cpu.int_regfile_writes 14992 # number of integer regfile writes 729system.cpu.fp_regfile_reads 16 # number of floating regfile reads 730system.cpu.fp_regfile_writes 4 # number of floating regfile writes 731system.cpu.misc_regfile_reads 2 # number of misc regfile reads 732system.cpu.misc_regfile_writes 2 # number of misc regfile writes 733system.cpu.dcache.tags.replacements::0 0 # number of replacements 734system.cpu.dcache.tags.replacements::1 0 # number of replacements 735system.cpu.dcache.tags.replacements::total 0 # number of replacements 736system.cpu.dcache.tags.tagsinuse 212.222617 # Cycle average of tags in use 737system.cpu.dcache.tags.total_refs 4769 # Total number of references to valid blocks. 738system.cpu.dcache.tags.sampled_refs 344 # Sample count of references to valid blocks. 739system.cpu.dcache.tags.avg_refs 13.863372 # Average number of references to valid blocks. 740system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 741system.cpu.dcache.tags.occ_blocks::cpu.data 212.222617 # Average occupied blocks per requestor 742system.cpu.dcache.tags.occ_percent::cpu.data 0.051812 # Average percentage of cache occupancy 743system.cpu.dcache.tags.occ_percent::total 0.051812 # Average percentage of cache occupancy 744system.cpu.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id 745system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 746system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 747system.cpu.dcache.tags.occ_task_id_percent::1024 0.083984 # Percentage of cache occupancy per task id 748system.cpu.dcache.tags.tag_accesses 11936 # Number of tag accesses 749system.cpu.dcache.tags.data_accesses 11936 # Number of data accesses 750system.cpu.dcache.ReadReq_hits::cpu.data 3748 # number of ReadReq hits 751system.cpu.dcache.ReadReq_hits::total 3748 # number of ReadReq hits 752system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits 753system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits 754system.cpu.dcache.demand_hits::cpu.data 4769 # number of demand (read+write) hits 755system.cpu.dcache.demand_hits::total 4769 # number of demand (read+write) hits 756system.cpu.dcache.overall_hits::cpu.data 4769 # number of overall hits 757system.cpu.dcache.overall_hits::total 4769 # number of overall hits 758system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses 759system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses 760system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses 761system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses 762system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses 763system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses 764system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses 765system.cpu.dcache.overall_misses::total 1027 # number of overall misses 766system.cpu.dcache.ReadReq_miss_latency::cpu.data 24395500 # number of ReadReq miss cycles 767system.cpu.dcache.ReadReq_miss_latency::total 24395500 # number of ReadReq miss cycles 768system.cpu.dcache.WriteReq_miss_latency::cpu.data 50809414 # number of WriteReq miss cycles 769system.cpu.dcache.WriteReq_miss_latency::total 50809414 # number of WriteReq miss cycles 770system.cpu.dcache.demand_miss_latency::cpu.data 75204914 # number of demand (read+write) miss cycles 771system.cpu.dcache.demand_miss_latency::total 75204914 # number of demand (read+write) miss cycles 772system.cpu.dcache.overall_miss_latency::cpu.data 75204914 # number of overall miss cycles 773system.cpu.dcache.overall_miss_latency::total 75204914 # number of overall miss cycles 774system.cpu.dcache.ReadReq_accesses::cpu.data 4066 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.ReadReq_accesses::total 4066 # number of ReadReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 778system.cpu.dcache.demand_accesses::cpu.data 5796 # number of demand (read+write) accesses 779system.cpu.dcache.demand_accesses::total 5796 # number of demand (read+write) accesses 780system.cpu.dcache.overall_accesses::cpu.data 5796 # number of overall (read+write) accesses 781system.cpu.dcache.overall_accesses::total 5796 # number of overall (read+write) accesses 782system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078210 # miss rate for ReadReq accesses 783system.cpu.dcache.ReadReq_miss_rate::total 0.078210 # miss rate for ReadReq accesses 784system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses 785system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses 786system.cpu.dcache.demand_miss_rate::cpu.data 0.177191 # miss rate for demand accesses 787system.cpu.dcache.demand_miss_rate::total 0.177191 # miss rate for demand accesses 788system.cpu.dcache.overall_miss_rate::cpu.data 0.177191 # miss rate for overall accesses 789system.cpu.dcache.overall_miss_rate::total 0.177191 # miss rate for overall accesses 790system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805 # average ReadReq miss latency 791system.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805 # average ReadReq miss latency 792system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422 # average WriteReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422 # average WriteReq miss latency 794system.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency 795system.cpu.dcache.demand_avg_miss_latency::total 73227.764362 # average overall miss latency 796system.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency 797system.cpu.dcache.overall_avg_miss_latency::total 73227.764362 # average overall miss latency 798system.cpu.dcache.blocked_cycles::no_mshrs 5829 # number of cycles access was blocked 799system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 800system.cpu.dcache.blocked::no_mshrs 135 # number of cycles access was blocked 801system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 802system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.177778 # average number of cycles each access was blocked 803system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 804system.cpu.dcache.fast_writes 0 # number of fast writes performed 805system.cpu.dcache.cache_copies 0 # number of cache copies performed 806system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits 807system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits 808system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits 809system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits 810system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits 811system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits 812system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits 813system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits 814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 198 # number of ReadReq MSHR misses 815system.cpu.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses 818system.cpu.dcache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses 819system.cpu.dcache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses 820system.cpu.dcache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses 821system.cpu.dcache.overall_mshr_misses::total 344 # number of overall MSHR misses 822system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17299000 # number of ReadReq MSHR miss cycles 823system.cpu.dcache.ReadReq_mshr_miss_latency::total 17299000 # number of ReadReq MSHR miss cycles 824system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12670989 # number of WriteReq MSHR miss cycles 825system.cpu.dcache.WriteReq_mshr_miss_latency::total 12670989 # number of WriteReq MSHR miss cycles 826system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29969989 # number of demand (read+write) MSHR miss cycles 827system.cpu.dcache.demand_mshr_miss_latency::total 29969989 # number of demand (read+write) MSHR miss cycles 828system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29969989 # number of overall MSHR miss cycles 829system.cpu.dcache.overall_mshr_miss_latency::total 29969989 # number of overall MSHR miss cycles 830system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048697 # mshr miss rate for ReadReq accesses 831system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048697 # mshr miss rate for ReadReq accesses 832system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 833system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 834system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for demand accesses 835system.cpu.dcache.demand_mshr_miss_rate::total 0.059351 # mshr miss rate for demand accesses 836system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for overall accesses 837system.cpu.dcache.overall_mshr_miss_rate::total 0.059351 # mshr miss rate for overall accesses 838system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869 # average ReadReq mshr miss latency 839system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869 # average ReadReq mshr miss latency 840system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890 # average WriteReq mshr miss latency 841system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890 # average WriteReq mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency 843system.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency 845system.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency 846system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 847system.cpu.icache.tags.replacements::0 8 # number of replacements 848system.cpu.icache.tags.replacements::1 0 # number of replacements 849system.cpu.icache.tags.replacements::total 8 # number of replacements 850system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use 851system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks. 852system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks. 853system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks. 854system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 855system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor 856system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy 857system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy 858system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id 861system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id 862system.cpu.icache.tags.tag_accesses 11430 # Number of tag accesses 863system.cpu.icache.tags.data_accesses 11430 # Number of data accesses 864system.cpu.icache.ReadReq_hits::cpu.inst 4463 # number of ReadReq hits 865system.cpu.icache.ReadReq_hits::total 4463 # number of ReadReq hits 866system.cpu.icache.demand_hits::cpu.inst 4463 # number of demand (read+write) hits 867system.cpu.icache.demand_hits::total 4463 # number of demand (read+write) hits 868system.cpu.icache.overall_hits::cpu.inst 4463 # number of overall hits 869system.cpu.icache.overall_hits::total 4463 # number of overall hits 870system.cpu.icache.ReadReq_misses::cpu.inst 935 # number of ReadReq misses 871system.cpu.icache.ReadReq_misses::total 935 # number of ReadReq misses 872system.cpu.icache.demand_misses::cpu.inst 935 # number of demand (read+write) misses 873system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses 874system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses 875system.cpu.icache.overall_misses::total 935 # number of overall misses 876system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles 877system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles 878system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles 879system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles 880system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles 881system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles 882system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses) 883system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses) 884system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses 885system.cpu.icache.demand_accesses::total 5398 # number of demand (read+write) accesses 886system.cpu.icache.overall_accesses::cpu.inst 5398 # number of overall (read+write) accesses 887system.cpu.icache.overall_accesses::total 5398 # number of overall (read+write) accesses 888system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.173212 # miss rate for ReadReq accesses 889system.cpu.icache.ReadReq_miss_rate::total 0.173212 # miss rate for ReadReq accesses 890system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 # miss rate for demand accesses 891system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses 892system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses 893system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses 894system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency 895system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency 896system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency 897system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency 898system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency 899system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency 900system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked 901system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked 903system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 # average number of cycles each access was blocked 905system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.icache.fast_writes 0 # number of fast writes performed 907system.cpu.icache.cache_copies 0 # number of cache copies performed 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits 914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 634 # number of ReadReq MSHR misses 915system.cpu.icache.ReadReq_mshr_misses::total 634 # number of ReadReq MSHR misses 916system.cpu.icache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses 917system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses 918system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses 919system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses 920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles 921system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses 927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses 928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses 929system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.l2cache.tags.replacements::0 0 # number of replacements 940system.cpu.l2cache.tags.replacements::1 0 # number of replacements 941system.cpu.l2cache.tags.replacements::total 0 # number of replacements 942system.cpu.l2cache.tags.tagsinuse 436.545027 # Cycle average of tags in use 943system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 944system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks. 945system.cpu.l2cache.tags.avg_refs 0.012048 # Average number of references to valid blocks. 946system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 947system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.712929 # Average occupied blocks per requestor 948system.cpu.l2cache.tags.occ_blocks::cpu.data 118.832098 # Average occupied blocks per requestor 949system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009696 # Average percentage of cache occupancy 950system.cpu.l2cache.tags.occ_percent::cpu.data 0.003626 # Average percentage of cache occupancy 951system.cpu.l2cache.tags.occ_percent::total 0.013322 # Average percentage of cache occupancy 952system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1024::0 326 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id 955system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id 956system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses 957system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses 958system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 959system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 960system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 961system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 962system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 963system.cpu.l2cache.overall_hits::total 2 # number of overall hits 964system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses 965system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses 966system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 632 # number of ReadCleanReq misses 967system.cpu.l2cache.ReadCleanReq_misses::total 632 # number of ReadCleanReq misses 968system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses 969system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses 970system.cpu.l2cache.demand_misses::cpu.inst 632 # number of demand (read+write) misses 971system.cpu.l2cache.demand_misses::cpu.data 344 # number of demand (read+write) misses 972system.cpu.l2cache.demand_misses::total 976 # number of demand (read+write) misses 973system.cpu.l2cache.overall_misses::cpu.inst 632 # number of overall misses 974system.cpu.l2cache.overall_misses::cpu.data 344 # number of overall misses 975system.cpu.l2cache.overall_misses::total 976 # number of overall misses 976system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12444500 # number of ReadExReq miss cycles 977system.cpu.l2cache.ReadExReq_miss_latency::total 12444500 # number of ReadExReq miss cycles 978system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50583000 # number of ReadCleanReq miss cycles 979system.cpu.l2cache.ReadCleanReq_miss_latency::total 50583000 # number of ReadCleanReq miss cycles 980system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16994000 # number of ReadSharedReq miss cycles 981system.cpu.l2cache.ReadSharedReq_miss_latency::total 16994000 # number of ReadSharedReq miss cycles 982system.cpu.l2cache.demand_miss_latency::cpu.inst 50583000 # number of demand (read+write) miss cycles 983system.cpu.l2cache.demand_miss_latency::cpu.data 29438500 # number of demand (read+write) miss cycles 984system.cpu.l2cache.demand_miss_latency::total 80021500 # number of demand (read+write) miss cycles 985system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles 986system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles 987system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles 988system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) 989system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) 990system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses) 991system.cpu.l2cache.ReadCleanReq_accesses::total 634 # number of ReadCleanReq accesses(hits+misses) 992system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses) 993system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses) 994system.cpu.l2cache.demand_accesses::cpu.inst 634 # number of demand (read+write) accesses 995system.cpu.l2cache.demand_accesses::cpu.data 344 # number of demand (read+write) accesses 996system.cpu.l2cache.demand_accesses::total 978 # number of demand (read+write) accesses 997system.cpu.l2cache.overall_accesses::cpu.inst 634 # number of overall (read+write) accesses 998system.cpu.l2cache.overall_accesses::cpu.data 344 # number of overall (read+write) accesses 999system.cpu.l2cache.overall_accesses::total 978 # number of overall (read+write) accesses 1000system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1001system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 1002system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996845 # miss rate for ReadCleanReq accesses 1003system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996845 # miss rate for ReadCleanReq accesses 1004system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1005system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 1006system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996845 # miss rate for demand accesses 1007system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 1008system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 1009system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996845 # miss rate for overall accesses 1010system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 1011system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 1012system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370 # average ReadExReq miss latency 1013system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370 # average ReadExReq miss latency 1014system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405 # average ReadCleanReq miss latency 1015system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405 # average ReadCleanReq miss latency 1016system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828 # average ReadSharedReq miss latency 1017system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828 # average ReadSharedReq miss latency 1018system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency 1019system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency 1020system.cpu.l2cache.demand_avg_miss_latency::total 81989.241803 # average overall miss latency 1021system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency 1022system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency 1023system.cpu.l2cache.overall_avg_miss_latency::total 81989.241803 # average overall miss latency 1024system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1025system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1026system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1027system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1028system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1029system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1030system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1031system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1032system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 1033system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 1034system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 632 # number of ReadCleanReq MSHR misses 1035system.cpu.l2cache.ReadCleanReq_mshr_misses::total 632 # number of ReadCleanReq MSHR misses 1036system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses 1037system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses 1038system.cpu.l2cache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses 1039system.cpu.l2cache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses 1040system.cpu.l2cache.demand_mshr_misses::total 976 # number of demand (read+write) MSHR misses 1041system.cpu.l2cache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses 1042system.cpu.l2cache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses 1043system.cpu.l2cache.overall_mshr_misses::total 976 # number of overall MSHR misses 1044system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10984500 # number of ReadExReq MSHR miss cycles 1045system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10984500 # number of ReadExReq MSHR miss cycles 1046system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles 1047system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles 1048system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles 1049system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles 1050system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles 1051system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles 1052system.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles 1053system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles 1054system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles 1055system.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles 1056system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1057system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 1058system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses 1059system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses 1060system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1061system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 1062system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses 1063system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 1064system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 1065system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses 1066system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 1067system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 1068system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency 1069system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency 1070system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency 1071system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency 1072system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency 1073system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency 1074system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency 1075system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency 1076system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency 1077system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency 1078system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency 1079system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency 1080system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1081system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter. 1082system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1083system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1084system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1085system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1086system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1087system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution 1088system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution 1089system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution 1091system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution 1092system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution 1093system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 1094system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 1095system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) 1096system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) 1098system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes) 1099system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1100system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1109system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1110system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram 1111system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) 1112system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 1113system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks) 1114system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%) 1115system.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks) 1116system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) 1117system.membus.trans_dist::ReadResp 830 # Transaction distribution 1118system.membus.trans_dist::ReadExReq 146 # Transaction distribution 1119system.membus.trans_dist::ReadExResp 146 # Transaction distribution 1120system.membus.trans_dist::ReadSharedReq 830 # Transaction distribution 1121system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes) 1122system.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) 1123system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes) 1124system.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) 1125system.membus.snoops 0 # Total snoops (count) 1126system.membus.snoop_fanout::samples 976 # Request fanout histogram 1127system.membus.snoop_fanout::mean 0 # Request fanout histogram 1128system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1129system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1130system.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram 1131system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1132system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1133system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1134system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1135system.membus.snoop_fanout::total 976 # Request fanout histogram 1136system.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks) 1137system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) 1138system.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks) 1139system.membus.respLayer1.utilization 20.9 # Layer utilization (%) 1140 1141---------- End Simulation Statistics ---------- 1142