stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28768000 # Number of ticks simulated 5final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 320748 # Simulator instruction rate (inst/s) 8host_tick_rate 940055576 # Simulator tick rate (ticks/s) 9host_mem_usage 211332 # Number of bytes of host memory used 10host_seconds 0.03 # Real time elapsed on the host 11sim_insts 9810 # Number of instructions simulated 12system.physmem.bytes_read 23104 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 361 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.workload.num_syscalls 11 # Number of system calls 22system.cpu.numCycles 57536 # number of cpu cycles simulated 23system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 24system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 25system.cpu.num_insts 9810 # Number of instructions executed 26system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses 27system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 28system.cpu.num_func_calls 0 # number of times a function call or return occured 29system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls 30system.cpu.num_int_insts 9715 # number of integer instructions 31system.cpu.num_fp_insts 0 # number of float instructions 32system.cpu.num_int_register_reads 21313 # number of times the integer registers were read 33system.cpu.num_int_register_writes 9368 # number of times the integer registers were written 34system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 35system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 36system.cpu.num_mem_refs 1990 # number of memory refs 37system.cpu.num_load_insts 1056 # Number of load instructions 38system.cpu.num_store_insts 934 # Number of store instructions 39system.cpu.num_idle_cycles 0 # Number of idle cycles 40system.cpu.num_busy_cycles 57536 # Number of busy cycles 41system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 42system.cpu.idle_fraction 0 # Percentage of idle cycles 43system.cpu.icache.replacements 0 # number of replacements 44system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use 45system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. 46system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. 47system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. 48system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 49system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context 50system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy 51system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits 52system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits 53system.cpu.icache.overall_hits 6683 # number of overall hits 54system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses 55system.cpu.icache.demand_misses 228 # number of demand (read+write) misses 56system.cpu.icache.overall_misses 228 # number of overall misses 57system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles 58system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles 59system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles 60system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses) 61system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses 62system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses 63system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses 64system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses 65system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses 66system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency 67system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency 68system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency 69system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 72system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 73system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 74system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 75system.cpu.icache.fast_writes 0 # number of fast writes performed 76system.cpu.icache.cache_copies 0 # number of cache copies performed 77system.cpu.icache.writebacks 0 # number of writebacks 78system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 79system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 80system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses 81system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses 82system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses 83system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 84system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles 85system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles 86system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles 87system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 88system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses 89system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses 90system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses 91system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency 92system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency 93system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency 94system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 95system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 96system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 97system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 98system.cpu.dcache.replacements 0 # number of replacements 99system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use 100system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. 101system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. 102system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. 103system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 104system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context 105system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy 106system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits 107system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits 108system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits 109system.cpu.dcache.overall_hits 1856 # number of overall hits 110system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses 111system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses 112system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses 113system.cpu.dcache.overall_misses 134 # number of overall misses 114system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles 115system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles 116system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles 117system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles 118system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) 119system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) 120system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses 121system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses 122system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses 123system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses 124system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses 125system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses 126system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 127system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 128system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 129system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 130system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 131system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 133system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 134system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 135system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 136system.cpu.dcache.fast_writes 0 # number of fast writes performed 137system.cpu.dcache.cache_copies 0 # number of cache copies performed 138system.cpu.dcache.writebacks 0 # number of writebacks 139system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 140system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 141system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses 142system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses 143system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses 144system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses 145system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 146system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles 147system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles 148system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles 149system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles 150system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 151system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses 152system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses 153system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses 154system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses 155system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 156system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 157system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 158system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 159system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 160system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 161system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 162system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.l2cache.replacements 0 # number of replacements 164system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use 165system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 166system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. 167system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. 168system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 169system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context 170system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy 171system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 172system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 173system.cpu.l2cache.overall_hits 1 # number of overall hits 174system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses 175system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses 176system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses 177system.cpu.l2cache.overall_misses 361 # number of overall misses 178system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles 179system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles 180system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles 181system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles 182system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses) 183system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) 184system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses 185system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses 186system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses 187system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 188system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses 189system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses 190system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 191system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 192system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 193system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 194system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 195system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 196system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 197system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 198system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 199system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 200system.cpu.l2cache.fast_writes 0 # number of fast writes performed 201system.cpu.l2cache.cache_copies 0 # number of cache copies performed 202system.cpu.l2cache.writebacks 0 # number of writebacks 203system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 204system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 205system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses 206system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses 207system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses 208system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses 209system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 210system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles 211system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles 212system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles 213system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles 214system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 215system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses 216system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 217system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses 218system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses 219system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 220system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 221system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 222system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 223system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 224system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 225system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 226system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 227 228---------- End Simulation Statistics ---------- 229