stats.txt revision 11680
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000092 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 91859 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000 # Frequency of simulated ticks 711680SCurtis.Dunham@arm.comhost_inst_rate 42401 # Simulator instruction rate (inst/s) 811680SCurtis.Dunham@arm.comhost_op_rate 76797 # Simulator op (including micro ops) rate (op/s) 911680SCurtis.Dunham@arm.comhost_tick_rate 723555 # Simulator tick rate (ticks/s) 1011680SCurtis.Dunham@arm.comhost_mem_usage 431840 # Number of bytes of host memory used 1111680SCurtis.Dunham@arm.comhost_seconds 0.13 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory 1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory 1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory 2010526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory 2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory 2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory 2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory 2410526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory 2511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) 2711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) 2811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) 2911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) 3011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) 3110526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs 1377 # Number of read requests accepted 3210526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs 1373 # Number of write requests accepted 3310526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue 3410526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue 3511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM 3611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue 3711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM 3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side 3910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side 4011680SCurtis.Dunham@arm.comsystem.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue 4111680SCurtis.Dunham@arm.comsystem.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one 4210526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts 4411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts 4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts 4611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts 4711680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts 4811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts 4911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts 5011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts 5111680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts 5211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts 5311680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts 5411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts 5510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts 5611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts 5710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts 5811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts 5911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts 6011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts 6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts 6211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts 6311023Sjthestness@gmail.comsystem.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts 6411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts 6511680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts 6611680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts 6711680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts 6911680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts 7011680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts 7110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts 7211680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts 7310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts 7411680SCurtis.Dunham@arm.comsystem.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts 7510526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7610526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7711680SCurtis.Dunham@arm.comsystem.mem_ctrls.totGap 91773 # Total gap between requests 7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8410526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) 8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 9110526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) 9211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdQLenPdf::0 647 # What read queue length does an incoming req see 9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 12310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 13911023Sjthestness@gmail.comsystem.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see 14011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see 14111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see 14211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::18 42 # What write queue length does an incoming req see 14311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see 14411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see 14511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see 14611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see 14711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see 14911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see 15011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see 15111680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see 15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation 18911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation 19011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation 19211680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation 19311680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation 19611680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes 20311680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes 20411680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes 20511680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes 20611680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes 20711680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes 20811680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes 20911680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes 21011680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes 21111680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes 21211680SCurtis.Dunham@arm.comsystem.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes 21311680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads 21411680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads 21511680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads 21611680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads 21711680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads 21811680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads 21911680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads 22011680SCurtis.Dunham@arm.comsystem.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads 22111680SCurtis.Dunham@arm.comsystem.mem_ctrls.totQLat 12721 # Total ticks spent queuing 22211680SCurtis.Dunham@arm.comsystem.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM 22311680SCurtis.Dunham@arm.comsystem.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers 22411680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst 22510526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 22611680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst 22711680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s 22811680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s 22911680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s 23011680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s 23110526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23211680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage 23311680SCurtis.Dunham@arm.comsystem.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads 23411023Sjthestness@gmail.comsystem.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes 23510526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 23611680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing 23711680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads 23811680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes 23911680SCurtis.Dunham@arm.comsystem.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads 24011680SCurtis.Dunham@arm.comsystem.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes 24111680SCurtis.Dunham@arm.comsystem.mem_ctrls.avgGap 33.37 # Average gap between requests 24211680SCurtis.Dunham@arm.comsystem.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined 24311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) 24411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) 24511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) 24811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) 25011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) 25111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) 25211680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) 25311680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) 25511680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank 25611680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states 25711680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states 25811680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states 25911680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states 26011680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states 26111680SCurtis.Dunham@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states 26211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) 26311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) 26411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) 26511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) 26611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) 26711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) 26811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) 26911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) 27011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) 27111680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 27211680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) 27311680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) 27411680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank 27511680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states 27611680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states 27711680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 27811680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states 27911680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states 28011680SCurtis.Dunham@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states 28111680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 28210526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock 1 # Clock period in ticks 28311680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 28410036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 16 # Clock period in ticks 28511680SCurtis.Dunham@arm.comsystem.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 28611680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 2878673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 28811680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states 28911680SCurtis.Dunham@arm.comsystem.cpu.numCycles 91859 # number of cpu cycles simulated 2908673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2917935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2929150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 2939583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 2949924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 2958673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2969702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 2979150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 2989924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 2997935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 3009924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 3019924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 3027935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 3037935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 3049924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 3059924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 3069583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 3079583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 3089373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 30911023Sjthestness@gmail.comsystem.cpu.num_idle_cycles 0.999989 # Number of idle cycles 31011680SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 91858.000011 # Number of busy cycles 31111023Sjthestness@gmail.comsystem.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles 31211023Sjthestness@gmail.comsystem.cpu.idle_fraction 0.000011 # Percentage of idle cycles 31310063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 31410220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 31510220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 31610220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 31710220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 31810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 31910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 32010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 32110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 32210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 32310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 32410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 32510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 32610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 32710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 32810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 32910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 33010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 33110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 33210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 33310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 33410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 33510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 33610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 33710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 33810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 33910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 34010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 34110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 34210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 34310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 34410220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 34510220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 34610220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 34710220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 34810220Sandreas.hansson@arm.comsystem.cpu.op_class::total 9748 # Class of executed instruction 34910628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 35011680SCurtis.Dunham@arm.comsystem.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 35110628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 35210628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 35310628Sandreas.hansson@arm.comsystem.ruby.delayHist::samples 2750 # delay histogram for all message 35410628Sandreas.hansson@arm.comsystem.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 35510628Sandreas.hansson@arm.comsystem.ruby.delayHist::total 2750 # delay histogram for all message 35611312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::bucket_size 1 35711312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::max_bucket 9 35811312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::samples 8852 35911312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::mean 1 36011312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::gmean 1 36111312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36211312Santhony.gutierrez@amd.comsystem.ruby.outstanding_req_hist_seqr::total 8852 36311312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::bucket_size 64 36411312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::max_bucket 639 36511312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::samples 8852 36611680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::mean 9.377203 36711680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::gmean 1.827971 36811680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr::stdev 23.652747 36911680SCurtis.Dunham@arm.comsystem.ruby.latency_hist_seqr | 8226 92.93% 92.93% | 589 6.65% 99.58% | 26 0.29% 99.88% | 4 0.05% 99.92% | 3 0.03% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 37011312Santhony.gutierrez@amd.comsystem.ruby.latency_hist_seqr::total 8852 37111312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::bucket_size 1 37211312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::max_bucket 9 37311312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::samples 7475 37411312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::mean 1 37511312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::gmean 1 37611312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 37711312Santhony.gutierrez@amd.comsystem.ruby.hit_latency_hist_seqr::total 7475 37811312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::bucket_size 64 37911312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::max_bucket 639 38011312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::samples 1377 38111680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::mean 54.852578 38211680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::gmean 48.312712 38311680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr::stdev 33.880423 38411680SCurtis.Dunham@arm.comsystem.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 38511312Santhony.gutierrez@amd.comsystem.ruby.miss_latency_hist_seqr::total 1377 38611312Santhony.gutierrez@amd.comsystem.ruby.Directory.incomplete_times_seqr 1376 38711680SCurtis.Dunham@arm.comsystem.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 38810628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 38910628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 39010628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 39111680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 39211680SCurtis.Dunham@arm.comsystem.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 39310628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 39411680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 39511680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.percent_links_utilized 7.484297 39610628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::2 1377 39710628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Data::2 1373 39810628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::4 1377 39910628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3 1373 40010628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::2 11016 40110628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Data::2 98856 40210628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4 99144 40310628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 40411680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 40511680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.percent_links_utilized 7.484297 40610628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::2 1377 40710628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Data::2 1373 40810628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::4 1377 40910628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3 1373 41010628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::2 11016 41110628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Data::2 98856 41210628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4 99144 41310628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 41411680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 41511680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.percent_links_utilized 7.484297 41610628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::2 1377 41710628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Data::2 1373 41810628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::4 1377 41910628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3 1373 42010628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::2 11016 42110628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Data::2 98856 42210628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4 99144 42310628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 42411680SCurtis.Dunham@arm.comsystem.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 42510628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control 4131 42610628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Data 4119 42710628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data 4131 42810628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control 4119 42910628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control 33048 43010628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Data 296568 43110628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data 297432 43210628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control 32952 43311680SCurtis.Dunham@arm.comsystem.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states 43411680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle0.link_utilization 7.493006 4359864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 4369864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 4379864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 4389864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 43911680SCurtis.Dunham@arm.comsystem.ruby.network.routers0.throttle1.link_utilization 7.475588 4409864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1377 4419864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1373 4429864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 4439864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 44411680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle0.link_utilization 7.475588 4459864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1377 4469864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1373 4479864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 4489864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 44911680SCurtis.Dunham@arm.comsystem.ruby.network.routers1.throttle1.link_utilization 7.493006 4509864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 4519864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 4529864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 4539864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 45411680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle0.link_utilization 7.493006 4559864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 4569864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 4579864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 4589864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 45911680SCurtis.Dunham@arm.comsystem.ruby.network.routers2.throttle1.link_utilization 7.475588 4609864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1377 4619864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1373 4629864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 4639864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 46410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 46510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 46610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 46710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 46810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 46910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 47010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 47110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 47210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 47310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 47411312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::bucket_size 32 47511312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::max_bucket 319 47611312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::samples 1045 47711680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::mean 23.607656 47811680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::gmean 6.057935 47911680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr::stdev 29.475705 48011680SCurtis.Dunham@arm.comsystem.ruby.LD.latency_hist_seqr | 546 52.25% 52.25% | 330 31.58% 83.83% | 162 15.50% 99.33% | 1 0.10% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 48111312Santhony.gutierrez@amd.comsystem.ruby.LD.latency_hist_seqr::total 1045 48211312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size 1 48311312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket 9 48411312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples 546 48511312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::mean 1 48611312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::gmean 1 48711312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 48811312Santhony.gutierrez@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total 546 48911312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size 32 49011312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket 319 49111312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples 499 49211680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::mean 48.344689 49311680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::gmean 43.484561 49411680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr::stdev 25.453032 49511680SCurtis.Dunham@arm.comsystem.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 330 66.13% 66.13% | 162 32.46% 98.60% | 1 0.20% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 49611312Santhony.gutierrez@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total 499 49711312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::bucket_size 64 49811312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::max_bucket 639 49911312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::samples 935 50011680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::mean 16.455615 50111680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::gmean 2.877223 50211680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr::stdev 34.720603 50311680SCurtis.Dunham@arm.comsystem.ruby.ST.latency_hist_seqr | 821 87.81% 87.81% | 102 10.91% 98.72% | 6 0.64% 99.36% | 2 0.21% 99.57% | 2 0.21% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50411312Santhony.gutierrez@amd.comsystem.ruby.ST.latency_hist_seqr::total 935 50511312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size 1 50611312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket 9 50711312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples 681 50811312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::mean 1 50911312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::gmean 1 51011312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 51111312Santhony.gutierrez@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total 681 51211312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size 64 51311312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket 639 51411312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples 254 51511680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::mean 57.893701 51611680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::gmean 48.924758 51711680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr::stdev 45.645746 51811680SCurtis.Dunham@arm.comsystem.ruby.ST.miss_latency_hist_seqr | 140 55.12% 55.12% | 102 40.16% 95.28% | 6 2.36% 97.64% | 2 0.79% 98.43% | 2 0.79% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 51911312Santhony.gutierrez@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total 254 52011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size 64 52111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket 639 52211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples 6864 52311680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::mean 6.251748 52411680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::gmean 1.432185 52511680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr::stdev 19.434647 52611680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.latency_hist_seqr | 6521 95.00% 95.00% | 324 4.72% 99.72% | 15 0.22% 99.94% | 1 0.01% 99.96% | 1 0.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 52711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total 6864 52811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 52911312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 53011312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples 6241 53111312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean 1 53211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 53311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 53411312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total 6241 53511312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 53611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 53711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples 623 53811680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean 58.861958 53911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.329270 54011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.443818 54111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr | 280 44.94% 44.94% | 324 52.01% 96.95% | 15 2.41% 99.36% | 1 0.16% 99.52% | 1 0.16% 99.68% | 2 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 54211312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total 623 54311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::bucket_size 4 54411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::max_bucket 39 54511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::samples 8 54611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::mean 4.875000 54711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::gmean 1.542211 54811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::stdev 10.960155 54911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 55011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::total 8 55111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1 55211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9 55311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::samples 7 55411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::mean 1 55511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1 55611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 55711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::total 7 55811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 4 55911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 39 56011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::samples 1 56111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::mean 32 56211312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::gmean 32 56311312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::stdev nan 56411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 56511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::total 1 56611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 56711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 56811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::samples 1377 56911680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.852578 57011680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::gmean 48.312712 57111680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.880423 57211680SCurtis.Dunham@arm.comsystem.ruby.Directory.miss_mach_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 57311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_mach_latency_hist_seqr::total 1377 57411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 57511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 57611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 57711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 57811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 57911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 58011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 58111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 58211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 58311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan 58411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 58511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 58611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 58711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 58811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 58911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan 59011312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 59111312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 59211312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 59311312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 59411312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 59511312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 59611312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 59711312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 59811312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 59911312Santhony.gutierrez@amd.comsystem.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 60011312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 60111312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 60211312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 499 60311680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 48.344689 60411680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.484561 60511680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.453032 60611680SCurtis.Dunham@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 330 66.13% 66.13% | 162 32.46% 98.60% | 1 0.20% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 60711312Santhony.gutierrez@amd.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 499 60811312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 60911312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 61011312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 254 61111680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 57.893701 61211680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.924758 61311680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 45.645746 61411680SCurtis.Dunham@arm.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 140 55.12% 55.12% | 102 40.16% 95.28% | 6 2.36% 97.64% | 2 0.79% 98.43% | 2 0.79% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 61511312Santhony.gutierrez@amd.comsystem.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 254 61611312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 61711312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 61811312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 623 61911680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 58.861958 62011680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.329270 62111680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 33.443818 62211680SCurtis.Dunham@arm.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 280 44.94% 44.94% | 324 52.01% 96.95% | 15 2.41% 99.36% | 1 0.16% 99.52% | 1 0.16% 99.68% | 2 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 62311312Santhony.gutierrez@amd.comsystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 623 62411312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::bucket_size 4 62511312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::max_bucket 39 62611312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::samples 1 62711312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::mean 32 62811312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::gmean 32 62911312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::stdev nan 63011312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 63111312Santhony.gutierrez@amd.comsystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::total 1 63210628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 63310628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 63410628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 63510628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 63610628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 63710628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 63810628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 63910628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 64010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 64110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 64210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 64310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 64410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 64510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 64610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 64710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 64810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 64910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 65010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 65110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 65210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 65310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 65410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 65510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 6566167SN/A 6576167SN/A---------- End Simulation Statistics ---------- 658