stats.txt revision 10526
16167SN/A
26167SN/A---------- Begin Simulation Statistics ----------
310526Snilay@cs.wisc.edusim_seconds                                  0.000107                       # Number of seconds simulated
410526Snilay@cs.wisc.edusim_ticks                                      107237                       # Number of ticks simulated
510526Snilay@cs.wisc.edufinal_tick                                     107237                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68673SN/Asim_freq                                   1000000000                       # Frequency of simulated ticks
710526Snilay@cs.wisc.eduhost_inst_rate                                  14917                       # Simulator instruction rate (inst/s)
810526Snilay@cs.wisc.eduhost_op_rate                                    27022                       # Simulator op (including micro ops) rate (op/s)
910526Snilay@cs.wisc.eduhost_tick_rate                                 297251                       # Simulator tick rate (ticks/s)
1010526Snilay@cs.wisc.eduhost_mem_usage                                 452416                       # Number of bytes of host memory used
1110526Snilay@cs.wisc.eduhost_seconds                                     0.36                       # Real time elapsed on the host
129150SAli.Saidi@ARM.comsim_insts                                        5381                       # Number of instructions simulated
139583Snilay@cs.wisc.edusim_ops                                          9748                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                             1                       # Clock period in ticks
1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0        88128                       # Number of bytes read from this memory
1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total              88128                       # Number of bytes read from this memory
1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0        87872                       # Number of bytes written to this memory
1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total           87872                       # Number of bytes written to this memory
2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0         1377                       # Number of read requests responded to by this memory
2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total                1377                       # Number of read requests responded to by this memory
2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0         1373                       # Number of write requests responded to by this memory
2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total               1373                       # Number of write requests responded to by this memory
2410526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::ruby.dir_cntrl0    821805907                       # Total read bandwidth from this memory (bytes/s)
2510526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::total             821805907                       # Total read bandwidth from this memory (bytes/s)
2610526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::ruby.dir_cntrl0    819418671                       # Write bandwidth from this memory (bytes/s)
2710526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::total            819418671                       # Write bandwidth from this memory (bytes/s)
2810526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::ruby.dir_cntrl0   1641224577                       # Total bandwidth to/from this memory (bytes/s)
2910526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::total           1641224577                       # Total bandwidth to/from this memory (bytes/s)
3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs                        1377                       # Number of read requests accepted
3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs                       1373                       # Number of write requests accepted
3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts                      1377                       # Number of DRAM read bursts, including those serviced by the write queue
3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts                     1373                       # Number of DRAM write bursts, including those merged in the write queue
3410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM                  42624                       # Total number of bytes read from DRAM
3510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ                   45504                       # Total number of bytes read from write queue
3610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten                   42752                       # Total number of bytes written to DRAM
3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys                   88128                       # Total read bytes from the system interface side
3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys                87872                       # Total written bytes from the system interface side
3910526Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ                    711                       # Number of DRAM read bursts serviced by the write queue
4010526Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts                   686                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0                57                       # Per bank write bursts
4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1                 1                       # Per bank write bursts
4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2                 6                       # Per bank write bursts
4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3                10                       # Per bank write bursts
4610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4                51                       # Per bank write bursts
4710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5                57                       # Per bank write bursts
4810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6                42                       # Per bank write bursts
4910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7                64                       # Per bank write bursts
5010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8                27                       # Per bank write bursts
5110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9               134                       # Per bank write bursts
5210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10              126                       # Per bank write bursts
5310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11               22                       # Per bank write bursts
5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12                2                       # Per bank write bursts
5510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13               28                       # Per bank write bursts
5610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14                7                       # Per bank write bursts
5710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15               32                       # Per bank write bursts
5810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0                50                       # Per bank write bursts
5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1                 1                       # Per bank write bursts
6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2                 6                       # Per bank write bursts
6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3                10                       # Per bank write bursts
6210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4                52                       # Per bank write bursts
6310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5                55                       # Per bank write bursts
6410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6                44                       # Per bank write bursts
6510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7                66                       # Per bank write bursts
6610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8                28                       # Per bank write bursts
6710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9               133                       # Per bank write bursts
6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10              129                       # Per bank write bursts
6910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11               22                       # Per bank write bursts
7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12                2                       # Per bank write bursts
7110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13               30                       # Per bank write bursts
7210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14                7                       # Per bank write bursts
7310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15               33                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7610526Snilay@cs.wisc.edusystem.mem_ctrls.totGap                        107133                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6                  1377                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6                 1373                       # Write request sizes (log2)
9110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0                     666                       # What read queue length does an incoming req see
9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                       0                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15                      6                       # What write queue length does an incoming req see
13910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16                      7                       # What write queue length does an incoming req see
14010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17                     39                       # What write queue length does an incoming req see
14110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18                     43                       # What write queue length does an incoming req see
14210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19                     42                       # What write queue length does an incoming req see
14310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20                     41                       # What write queue length does an incoming req see
14410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21                     43                       # What write queue length does an incoming req see
14510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                     41                       # What write queue length does an incoming req see
14610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                     41                       # What write queue length does an incoming req see
14710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24                     41                       # What write queue length does an incoming req see
14810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25                     41                       # What write queue length does an incoming req see
14910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26                     41                       # What write queue length does an incoming req see
15010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27                     41                       # What write queue length does an incoming req see
15110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                     41                       # What write queue length does an incoming req see
15210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                     41                       # What write queue length does an incoming req see
15310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                     41                       # What write queue length does an incoming req see
15410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                     41                       # What write queue length does an incoming req see
15510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                     41                       # What write queue length does an incoming req see
15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples          272                       # Bytes accessed per row activation
18810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean    306.823529                       # Bytes accessed per row activation
18910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean   199.088320                       # Bytes accessed per row activation
19010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev   295.785748                       # Bytes accessed per row activation
19110526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127           71     26.10%     26.10% # Bytes accessed per row activation
19210526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255           86     31.62%     57.72% # Bytes accessed per row activation
19310526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383           34     12.50%     70.22% # Bytes accessed per row activation
19410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511           20      7.35%     77.57% # Bytes accessed per row activation
19510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639           17      6.25%     83.82% # Bytes accessed per row activation
19610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767            9      3.31%     87.13% # Bytes accessed per row activation
19710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895           11      4.04%     91.18% # Bytes accessed per row activation
19810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023            3      1.10%     92.28% # Bytes accessed per row activation
19910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151           21      7.72%    100.00% # Bytes accessed per row activation
20010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total          272                       # Bytes accessed per row activation
20110526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples           41                       # Reads before turning the bus around for writes
20210526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      16.121951                       # Reads before turning the bus around for writes
20310526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::gmean     15.902045                       # Reads before turning the bus around for writes
20410526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev      3.325621                       # Reads before turning the bus around for writes
20510526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::12-13             2      4.88%      4.88% # Reads before turning the bus around for writes
20610526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::14-15            18     43.90%     48.78% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::16-17            18     43.90%     92.68% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::20-21             2      4.88%     97.56% # Reads before turning the bus around for writes
20910526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::34-35             1      2.44%    100.00% # Reads before turning the bus around for writes
21010526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total            41                       # Reads before turning the bus around for writes
21110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples           41                       # Writes before turning the bus around for reads
21210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean      16.292683                       # Writes before turning the bus around for reads
21310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean     16.274345                       # Writes before turning the bus around for reads
21410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      0.813754                       # Writes before turning the bus around for reads
21510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16               36     87.80%     87.80% # Writes before turning the bus around for reads
21610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18                3      7.32%     95.12% # Writes before turning the bus around for reads
21710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19                2      4.88%    100.00% # Writes before turning the bus around for reads
21810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total            41                       # Writes before turning the bus around for reads
21910526Snilay@cs.wisc.edusystem.mem_ctrls.totQLat                         9844                       # Total ticks spent queuing
22010526Snilay@cs.wisc.edusystem.mem_ctrls.totMemAccLat                   22498                       # Total ticks spent from burst creation until serviced by the DRAM
22110526Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat                       3330                       # Total ticks spent in databus transfers
22210526Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat                        14.78                       # Average queueing delay per DRAM burst
22310526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                       5.00                       # Average bus latency per DRAM burst
22410526Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat                   33.78                       # Average memory access latency per DRAM burst
22510526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                       397.47                       # Average DRAM read bandwidth in MiByte/s
22610526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBW                       398.67                       # Average achieved write bandwidth in MiByte/s
22710526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBWSys                    821.81                       # Average system read bandwidth in MiByte/s
22810526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBWSys                    819.42                       # Average system write bandwidth in MiByte/s
22910526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
23010526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         6.22                       # Data bus utilization in percentage
23110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     3.11                       # Data bus utilization in percentage for reads
23210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    3.11                       # Data bus utilization in percentage for writes
23310526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
23410526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen                      26.04                       # Average write queue length when enqueuing
23510526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits                      427                       # Number of row buffer hits during reads
23610526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits                     625                       # Number of row buffer hits during writes
23710526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate                 64.11                       # Row buffer hit rate for reads
23810526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHitRate                90.98                       # Row buffer hit rate for writes
23910526Snilay@cs.wisc.edusystem.mem_ctrls.avgGap                         38.96                       # Average gap between requests
24010526Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate                    77.75                       # Row buffer hit rate, read and write combined
24110526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::IDLE           6647                       # Time in different power states
24210526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::REF            3380                       # Time in different power states
24310526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
24410526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT           91465                       # Time in different power states
24510526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
24610526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::0                  695520                       # Energy for activate commands per rank (pJ)
24710526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::1                 1270080                       # Energy for activate commands per rank (pJ)
24810526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::0                  386400                       # Energy for precharge commands per rank (pJ)
24910526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::1                  705600                       # Energy for precharge commands per rank (pJ)
25010526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::0                3219840                       # Energy for read commands per rank (pJ)
25110526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::1                4605120                       # Energy for read commands per rank (pJ)
25210526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::0               2623104                       # Energy for write commands per rank (pJ)
25310526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::1               3784320                       # Energy for write commands per rank (pJ)
25410526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::0             6611280                       # Energy for refresh commands per rank (pJ)
25510526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::1             6611280                       # Energy for refresh commands per rank (pJ)
25610526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::0            57894444                       # Energy for active background per rank (pJ)
25710526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::1            62913636                       # Energy for active background per rank (pJ)
25810526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::0            10102200                       # Energy for precharge background per rank (pJ)
25910526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::1             5699400                       # Energy for precharge background per rank (pJ)
26010526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::0              81532788                       # Total energy per rank (pJ)
26110526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::1              85589436                       # Total energy per rank (pJ)
26210526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::0           803.452847                       # Core power per rank (mW)
26310526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::1           843.428487                       # Core power per rank (mW)
26410036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock                        1                       # Clock period in ticks
26510013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
26610013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
26710013Snilay@cs.wisc.edusystem.ruby.delayHist::samples                   2750                       # delay histogram for all message
26810013Snilay@cs.wisc.edusystem.ruby.delayHist                    |        2750    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
26910013Snilay@cs.wisc.edusystem.ruby.delayHist::total                     2750                       # delay histogram for all message
27010013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size            1                      
27110013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket            9                      
27210488Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples         8852                      
27310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean              1                      
27410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean             1                      
27510488Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8852    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
27610488Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total          8852                      
27710526Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size              64                      
27810526Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket              639                      
27910013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples                8852                      
28010526Snilay@cs.wisc.edusystem.ruby.latency_hist::mean              11.114437                      
28110526Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean              4.638311                      
28210526Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev             22.978637                      
28310526Snilay@cs.wisc.edusystem.ruby.latency_hist                 |        8594     97.09%     97.09% |         215      2.43%     99.51% |          29      0.33%     99.84% |           6      0.07%     99.91% |           6      0.07%     99.98% |           2      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
28410013Snilay@cs.wisc.edusystem.ruby.latency_hist::total                  8852                      
28510013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size            1                      
28610013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket            9                      
28710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples            7475                      
28810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean                  3                      
28910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean          3.000000                      
29010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        7475    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
29110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total              7475                      
29210526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size           64                      
29310526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket          639                      
29410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples           1377                      
29510526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean         55.163399                      
29610526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean        49.389613                      
29710526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev        33.121212                      
29810526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist            |        1119     81.26%     81.26% |         215     15.61%     96.88% |          29      2.11%     98.98% |           6      0.44%     99.42% |           6      0.44%     99.85% |           2      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
29910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total             1377                      
30010013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times           1376                      
30110036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
3029698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
3039698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses         1377                       # Number of cache demand misses
3049698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses         8852                       # Number of cache demand accesses
30510526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock                         1                       # Clock period in ticks
30610526Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized     6.411034                      
3079864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2         1377                      
3089864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2         1373                      
3099864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4         1377                      
3109864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3         1373                      
3119864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2        11016                      
3129864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2        98856                      
3139864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4        99144                      
3149864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3        10984                      
31510526Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized     6.411034                      
3169864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2         1377                      
3179864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2         1373                      
3189864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4         1377                      
3199864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3         1373                      
3209864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2        11016                      
3219864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2        98856                      
3229864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4        99144                      
3239864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3        10984                      
32410526Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized     6.411034                      
3259864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2         1377                      
3269864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2         1373                      
3279864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4         1377                      
3289864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3         1373                      
3299864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2        11016                      
3309864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2        98856                      
3319864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4        99144                      
3329864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3        10984                      
3339885Sstever@gmail.comsystem.ruby.network.msg_count.Control            4131                      
3349885Sstever@gmail.comsystem.ruby.network.msg_count.Data               4119                      
3359885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data         4131                      
3369885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control         4119                      
3379885Sstever@gmail.comsystem.ruby.network.msg_byte.Control            33048                      
3389885Sstever@gmail.comsystem.ruby.network.msg_byte.Data              296568                      
3399885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data       297432                      
3409885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control        32952                      
34110036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock                   16                       # Clock period in ticks
3428673SN/Asystem.cpu.workload.num_syscalls                   11                       # Number of system calls
34310526Snilay@cs.wisc.edusystem.cpu.numCycles                           107237                       # number of cpu cycles simulated
3448673SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
3457935SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
3469150SAli.Saidi@ARM.comsystem.cpu.committedInsts                        5381                       # Number of instructions committed
3479583Snilay@cs.wisc.edusystem.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
3489924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses                  9654                       # Number of integer alu accesses
3498673SN/Asystem.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
3509702Snilay@cs.wisc.edusystem.cpu.num_func_calls                         209                       # number of times a function call or return occured
3519150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
3529924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts                         9654                       # number of integer instructions
3537935SN/Asystem.cpu.num_fp_insts                             0                       # number of float instructions
3549924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads               18335                       # number of times the integer registers were read
3559924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes               7527                       # number of times the integer registers were written
3567935SN/Asystem.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
3577935SN/Asystem.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
3589924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads                 6487                       # number of times the CC registers were read
3599924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes                3536                       # number of times the CC registers were written
3609583Snilay@cs.wisc.edusystem.cpu.num_mem_refs                          1988                       # number of memory refs
3619583Snilay@cs.wisc.edusystem.cpu.num_load_insts                        1053                       # Number of load instructions
3629373Snilay@cs.wisc.edusystem.cpu.num_store_insts                        935                       # Number of store instructions
36310526Snilay@cs.wisc.edusystem.cpu.num_idle_cycles                   0.999991                       # Number of idle cycles
36410526Snilay@cs.wisc.edusystem.cpu.num_busy_cycles               107236.000009                       # Number of busy cycles
36510526Snilay@cs.wisc.edusystem.cpu.not_idle_fraction                 0.999991                       # Percentage of non-idle cycles
36610526Snilay@cs.wisc.edusystem.cpu.idle_fraction                     0.000009                       # Percentage of idle cycles
36710063Snilay@cs.wisc.edusystem.cpu.Branches                              1208                       # Number of branches fetched
36810220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass                     1      0.01%      0.01% # Class of executed instruction
36910220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu                      7749     79.49%     79.50% # Class of executed instruction
37010220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult                        3      0.03%     79.53% # Class of executed instruction
37110220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv                         7      0.07%     79.61% # Class of executed instruction
37210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd                       0      0.00%     79.61% # Class of executed instruction
37310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp                       0      0.00%     79.61% # Class of executed instruction
37410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt                       0      0.00%     79.61% # Class of executed instruction
37510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult                      0      0.00%     79.61% # Class of executed instruction
37610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv                       0      0.00%     79.61% # Class of executed instruction
37710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt                      0      0.00%     79.61% # Class of executed instruction
37810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd                        0      0.00%     79.61% # Class of executed instruction
37910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     79.61% # Class of executed instruction
38010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu                        0      0.00%     79.61% # Class of executed instruction
38110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp                        0      0.00%     79.61% # Class of executed instruction
38210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt                        0      0.00%     79.61% # Class of executed instruction
38310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc                       0      0.00%     79.61% # Class of executed instruction
38410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult                       0      0.00%     79.61% # Class of executed instruction
38510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     79.61% # Class of executed instruction
38610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift                      0      0.00%     79.61% # Class of executed instruction
38710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     79.61% # Class of executed instruction
38810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     79.61% # Class of executed instruction
38910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     79.61% # Class of executed instruction
39010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     79.61% # Class of executed instruction
39110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     79.61% # Class of executed instruction
39210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt                   0      0.00%     79.61% # Class of executed instruction
39310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     79.61% # Class of executed instruction
39410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc                  0      0.00%     79.61% # Class of executed instruction
39510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     79.61% # Class of executed instruction
39610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     79.61% # Class of executed instruction
39710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     79.61% # Class of executed instruction
39810220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead                     1053     10.80%     90.41% # Class of executed instruction
39910220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite                     935      9.59%    100.00% # Class of executed instruction
40010220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
40110220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
40210220Sandreas.hansson@arm.comsystem.cpu.op_class::total                       9748                       # Class of executed instruction
40310526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization     6.418494                      
4049864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1377                      
4059864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1373                      
4069864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4        99144                      
4079864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3        10984                      
40810526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization     6.403573                      
4099864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2         1377                      
4109864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2         1373                      
4119864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2        11016                      
4129864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2        98856                      
41310526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization     6.403573                      
4149864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2         1377                      
4159864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2         1373                      
4169864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2        11016                      
4179864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2        98856                      
41810526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization     6.418494                      
4199864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4         1377                      
4209864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3         1373                      
4219864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4        99144                      
4229864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3        10984                      
42310526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization     6.418494                      
4249864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4         1377                      
4259864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3         1373                      
4269864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4        99144                      
4279864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3        10984                      
42810526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization     6.403573                      
4299864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2         1377                      
4309864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2         1373                      
4319864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2        11016                      
4329864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2        98856                      
43310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            1                       # delay histogram for vnet_1
43410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket            9                       # delay histogram for vnet_1
43510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples          1377                       # delay histogram for vnet_1
43610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1           |        1377    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
43710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total            1377                       # delay histogram for vnet_1
43810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
43910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
44010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples          1373                       # delay histogram for vnet_2
44110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2           |        1373    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
44210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total            1373                       # delay histogram for vnet_2
44310526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size           32                      
44410526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket           319                      
44510013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples             1045                      
44610526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean           24.819139                      
44710526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean          10.890845                      
44810526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev          28.082269                      
44910526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist              |         546     52.25%     52.25% |         414     39.62%     91.87% |          77      7.37%     99.23% |           1      0.10%     99.33% |           2      0.19%     99.52% |           4      0.38%     99.90% |           1      0.10%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
45010013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total               1045                      
45110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
45210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
45310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples          546                      
45410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               3                      
45510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean       3.000000                      
45610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         546    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
45710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total            546                      
45810526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size           32                      
45910526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket          319                      
46010013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples          499                      
46110526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean      48.693387                      
46210526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean     44.641812                      
46310526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev     23.667547                      
46410526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist         |           0      0.00%      0.00% |         414     82.97%     82.97% |          77     15.43%     98.40% |           1      0.20%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
46510013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total           499                      
46610526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size           64                      
46710526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket           639                      
46810013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples              935                      
46910526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean           16.765775                      
47010526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean           6.381495                      
47110526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev          28.609452                      
47210526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist              |         895     95.72%     95.72% |          35      3.74%     99.47% |           1      0.11%     99.57% |           2      0.21%     99.79% |           1      0.11%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
47310013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total                935                      
47410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
47510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
47610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples          681                      
47710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               3                      
47810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean       3.000000                      
47910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         681    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
48010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total            681                      
48110526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size           64                      
48210526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket          639                      
48310013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples          254                      
48410526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean      53.673228                      
48510526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean     48.282634                      
48610526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev     33.823763                      
48710526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist         |         214     84.25%     84.25% |          35     13.78%     98.03% |           1      0.39%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
48810013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total           254                      
48910526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size           64                      
49010526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket          639                      
49110013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples         6864                      
49210526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean        8.263112                      
49310526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean       3.900454                      
49410526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev      20.208626                      
49510526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist          |        6731     98.06%     98.06% |         102      1.49%     99.55% |          22      0.32%     99.87% |           3      0.04%     99.91% |           5      0.07%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
49610013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total           6864                      
49710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
49810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
49910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples         6241                      
50010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            3                      
50110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
50210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6241    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
50310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total         6241                      
50410526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
50510526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
50610013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples          623                      
50710526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean    60.987159                      
50810526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean    54.083768                      
50910526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev    37.997755                      
51010526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist     |         490     78.65%     78.65% |         102     16.37%     95.02% |          22      3.53%     98.56% |           3      0.48%     99.04% |           5      0.80%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
51110013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total          623                      
51210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size            4                      
51310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket           39                      
51410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples            8                      
51510526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean      6.875000                      
51610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean     4.063647                      
51710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev    10.960155                      
51810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist        |           7     87.50%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           0      0.00%     87.50% |           1     12.50%    100.00% |           0      0.00%    100.00%
51910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total            8                      
52010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
52110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
52210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples            7                      
52310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            3                      
52410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
52510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           7    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
52610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total            7                      
52710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size            4                      
52810526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket           39                      
52910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples            1                      
53010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean           34                      
53110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean    34.000000                      
53210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev          nan                      
53310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist   |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
53410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total            1                      
53510526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size           64                      
53610526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
53710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples         1377                      
53810526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean    55.163399                      
53910526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean    49.389613                      
54010526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev    33.121212                      
54110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist |        1119     81.26%     81.26% |         215     15.61%     96.88% |          29      2.11%     98.98% |           6      0.44%     99.42% |           6      0.44%     99.85% |           2      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
54210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total         1377                      
54310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
54410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
54510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples            1                      
54610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev          nan                      
54710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
54810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total            1                      
54910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size            1                      
55010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket            9                      
55110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples            1                      
55210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev          nan                      
55310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
55410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total            1                      
55510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size            1                      
55610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket            9                      
55710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples            1                      
55810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev          nan                      
55910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response |           1    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
56010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total            1                      
56110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size            8                      
56210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket           79                      
56310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples            1                      
56410526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean           75                      
56510526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean    75.000000                      
56610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev          nan                      
56710526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00%
56810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total            1                      
56910526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size           32                      
57010526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket          319                      
57110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples          499                      
57210526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean    48.693387                      
57310526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean    44.641812                      
57410526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev    23.667547                      
57510526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         414     82.97%     82.97% |          77     15.43%     98.40% |           1      0.20%     98.60% |           2      0.40%     99.00% |           4      0.80%     99.80% |           1      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
57610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total          499                      
57710526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size           64                      
57810526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket          639                      
57910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples          254                      
58010526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean    53.673228                      
58110526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean    48.282634                      
58210526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev    33.823763                      
58310526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist |         214     84.25%     84.25% |          35     13.78%     98.03% |           1      0.39%     98.43% |           2      0.79%     99.21% |           1      0.39%     99.61% |           1      0.39%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total          254                      
58510526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size           64                      
58610526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
58710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          623                      
58810526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    60.987159                      
58910526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    54.083768                      
59010526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    37.997755                      
59110526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         490     78.65%     78.65% |         102     16.37%     95.02% |          22      3.53%     98.56% |           3      0.48%     99.04% |           5      0.80%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          623                      
59310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size            4                      
59410526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket           39                      
59510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples            1                      
59610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean           34                      
59710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean    34.000000                      
59810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev          nan                      
59910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |           1    100.00%    100.00% |           0      0.00%    100.00%
60010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total            1                      
60110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load              1045      0.00%      0.00%
60210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch            6864      0.00%      0.00%
60310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store              943      0.00%      0.00%
60410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data              1377      0.00%      0.00%
60510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement         1373      0.00%      0.00%
60610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack         1373      0.00%      0.00%
60710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load             499      0.00%      0.00%
60810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch           623      0.00%      0.00%
60910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store            255      0.00%      0.00%
61010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load             546      0.00%      0.00%
61110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch          6241      0.00%      0.00%
61210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store            688      0.00%      0.00%
61310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement         1373      0.00%      0.00%
61410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack         1373      0.00%      0.00%
61510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data           1122      0.00%      0.00%
61610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data            255      0.00%      0.00%
61710013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX            1377      0.00%      0.00%
61810013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX            1373      0.00%      0.00%
61910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data         1377      0.00%      0.00%
62010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack         1373      0.00%      0.00%
62110013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX          1377      0.00%      0.00%
62210013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX          1373      0.00%      0.00%
62310013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data         1377      0.00%      0.00%
62410013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack         1373      0.00%      0.00%
6256167SN/A
6266167SN/A---------- End Simulation Statistics   ----------
627