stats.txt revision 10220
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 39204Sandreas.hansson@arm.comsim_seconds 0.000122 # Number of seconds simulated 49204Sandreas.hansson@arm.comsim_ticks 121759 # Number of ticks simulated 59204Sandreas.hansson@arm.comfinal_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 47256 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 85597 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 1069027 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 179456 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.11 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 1710013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 1810013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 1910013Snilay@cs.wisc.edusystem.ruby.delayHist::samples 2750 # delay histogram for all message 2010013Snilay@cs.wisc.edusystem.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 2110013Snilay@cs.wisc.edusystem.ruby.delayHist::total 2750 # delay histogram for all message 2210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size 1 2310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket 9 2410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples 8853 2510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean 1 2610013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean 1 2710013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 2810013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total 8853 2910013Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size 16 3010013Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket 159 3110013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples 8852 3210013Snilay@cs.wisc.edusystem.ruby.latency_hist::mean 12.754971 3310013Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean 4.846146 3410013Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev 22.865469 3510013Snilay@cs.wisc.edusystem.ruby.latency_hist | 7475 84.44% 84.44% | 0 0.00% 84.44% | 0 0.00% 84.44% | 329 3.72% 88.16% | 977 11.04% 99.20% | 69 0.78% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3610013Snilay@cs.wisc.edusystem.ruby.latency_hist::total 8852 3710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size 1 3810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket 9 3910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples 7475 4010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean 3 4110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean 3.000000 4210013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 4310013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total 7475 4410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size 16 4510013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket 159 4610013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples 1377 4710013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean 65.709513 4810013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean 65.465397 4910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev 6.315805 5010013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 5110013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total 1377 5210013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times 1376 5310036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 549698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 559698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 569698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 579864Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized 5.646400 589864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2 1377 599864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2 1373 609864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4 1377 619864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3 1373 629864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2 11016 639864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2 98856 649864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4 99144 659864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 669748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReq 2750 # Total number of memory requests 679748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRead 1377 # Number of memory reads 689748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWrite 1373 # Number of memory writes 699748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRefresh 846 # Number of memory refreshes 709748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWaitCycles 1965 # Delay stalled at the head of the bank queue 719748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue 729748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.totalStalls 1968 # Total number of stall cycles 739748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.715636 # Expected number of stall cycles per request 749748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankBusy 823 # memory stalls due to busy bank 759748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBusBusy 1044 # memory stalls due to busy bus 769748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 33 # memory stalls due to read write turnaround 779748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memArbWait 65 # memory stalls due to arbitration 789748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount | 160 5.82% 5.82% | 144 5.24% 11.05% | 210 7.64% 18.69% | 146 5.31% 24.00% | 196 7.13% 31.13% | 96 3.49% 34.62% | 66 2.40% 37.02% | 38 1.38% 38.40% | 22 0.80% 39.20% | 20 0.73% 39.93% | 184 6.69% 46.62% | 297 10.80% 57.42% | 71 2.58% 60.00% | 124 4.51% 64.51% | 60 2.18% 66.69% | 18 0.65% 67.35% | 84 3.05% 70.40% | 6 0.22% 70.62% | 8 0.29% 70.91% | 14 0.51% 71.42% | 92 3.35% 74.76% | 56 2.04% 76.80% | 14 0.51% 77.31% | 60 2.18% 79.49% | 34 1.24% 80.73% | 58 2.11% 82.84% | 84 3.05% 85.89% | 66 2.40% 88.29% | 42 1.53% 89.82% | 122 4.44% 94.25% | 104 3.78% 98.04% | 54 1.96% 100.00% # Number of accesses per bank 799748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount::total 2750 # Number of accesses per bank 809864Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized 5.646400 819864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2 1377 829864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2 1373 839864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4 1377 849864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3 1373 859864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2 11016 869864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2 98856 879864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4 99144 889864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 899864Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized 5.646400 909864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2 1377 919864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2 1373 929864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4 1377 939864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3 1373 949864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2 11016 959864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2 98856 969864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4 99144 979864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 989885Sstever@gmail.comsystem.ruby.network.msg_count.Control 4131 999885Sstever@gmail.comsystem.ruby.network.msg_count.Data 4119 1009885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data 4131 1019885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control 4119 1029885Sstever@gmail.comsystem.ruby.network.msg_byte.Control 33048 1039885Sstever@gmail.comsystem.ruby.network.msg_byte.Data 296568 1049885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data 297432 1059885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control 32952 10610036SAli.Saidi@ARM.comsystem.cpu.clk_domain.clock 1 # Clock period in ticks 10710036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 16 # Clock period in ticks 1088673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 1099204Sandreas.hansson@arm.comsystem.cpu.numCycles 121759 # number of cpu cycles simulated 1108673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1117935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1129150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 1139583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 1149924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 1158673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 1169702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 1179150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 1189924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 1197935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 1209924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 1219924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 1227935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 1237935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1249924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 1259924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 1269583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 1279583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 1289373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 1297935SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 1309204Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 121759 # Number of busy cycles 1318673SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 1328673SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 13310063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 13410220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction 13510220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction 13610220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction 13710220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction 13810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction 13910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction 14010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction 14110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction 14210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction 14310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction 14410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction 14510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction 14610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction 14710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction 14810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction 14910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction 15010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction 15110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction 15210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction 15310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction 15410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction 15510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction 15610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction 15710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction 15810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction 15910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction 16010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction 16110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction 16210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction 16310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction 16410220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction 16510220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction 16610220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 16710220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 16810220Sandreas.hansson@arm.comsystem.cpu.op_class::total 9748 # Class of executed instruction 1699864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization 5.652970 1709864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 1719864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 1729864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 1739864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 1749864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization 5.639829 1759864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1377 1769864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1373 1779864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 1789864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 1799864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization 5.639829 1809864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1377 1819864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1373 1829864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 1839864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 1849864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization 5.652970 1859864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 1869864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 1879864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 1889864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 1899864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization 5.652970 1909864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 1919864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 1929864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 1939864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 1949864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization 5.639829 1959864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1377 1969864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1373 1979864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 1989864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 19910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 20010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 20110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 20210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 20310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 20410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 20510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 20610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 20710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 20810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 20910013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size 16 21010013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket 159 21110013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 1045 21210013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean 33.084211 21310013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean 13.097827 21410013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev 31.853421 21510013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist | 546 52.25% 52.25% | 0 0.00% 52.25% | 0 0.00% 52.25% | 105 10.05% 62.30% | 361 34.55% 96.84% | 32 3.06% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21610013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 1045 21710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 21810013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 21910013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 546 22010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 22110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 22210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 22310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 546 22410013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size 16 22510013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket 159 22610013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 499 22710013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean 66.002004 22810013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean 65.699964 22910013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev 7.001864 23010013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 23110013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 499 23210013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 16 23310013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 159 23410013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 935 23510013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean 20.084492 23610013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean 6.936580 23710013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev 28.187775 23810013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist | 681 72.83% 72.83% | 0 0.00% 72.83% | 0 0.00% 72.83% | 62 6.63% 79.47% | 177 18.93% 98.40% | 15 1.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 23910013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 935 24010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 24110013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 24210013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 681 24310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 24410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 24510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 24610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 681 24710013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 16 24810013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 159 24910013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 254 25010013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean 65.889764 25110013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean 65.634390 25210013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev 6.416664 25310013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 25410013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 254 25510013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 16 25610013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 159 25710013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 6864 25810013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean 8.663899 25910013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean 3.967250 26010013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev 18.008804 26110013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist | 6241 90.92% 90.92% | 0 0.00% 90.92% | 0 0.00% 90.92% | 162 2.36% 93.28% | 438 6.38% 99.66% | 22 0.32% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 26210013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 6864 26310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 26410013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 26510013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 6241 26610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 26710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 26810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 26910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 6241 27010013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 16 27110013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 159 27210013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 623 27310013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean 65.402889 27410013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean 65.210291 27510013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev 5.662802 27610013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27710013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 623 27810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size 8 27910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket 79 28010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples 8 28110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean 10.750000 28210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean 4.406515 28310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev 21.920310 28410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 28510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total 8 28610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size 1 28710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket 9 28810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples 7 28910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean 3 29010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 29110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total 7 29310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size 8 29410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket 79 29510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples 1 29610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean 65 29710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean 65.000000 29810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev nan 29910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 30010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total 1 30110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 16 30210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 159 30310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1377 30410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean 65.709513 30510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean 65.465397 30610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev 6.315805 30710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1377 30910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 31010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 31110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 31210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 31310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 31510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 31610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 31710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 31810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 31910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 32110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 32210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 32310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 32410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 32510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 32710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 32810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 32910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 33010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61 33110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000 33210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 33310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 33410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 33510013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 33610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 33710013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 33810013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 66.002004 33910013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.699964 34010013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.001864 34110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 34310013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 34410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 34510013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 34610013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.889764 34710013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.634390 34810013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.416664 34910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 35110013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 35210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 35310013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 35410013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.402889 35510013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.210291 35610013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 5.662802 35710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 35910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 8 36010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 79 36110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 36210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 65 36310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 65.000000 36410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan 36510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 36610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 36710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 36810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 36910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 37010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 37110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 37210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 37310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 37410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 37510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 37610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 37710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 37810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 37910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 38010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 38110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 38210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 38310013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 38410013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 38510013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 38610013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 38710013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 38810013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 38910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 39010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 3916167SN/A 3926167SN/A---------- End Simulation Statistics ---------- 393