stats.txt revision 10063
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 39204Sandreas.hansson@arm.comsim_seconds 0.000122 # Number of seconds simulated 49204Sandreas.hansson@arm.comsim_ticks 121759 # Number of ticks simulated 59204Sandreas.hansson@arm.comfinal_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68673SN/Asim_freq 1000000000 # Frequency of simulated ticks 710063Snilay@cs.wisc.eduhost_inst_rate 29778 # Simulator instruction rate (inst/s) 810063Snilay@cs.wisc.eduhost_op_rate 53940 # Simulator op (including micro ops) rate (op/s) 910063Snilay@cs.wisc.eduhost_tick_rate 673676 # Simulator tick rate (ticks/s) 1010063Snilay@cs.wisc.eduhost_mem_usage 193492 # Number of bytes of host memory used 1110063Snilay@cs.wisc.eduhost_seconds 0.18 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5381 # Number of instructions simulated 139583Snilay@cs.wisc.edusim_ops 9748 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 1710013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 1810013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 1910013Snilay@cs.wisc.edusystem.ruby.delayHist::samples 2750 # delay histogram for all message 2010013Snilay@cs.wisc.edusystem.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 2110013Snilay@cs.wisc.edusystem.ruby.delayHist::total 2750 # delay histogram for all message 2210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size 1 2310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket 9 2410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples 8853 2510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean 1 2610013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean 1 2710013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 2810013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total 8853 2910013Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size 16 3010013Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket 159 3110013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples 8852 3210013Snilay@cs.wisc.edusystem.ruby.latency_hist::mean 12.754971 3310013Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean 4.846146 3410013Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev 22.865469 3510013Snilay@cs.wisc.edusystem.ruby.latency_hist | 7475 84.44% 84.44% | 0 0.00% 84.44% | 0 0.00% 84.44% | 329 3.72% 88.16% | 977 11.04% 99.20% | 69 0.78% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3610013Snilay@cs.wisc.edusystem.ruby.latency_hist::total 8852 3710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size 1 3810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket 9 3910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples 7475 4010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean 3 4110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean 3.000000 4210013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 4310013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total 7475 4410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size 16 4510013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket 159 4610013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples 1377 4710013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean 65.709513 4810013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean 65.465397 4910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev 6.315805 5010013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 5110013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total 1377 5210013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times 1376 5310036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 549698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits 559698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses 569698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses 579864Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized 5.646400 589864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2 1377 599864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2 1373 609864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4 1377 619864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3 1373 629864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2 11016 639864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2 98856 649864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4 99144 659864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 669748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReq 2750 # Total number of memory requests 679748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRead 1377 # Number of memory reads 689748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWrite 1373 # Number of memory writes 699748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRefresh 846 # Number of memory refreshes 709748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWaitCycles 1965 # Delay stalled at the head of the bank queue 719748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue 729748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.totalStalls 1968 # Total number of stall cycles 739748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.715636 # Expected number of stall cycles per request 749748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankBusy 823 # memory stalls due to busy bank 759748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBusBusy 1044 # memory stalls due to busy bus 769748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 33 # memory stalls due to read write turnaround 779748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memArbWait 65 # memory stalls due to arbitration 789748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount | 160 5.82% 5.82% | 144 5.24% 11.05% | 210 7.64% 18.69% | 146 5.31% 24.00% | 196 7.13% 31.13% | 96 3.49% 34.62% | 66 2.40% 37.02% | 38 1.38% 38.40% | 22 0.80% 39.20% | 20 0.73% 39.93% | 184 6.69% 46.62% | 297 10.80% 57.42% | 71 2.58% 60.00% | 124 4.51% 64.51% | 60 2.18% 66.69% | 18 0.65% 67.35% | 84 3.05% 70.40% | 6 0.22% 70.62% | 8 0.29% 70.91% | 14 0.51% 71.42% | 92 3.35% 74.76% | 56 2.04% 76.80% | 14 0.51% 77.31% | 60 2.18% 79.49% | 34 1.24% 80.73% | 58 2.11% 82.84% | 84 3.05% 85.89% | 66 2.40% 88.29% | 42 1.53% 89.82% | 122 4.44% 94.25% | 104 3.78% 98.04% | 54 1.96% 100.00% # Number of accesses per bank 799748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount::total 2750 # Number of accesses per bank 809864Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized 5.646400 819864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2 1377 829864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2 1373 839864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4 1377 849864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3 1373 859864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2 11016 869864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2 98856 879864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4 99144 889864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 899864Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized 5.646400 909864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2 1377 919864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2 1373 929864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4 1377 939864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3 1373 949864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2 11016 959864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2 98856 969864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4 99144 979864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 989885Sstever@gmail.comsystem.ruby.network.msg_count.Control 4131 999885Sstever@gmail.comsystem.ruby.network.msg_count.Data 4119 1009885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data 4131 1019885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control 4119 1029885Sstever@gmail.comsystem.ruby.network.msg_byte.Control 33048 1039885Sstever@gmail.comsystem.ruby.network.msg_byte.Data 296568 1049885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data 297432 1059885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control 32952 10610036SAli.Saidi@ARM.comsystem.cpu.clk_domain.clock 1 # Clock period in ticks 10710036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 16 # Clock period in ticks 1088673SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 1099204Sandreas.hansson@arm.comsystem.cpu.numCycles 121759 # number of cpu cycles simulated 1108673SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1117935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1129150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5381 # Number of instructions committed 1139583Snilay@cs.wisc.edusystem.cpu.committedOps 9748 # Number of ops (including micro ops) committed 1149924Ssteve.reinhardt@amd.comsystem.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses 1158673SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 1169702Snilay@cs.wisc.edusystem.cpu.num_func_calls 209 # number of times a function call or return occured 1179150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls 1189924Ssteve.reinhardt@amd.comsystem.cpu.num_int_insts 9654 # number of integer instructions 1197935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 1209924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_reads 18335 # number of times the integer registers were read 1219924Ssteve.reinhardt@amd.comsystem.cpu.num_int_register_writes 7527 # number of times the integer registers were written 1227935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 1237935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1249924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_reads 6487 # number of times the CC registers were read 1259924Ssteve.reinhardt@amd.comsystem.cpu.num_cc_register_writes 3536 # number of times the CC registers were written 1269583Snilay@cs.wisc.edusystem.cpu.num_mem_refs 1988 # number of memory refs 1279583Snilay@cs.wisc.edusystem.cpu.num_load_insts 1053 # Number of load instructions 1289373Snilay@cs.wisc.edusystem.cpu.num_store_insts 935 # Number of store instructions 1297935SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 1309204Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 121759 # Number of busy cycles 1318673SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 1328673SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 13310063Snilay@cs.wisc.edusystem.cpu.Branches 1208 # Number of branches fetched 1349864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization 5.652970 1359864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 1369864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 1379864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 1389864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 1399864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization 5.639829 1409864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1377 1419864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1373 1429864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 1439864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 1449864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization 5.639829 1459864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1377 1469864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1373 1479864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 1489864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 1499864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization 5.652970 1509864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 1519864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 1529864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 1539864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 1549864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization 5.652970 1559864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 1569864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 1579864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 1589864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 1599864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization 5.639829 1609864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1377 1619864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1373 1629864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 1639864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 16410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 16510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 16610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 16710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 16810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 16910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 17010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 17110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 17210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 17310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 17410013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size 16 17510013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket 159 17610013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 1045 17710013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean 33.084211 17810013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean 13.097827 17910013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev 31.853421 18010013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist | 546 52.25% 52.25% | 0 0.00% 52.25% | 0 0.00% 52.25% | 105 10.05% 62.30% | 361 34.55% 96.84% | 32 3.06% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 18110013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 1045 18210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 18310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 18410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 546 18510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 18610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 18710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 18810013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 546 18910013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size 16 19010013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket 159 19110013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 499 19210013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean 66.002004 19310013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean 65.699964 19410013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev 7.001864 19510013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 19610013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 499 19710013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 16 19810013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 159 19910013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 935 20010013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean 20.084492 20110013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean 6.936580 20210013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev 28.187775 20310013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist | 681 72.83% 72.83% | 0 0.00% 72.83% | 0 0.00% 72.83% | 62 6.63% 79.47% | 177 18.93% 98.40% | 15 1.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 20410013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 935 20510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 20610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 20710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 681 20810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 20910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 21010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21110013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 681 21210013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 16 21310013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 159 21410013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 254 21510013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean 65.889764 21610013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean 65.634390 21710013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev 6.416664 21810013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21910013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 254 22010013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 16 22110013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 159 22210013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 6864 22310013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean 8.663899 22410013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean 3.967250 22510013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev 18.008804 22610013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist | 6241 90.92% 90.92% | 0 0.00% 90.92% | 0 0.00% 90.92% | 162 2.36% 93.28% | 438 6.38% 99.66% | 22 0.32% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 22710013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 6864 22810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 22910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 23010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 6241 23110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 23210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 23310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 23410013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 6241 23510013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 16 23610013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 159 23710013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 623 23810013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean 65.402889 23910013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean 65.210291 24010013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev 5.662802 24110013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 24210013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 623 24310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size 8 24410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket 79 24510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples 8 24610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean 10.750000 24710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean 4.406515 24810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev 21.920310 24910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% 25010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total 8 25110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size 1 25210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket 9 25310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples 7 25410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean 3 25510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 25610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 25710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total 7 25810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size 8 25910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket 79 26010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples 1 26110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean 65 26210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean 65.000000 26310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev nan 26410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 26510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total 1 26610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 16 26710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 159 26810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1377 26910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean 65.709513 27010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean 65.465397 27110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev 6.315805 27210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1377 27410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 27510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 27610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 27710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 27810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 28010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 28110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 28210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 28310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 28410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 28610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 28710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 28810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 28910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 29010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 29210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 29310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 29410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 29510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61 29610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000 29710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 29810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 30010013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 30110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 30210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 30310013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 66.002004 30410013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.699964 30510013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.001864 30610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30710013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 30810013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 30910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 31010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 31110013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.889764 31210013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.634390 31310013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.416664 31410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31510013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 31610013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 31710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 31810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 31910013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.402889 32010013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.210291 32110013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 5.662802 32210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32310013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 32410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 8 32510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 79 32610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 32710013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 65 32810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 65.000000 32910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan 33010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% 33110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 33210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% 33310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% 33410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 943 0.00% 0.00% 33510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1377 0.00% 0.00% 33610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00% 33710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00% 33810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00% 33910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00% 34010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00% 34110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00% 34210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00% 34310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00% 34410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% 34510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% 34610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% 34710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% 34810013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX 1377 0.00% 0.00% 34910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% 35010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% 35110013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% 35210013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% 35310013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% 35410013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% 35510013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% 3566167SN/A 3576167SN/A---------- End Simulation Statistics ---------- 358