stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 15474000 # Number of ticks simulated 5final_tick 15474000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 16433 # Simulator instruction rate (inst/s) 8host_op_rate 29770 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47259450 # Simulator tick rate (ticks/s) 10host_mem_usage 286708 # Number of bytes of host memory used 11host_seconds 0.33 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1253198914 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 603851622 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1857050536 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1253198914 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1253198914 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1253198914 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 603851622 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1857050536 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 451 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 28736 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 15458000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 451 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 1899500 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests 154system.physmem.totBusLat 2255000 # Total cycles spent in databus access 155system.physmem.totBankLat 9006250 # Total cycles spent in bank access 156system.physmem.avgQLat 4211.75 # Average queueing delay per request 157system.physmem.avgBankLat 19969.51 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 29181.26 # Average memory access latency 160system.physmem.avgRdBW 1857.05 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 1857.05 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 14.51 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.85 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 333 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 34274.94 # Average gap between requests 173system.cpu.branchPred.lookups 2993 # Number of BP lookups 174system.cpu.branchPred.condPredicted 2993 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 2483 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 793 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 31.937173 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 182system.cpu.workload.num_syscalls 11 # Number of system calls 183system.cpu.numCycles 30949 # number of cpu cycles simulated 184system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 185system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 186system.cpu.fetch.icacheStallCycles 8903 # Number of cycles fetch is stalled on an Icache miss 187system.cpu.fetch.Insts 14396 # Number of instructions fetch has processed 188system.cpu.fetch.Branches 2993 # Number of branches that fetch encountered 189system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken 190system.cpu.fetch.Cycles 3910 # Number of cycles fetch has run and was not squashing or blocked 191system.cpu.fetch.SquashCycles 2411 # Number of cycles fetch has spent squashing 192system.cpu.fetch.BlockedCycles 3703 # Number of cycles fetch has spent blocked 193system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 194system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps 195system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 196system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched 197system.cpu.fetch.IcacheSquashes 286 # Number of outstanding Icache misses that were squashed 198system.cpu.fetch.rateDist::samples 18564 # Number of instructions fetched each cycle (Total) 199system.cpu.fetch.rateDist::mean 1.369856 # Number of instructions fetched each cycle (Total) 200system.cpu.fetch.rateDist::stdev 2.872055 # Number of instructions fetched each cycle (Total) 201system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 202system.cpu.fetch.rateDist::0 14753 79.47% 79.47% # Number of instructions fetched each cycle (Total) 203system.cpu.fetch.rateDist::1 190 1.02% 80.49% # Number of instructions fetched each cycle (Total) 204system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total) 205system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::5 168 0.90% 84.14% # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::6 264 1.42% 85.56% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::7 161 0.87% 86.43% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::8 2519 13.57% 100.00% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::total 18564 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.branchRate 0.096707 # Number of branch fetches per cycle 216system.cpu.fetch.rate 0.465152 # Number of inst fetches per cycle 217system.cpu.decode.IdleCycles 9437 # Number of cycles decode is idle 218system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked 219system.cpu.decode.RunCycles 3520 # Number of cycles decode is running 220system.cpu.decode.UnblockCycles 143 # Number of cycles decode is unblocking 221system.cpu.decode.SquashCycles 1818 # Number of cycles decode is squashing 222system.cpu.decode.DecodedInsts 24283 # Number of instructions handled by decode 223system.cpu.rename.SquashCycles 1818 # Number of cycles rename is squashing 224system.cpu.rename.IdleCycles 9780 # Number of cycles rename is idle 225system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking 226system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst 227system.cpu.rename.RunCycles 3306 # Number of cycles rename is running 228system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking 229system.cpu.rename.RenamedInsts 22784 # Number of instructions processed by rename 230system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 231system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full 232system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full 233system.cpu.rename.RenamedOperands 24893 # Number of destination operands rename has renamed 234system.cpu.rename.RenameLookups 54727 # Number of register rename lookups that rename has made 235system.cpu.rename.int_rename_lookups 54711 # Number of integer rename lookups 236system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 237system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed 238system.cpu.rename.UndoneMaps 13830 # Number of HB maps that are undone due to squashing 239system.cpu.rename.serializingInsts 34 # count of serializing insts renamed 240system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed 241system.cpu.rename.skidInsts 2066 # count of insts added to the skid buffer 242system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit. 243system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit. 244system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 245system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 246system.cpu.iq.iqInstsAdded 20310 # Number of instructions added to the IQ (excludes non-spec) 247system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ 248system.cpu.iq.iqInstsIssued 17272 # Number of instructions issued 249system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued 250system.cpu.iq.iqSquashedInstsExamined 9822 # Number of squashed instructions iterated over during squash; mainly for profiling 251system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph 252system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed 253system.cpu.iq.issued_per_cycle::samples 18564 # Number of insts issued each cycle 254system.cpu.iq.issued_per_cycle::mean 0.930403 # Number of insts issued each cycle 255system.cpu.iq.issued_per_cycle::stdev 1.788380 # Number of insts issued each cycle 256system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 257system.cpu.iq.issued_per_cycle::0 13176 70.98% 70.98% # Number of insts issued each cycle 258system.cpu.iq.issued_per_cycle::1 1404 7.56% 78.54% # Number of insts issued each cycle 259system.cpu.iq.issued_per_cycle::2 1053 5.67% 84.21% # Number of insts issued each cycle 260system.cpu.iq.issued_per_cycle::3 694 3.74% 87.95% # Number of insts issued each cycle 261system.cpu.iq.issued_per_cycle::4 727 3.92% 91.87% # Number of insts issued each cycle 262system.cpu.iq.issued_per_cycle::5 623 3.36% 95.22% # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::total 18564 # Number of insts issued each cycle 270system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 271system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available 272system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available 273system.cpu.iq.fu_full::IntDiv 0 0.00% 76.30% # attempts to use FU when none available 274system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.30% # attempts to use FU when none available 275system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.30% # attempts to use FU when none available 276system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.30% # attempts to use FU when none available 277system.cpu.iq.fu_full::FloatMult 0 0.00% 76.30% # attempts to use FU when none available 278system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.30% # attempts to use FU when none available 279system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.30% # attempts to use FU when none available 280system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.30% # attempts to use FU when none available 281system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.30% # attempts to use FU when none available 282system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.30% # attempts to use FU when none available 283system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.30% # attempts to use FU when none available 284system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.30% # attempts to use FU when none available 285system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.30% # attempts to use FU when none available 286system.cpu.iq.fu_full::SimdMult 0 0.00% 76.30% # attempts to use FU when none available 287system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.30% # attempts to use FU when none available 288system.cpu.iq.fu_full::SimdShift 0 0.00% 76.30% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.30% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.30% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.30% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.30% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.30% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.30% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.30% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.30% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.30% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.30% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.30% # attempts to use FU when none available 300system.cpu.iq.fu_full::MemRead 20 11.56% 87.86% # attempts to use FU when none available 301system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # attempts to use FU when none available 302system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 303system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 304system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued 305system.cpu.iq.FU_type_0::IntAlu 13885 80.39% 80.41% # Type of FU issued 306system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued 307system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued 308system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued 309system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.41% # Type of FU issued 310system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.41% # Type of FU issued 311system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.41% # Type of FU issued 312system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.41% # Type of FU issued 313system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.41% # Type of FU issued 314system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.41% # Type of FU issued 315system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.41% # Type of FU issued 316system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.41% # Type of FU issued 317system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.41% # Type of FU issued 318system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.41% # Type of FU issued 319system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.41% # Type of FU issued 320system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.41% # Type of FU issued 321system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.41% # Type of FU issued 322system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.41% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.41% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.41% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.41% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.41% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.41% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.41% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.41% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued 334system.cpu.iq.FU_type_0::MemRead 1904 11.02% 91.43% # Type of FU issued 335system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued 336system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 337system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 338system.cpu.iq.FU_type_0::total 17272 # Type of FU issued 339system.cpu.iq.rate 0.558079 # Inst issue rate 340system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 341system.cpu.iq.fu_busy_rate 0.010016 # FU busy rate (busy events/executed inst) 342system.cpu.iq.int_inst_queue_reads 53478 # Number of integer instruction queue reads 343system.cpu.iq.int_inst_queue_writes 30175 # Number of integer instruction queue writes 344system.cpu.iq.int_inst_queue_wakeup_accesses 15918 # Number of integer instruction queue wakeup accesses 345system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 346system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 347system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses 348system.cpu.iq.int_alu_accesses 17438 # Number of integer alu accesses 349system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 350system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores 351system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 352system.cpu.iew.lsq.thread0.squashedLoads 1149 # Number of loads squashed 353system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed 354system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 355system.cpu.iew.lsq.thread0.squashedStores 813 # Number of stores squashed 356system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 357system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 358system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 359system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked 360system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 361system.cpu.iew.iewSquashCycles 1818 # Number of cycles IEW is squashing 362system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking 363system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking 364system.cpu.iew.iewDispatchedInsts 20346 # Number of instructions dispatched to IQ 365system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch 366system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions 367system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions 368system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions 369system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 370system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 371system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 372system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly 373system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly 374system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute 375system.cpu.iew.iewExecutedInsts 16347 # Number of executed instructions 376system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed 377system.cpu.iew.iewExecSquashedInsts 925 # Number of squashed instructions skipped in execute 378system.cpu.iew.exec_swp 0 # number of swp insts executed 379system.cpu.iew.exec_nop 0 # number of nop insts executed 380system.cpu.iew.exec_refs 3143 # number of memory reference insts executed 381system.cpu.iew.exec_branches 1619 # Number of branches executed 382system.cpu.iew.exec_stores 1363 # Number of stores executed 383system.cpu.iew.exec_rate 0.528192 # Inst execution rate 384system.cpu.iew.wb_sent 16117 # cumulative count of insts sent to commit 385system.cpu.iew.wb_count 15922 # cumulative count of insts written-back 386system.cpu.iew.wb_producers 10116 # num instructions producing a value 387system.cpu.iew.wb_consumers 15624 # num instructions consuming a value 388system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 389system.cpu.iew.wb_rate 0.514459 # insts written-back per cycle 390system.cpu.iew.wb_fanout 0.647465 # average fanout of values written-back 391system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 392system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit 393system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 394system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted 395system.cpu.commit.committed_per_cycle::samples 16746 # Number of insts commited each cycle 396system.cpu.commit.committed_per_cycle::mean 0.582049 # Number of insts commited each cycle 397system.cpu.commit.committed_per_cycle::stdev 1.457997 # Number of insts commited each cycle 398system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 399system.cpu.commit.committed_per_cycle::0 13211 78.89% 78.89% # Number of insts commited each cycle 400system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle 401system.cpu.commit.committed_per_cycle::2 595 3.55% 90.37% # Number of insts commited each cycle 402system.cpu.commit.committed_per_cycle::3 703 4.20% 94.57% # Number of insts commited each cycle 403system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle 404system.cpu.commit.committed_per_cycle::5 140 0.84% 97.53% # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::6 119 0.71% 98.24% # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::total 16746 # Number of insts commited each cycle 412system.cpu.commit.committedInsts 5380 # Number of instructions committed 413system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 414system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 415system.cpu.commit.refs 1988 # Number of memory references committed 416system.cpu.commit.loads 1053 # Number of loads committed 417system.cpu.commit.membars 0 # Number of memory barriers committed 418system.cpu.commit.branches 1208 # Number of branches committed 419system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 420system.cpu.commit.int_insts 9654 # Number of committed integer instructions. 421system.cpu.commit.function_calls 0 # Number of function calls committed. 422system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached 423system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 424system.cpu.rob.rob_reads 36870 # The number of ROB reads 425system.cpu.rob.rob_writes 42537 # The number of ROB writes 426system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself 427system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling 428system.cpu.committedInsts 5380 # Number of Instructions Simulated 429system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 430system.cpu.committedInsts_total 5380 # Number of Instructions Simulated 431system.cpu.cpi 5.752602 # CPI: Cycles Per Instruction 432system.cpu.cpi_total 5.752602 # CPI: Total CPI of All Threads 433system.cpu.ipc 0.173834 # IPC: Instructions Per Cycle 434system.cpu.ipc_total 0.173834 # IPC: Total IPC of All Threads 435system.cpu.int_regfile_reads 28776 # number of integer regfile reads 436system.cpu.int_regfile_writes 17146 # number of integer regfile writes 437system.cpu.fp_regfile_reads 4 # number of floating regfile reads 438system.cpu.misc_regfile_reads 7131 # number of misc regfile reads 439system.cpu.misc_regfile_writes 1 # number of misc regfile writes 440system.cpu.icache.replacements 0 # number of replacements 441system.cpu.icache.tagsinuse 144.810143 # Cycle average of tags in use 442system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. 443system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. 444system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. 445system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 446system.cpu.icache.occ_blocks::cpu.inst 144.810143 # Average occupied blocks per requestor 447system.cpu.icache.occ_percent::cpu.inst 0.070708 # Average percentage of cache occupancy 448system.cpu.icache.occ_percent::total 0.070708 # Average percentage of cache occupancy 449system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits 450system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits 451system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits 452system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits 453system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits 454system.cpu.icache.overall_hits::total 1475 # number of overall hits 455system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses 456system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses 457system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses 458system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses 459system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses 460system.cpu.icache.overall_misses::total 399 # number of overall misses 461system.cpu.icache.ReadReq_miss_latency::cpu.inst 20615000 # number of ReadReq miss cycles 462system.cpu.icache.ReadReq_miss_latency::total 20615000 # number of ReadReq miss cycles 463system.cpu.icache.demand_miss_latency::cpu.inst 20615000 # number of demand (read+write) miss cycles 464system.cpu.icache.demand_miss_latency::total 20615000 # number of demand (read+write) miss cycles 465system.cpu.icache.overall_miss_latency::cpu.inst 20615000 # number of overall miss cycles 466system.cpu.icache.overall_miss_latency::total 20615000 # number of overall miss cycles 467system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses) 468system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses) 469system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses 470system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses 471system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses 472system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses 473system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses 474system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses 475system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses 476system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses 477system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses 478system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses 479system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51666.666667 # average ReadReq miss latency 480system.cpu.icache.ReadReq_avg_miss_latency::total 51666.666667 # average ReadReq miss latency 481system.cpu.icache.demand_avg_miss_latency::cpu.inst 51666.666667 # average overall miss latency 482system.cpu.icache.demand_avg_miss_latency::total 51666.666667 # average overall miss latency 483system.cpu.icache.overall_avg_miss_latency::cpu.inst 51666.666667 # average overall miss latency 484system.cpu.icache.overall_avg_miss_latency::total 51666.666667 # average overall miss latency 485system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked 486system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 487system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked 488system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 489system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked 490system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 491system.cpu.icache.fast_writes 0 # number of fast writes performed 492system.cpu.icache.cache_copies 0 # number of cache copies performed 493system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits 494system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits 495system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits 496system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits 497system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits 498system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits 499system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 500system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 501system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 502system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 503system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 504system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 505system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157500 # number of ReadReq MSHR miss cycles 506system.cpu.icache.ReadReq_mshr_miss_latency::total 16157500 # number of ReadReq MSHR miss cycles 507system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157500 # number of demand (read+write) MSHR miss cycles 508system.cpu.icache.demand_mshr_miss_latency::total 16157500 # number of demand (read+write) MSHR miss cycles 509system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157500 # number of overall MSHR miss cycles 510system.cpu.icache.overall_mshr_miss_latency::total 16157500 # number of overall MSHR miss cycles 511system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses 512system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses 513system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses 514system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses 515system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses 516system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses 517system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53149.671053 # average ReadReq mshr miss latency 518system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53149.671053 # average ReadReq mshr miss latency 519system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency 520system.cpu.icache.demand_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency 521system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency 522system.cpu.icache.overall_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency 523system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 524system.cpu.l2cache.replacements 0 # number of replacements 525system.cpu.l2cache.tagsinuse 177.966730 # Cycle average of tags in use 526system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 527system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 528system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 529system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 530system.cpu.l2cache.occ_blocks::cpu.inst 144.947246 # Average occupied blocks per requestor 531system.cpu.l2cache.occ_blocks::cpu.data 33.019484 # Average occupied blocks per requestor 532system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy 533system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy 534system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy 535system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 536system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 537system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 538system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 539system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 540system.cpu.l2cache.overall_hits::total 1 # number of overall hits 541system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 542system.cpu.l2cache.ReadReq_misses::cpu.data 72 # number of ReadReq misses 543system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses 544system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 545system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 546system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 547system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 548system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses 549system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses 550system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 551system.cpu.l2cache.overall_misses::total 451 # number of overall misses 552system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842500 # number of ReadReq miss cycles 553system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles 554system.cpu.l2cache.ReadReq_miss_latency::total 19735000 # number of ReadReq miss cycles 555system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles 556system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles 557system.cpu.l2cache.demand_miss_latency::cpu.inst 15842500 # number of demand (read+write) miss cycles 558system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles 559system.cpu.l2cache.demand_miss_latency::total 23725500 # number of demand (read+write) miss cycles 560system.cpu.l2cache.overall_miss_latency::cpu.inst 15842500 # number of overall miss cycles 561system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles 562system.cpu.l2cache.overall_miss_latency::total 23725500 # number of overall miss cycles 563system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 564system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses) 565system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) 566system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 567system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 568system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 569system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 570system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses 571system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 572system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses 573system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses 574system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses 575system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 576system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses 577system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 578system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 579system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses 580system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 581system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses 582system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses 583system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 584system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses 585system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52285.478548 # average ReadReq miss latency 586system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency 587system.cpu.l2cache.ReadReq_avg_miss_latency::total 52626.666667 # average ReadReq miss latency 588system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency 589system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency 590system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency 591system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency 592system.cpu.l2cache.demand_avg_miss_latency::total 52606.430155 # average overall miss latency 593system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency 594system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::total 52606.430155 # average overall miss latency 596system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.l2cache.fast_writes 0 # number of fast writes performed 603system.cpu.l2cache.cache_copies 0 # number of cache copies performed 604system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 605system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses 606system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 607system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 608system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 609system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 610system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 611system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses 612system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 613system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 614system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses 615system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles 616system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles 617system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles 618system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3057807 # number of ReadExReq MSHR miss cycles 619system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3057807 # number of ReadExReq MSHR miss cycles 620system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles 621system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6087848 # number of demand (read+write) MSHR miss cycles 622system.cpu.l2cache.demand_mshr_miss_latency::total 18179829 # number of demand (read+write) MSHR miss cycles 623system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles 624system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6087848 # number of overall MSHR miss cycles 625system.cpu.l2cache.overall_mshr_miss_latency::total 18179829 # number of overall MSHR miss cycles 626system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses 627system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 628system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses 629system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 630system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 631system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses 632system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 633system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses 634system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses 635system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 636system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses 637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency 638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency 639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency 640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40234.302632 # average ReadExReq mshr miss latency 641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40234.302632 # average ReadExReq mshr miss latency 642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency 643system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency 644system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency 645system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649system.cpu.dcache.replacements 0 # number of replacements 650system.cpu.dcache.tagsinuse 83.491215 # Cycle average of tags in use 651system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks. 652system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 653system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks. 654system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 655system.cpu.dcache.occ_blocks::cpu.data 83.491215 # Average occupied blocks per requestor 656system.cpu.dcache.occ_percent::cpu.data 0.020384 # Average percentage of cache occupancy 657system.cpu.dcache.occ_percent::total 0.020384 # Average percentage of cache occupancy 658system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits 659system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits 660system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits 661system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits 662system.cpu.dcache.demand_hits::cpu.data 2285 # number of demand (read+write) hits 663system.cpu.dcache.demand_hits::total 2285 # number of demand (read+write) hits 664system.cpu.dcache.overall_hits::cpu.data 2285 # number of overall hits 665system.cpu.dcache.overall_hits::total 2285 # number of overall hits 666system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses 667system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses 668system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 669system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 670system.cpu.dcache.demand_misses::cpu.data 203 # number of demand (read+write) misses 671system.cpu.dcache.demand_misses::total 203 # number of demand (read+write) misses 672system.cpu.dcache.overall_misses::cpu.data 203 # number of overall misses 673system.cpu.dcache.overall_misses::total 203 # number of overall misses 674system.cpu.dcache.ReadReq_miss_latency::cpu.data 6648000 # number of ReadReq miss cycles 675system.cpu.dcache.ReadReq_miss_latency::total 6648000 # number of ReadReq miss cycles 676system.cpu.dcache.WriteReq_miss_latency::cpu.data 4218500 # number of WriteReq miss cycles 677system.cpu.dcache.WriteReq_miss_latency::total 4218500 # number of WriteReq miss cycles 678system.cpu.dcache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles 679system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles 680system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles 681system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles 682system.cpu.dcache.ReadReq_accesses::cpu.data 1553 # number of ReadReq accesses(hits+misses) 683system.cpu.dcache.ReadReq_accesses::total 1553 # number of ReadReq accesses(hits+misses) 684system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 685system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 686system.cpu.dcache.demand_accesses::cpu.data 2488 # number of demand (read+write) accesses 687system.cpu.dcache.demand_accesses::total 2488 # number of demand (read+write) accesses 688system.cpu.dcache.overall_accesses::cpu.data 2488 # number of overall (read+write) accesses 689system.cpu.dcache.overall_accesses::total 2488 # number of overall (read+write) accesses 690system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081777 # miss rate for ReadReq accesses 691system.cpu.dcache.ReadReq_miss_rate::total 0.081777 # miss rate for ReadReq accesses 692system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses 693system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses 694system.cpu.dcache.demand_miss_rate::cpu.data 0.081592 # miss rate for demand accesses 695system.cpu.dcache.demand_miss_rate::total 0.081592 # miss rate for demand accesses 696system.cpu.dcache.overall_miss_rate::cpu.data 0.081592 # miss rate for overall accesses 697system.cpu.dcache.overall_miss_rate::total 0.081592 # miss rate for overall accesses 698system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency 699system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency 700system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency 701system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency 702system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency 703system.cpu.dcache.demand_avg_miss_latency::total 53529.556650 # average overall miss latency 704system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency 705system.cpu.dcache.overall_avg_miss_latency::total 53529.556650 # average overall miss latency 706system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked 707system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 709system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.600000 # average number of cycles each access was blocked 711system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.dcache.fast_writes 0 # number of fast writes performed 713system.cpu.dcache.cache_copies 0 # number of cache copies performed 714system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 715system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 716system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits 717system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 718system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits 719system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits 720system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses 721system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses 722system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 723system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 724system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 725system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 726system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 727system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 728system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles 729system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles 730system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles 731system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles 732system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles 733system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles 734system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles 735system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles 736system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046362 # mshr miss rate for ReadReq accesses 737system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046362 # mshr miss rate for ReadReq accesses 738system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses 739system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.059486 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059486 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.059486 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency 748system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency 749system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency 750system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency 751system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency 752system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 753 754---------- End Simulation Statistics ---------- 755