stats.txt revision 9013:afa278317136
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12198000 # Number of ticks simulated 5final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 10821 # Simulator instruction rate (inst/s) 8host_op_rate 19598 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24369729 # Simulator tick rate (ticks/s) 10host_mem_usage 271424 # Number of bytes of host memory used 11host_seconds 0.50 # Real time elapsed on the host 12sim_insts 5416 # Number of instructions simulated 13sim_ops 9809 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28864 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 451 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.workload.num_syscalls 11 # Number of system calls 24system.cpu.numCycles 24397 # number of cpu cycles simulated 25system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 26system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 27system.cpu.BPredUnit.lookups 3206 # Number of BP lookups 28system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted 29system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect 30system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups 31system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits 32system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 34system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 35system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss 36system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed 37system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered 38system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken 39system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked 40system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing 41system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked 42system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 43system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps 44system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched 45system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed 46system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total) 47system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle 64system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle 65system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle 66system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked 67system.cpu.decode.RunCycles 3749 # Number of cycles decode is running 68system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking 69system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing 70system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode 71system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing 72system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle 73system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking 74system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst 75system.cpu.rename.RunCycles 3522 # Number of cycles rename is running 76system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking 77system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename 78system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 79system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full 80system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full 81system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers 82system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed 83system.cpu.rename.RenameLookups 70482 # Number of register rename lookups that rename has made 84system.cpu.rename.int_rename_lookups 70466 # Number of integer rename lookups 85system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 86system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed 87system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing 88system.cpu.rename.serializingInsts 33 # count of serializing insts renamed 89system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed 90system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer 91system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit. 92system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit. 93system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. 94system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 95system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec) 96system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ 97system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued 98system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued 99system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling 100system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph 101system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed 102system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle 103system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle 119system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 120system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available 121system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available 122system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available 123system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available 126system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available 127system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available 128system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available 129system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available 149system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available 150system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available 151system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 152system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 153system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued 154system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued 155system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued 156system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued 157system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued 160system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued 161system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued 162system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued 163system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued 183system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued 184system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued 185system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 186system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 187system.cpu.iq.FU_type_0::total 17854 # Type of FU issued 188system.cpu.iq.rate 0.731811 # Inst issue rate 189system.cpu.iq.fu_busy_cnt 191 # FU busy when requested 190system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) 191system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads 192system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes 193system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses 194system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 195system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes 196system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses 197system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses 198system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 199system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores 200system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 201system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed 202system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed 203system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations 204system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed 205system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 206system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 207system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 208system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 209system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 210system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing 211system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking 212system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking 213system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ 214system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch 215system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions 216system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions 217system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 218system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall 219system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 220system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations 221system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly 222system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly 223system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute 224system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions 225system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed 226system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute 227system.cpu.iew.exec_swp 0 # number of swp insts executed 228system.cpu.iew.exec_nop 0 # number of nop insts executed 229system.cpu.iew.exec_refs 3203 # number of memory reference insts executed 230system.cpu.iew.exec_branches 1645 # Number of branches executed 231system.cpu.iew.exec_stores 1359 # Number of stores executed 232system.cpu.iew.exec_rate 0.689593 # Inst execution rate 233system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit 234system.cpu.iew.wb_count 16406 # cumulative count of insts written-back 235system.cpu.iew.wb_producers 10679 # num instructions producing a value 236system.cpu.iew.wb_consumers 24448 # num instructions consuming a value 237system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 238system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle 239system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back 240system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 241system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions 242system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions 243system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit 244system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards 245system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted 246system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle 247system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle 263system.cpu.commit.committedInsts 5416 # Number of instructions committed 264system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed 265system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 266system.cpu.commit.refs 1990 # Number of memory references committed 267system.cpu.commit.loads 1056 # Number of loads committed 268system.cpu.commit.membars 0 # Number of memory barriers committed 269system.cpu.commit.branches 1214 # Number of branches committed 270system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 271system.cpu.commit.int_insts 9714 # Number of committed integer instructions. 272system.cpu.commit.function_calls 0 # Number of function calls committed. 273system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached 274system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 275system.cpu.rob.rob_reads 36362 # The number of ROB reads 276system.cpu.rob.rob_writes 45397 # The number of ROB writes 277system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself 278system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling 279system.cpu.committedInsts 5416 # Number of Instructions Simulated 280system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated 281system.cpu.committedInsts_total 5416 # Number of Instructions Simulated 282system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction 283system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads 284system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle 285system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads 286system.cpu.int_regfile_reads 35454 # number of integer regfile reads 287system.cpu.int_regfile_writes 22063 # number of integer regfile writes 288system.cpu.fp_regfile_reads 4 # number of floating regfile reads 289system.cpu.misc_regfile_reads 7402 # number of misc regfile reads 290system.cpu.icache.replacements 0 # number of replacements 291system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use 292system.cpu.icache.total_refs 1561 # Total number of references to valid blocks. 293system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. 294system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks. 295system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 296system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor 297system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy 298system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy 299system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits 300system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits 301system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits 302system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits 303system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits 304system.cpu.icache.overall_hits::total 1561 # number of overall hits 305system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses 306system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses 307system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses 308system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses 309system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses 310system.cpu.icache.overall_misses::total 390 # number of overall misses 311system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles 312system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles 313system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles 314system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles 315system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles 316system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles 317system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) 318system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) 319system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses 320system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses 321system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses 322system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses 323system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses 324system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses 325system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses 326system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency 327system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency 328system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency 329system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 330system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 331system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 333system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 334system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 335system.cpu.icache.fast_writes 0 # number of fast writes performed 336system.cpu.icache.cache_copies 0 # number of cache copies performed 337system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits 338system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits 339system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits 340system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits 341system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits 342system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits 343system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 344system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 345system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 346system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 347system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 348system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 349system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles 350system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles 351system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles 352system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles 353system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles 354system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles 355system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses 356system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses 357system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses 358system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency 359system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency 360system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency 361system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 362system.cpu.dcache.replacements 0 # number of replacements 363system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use 364system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. 365system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. 366system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. 367system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 368system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor 369system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy 370system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy 371system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits 372system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits 373system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits 374system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits 375system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits 376system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits 377system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits 378system.cpu.dcache.overall_hits::total 2365 # number of overall hits 379system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 380system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 381system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses 382system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses 383system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses 384system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses 385system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses 386system.cpu.dcache.overall_misses::total 191 # number of overall misses 387system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles 388system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles 389system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles 391system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles 392system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles 393system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles 394system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles 395system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses 400system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses 401system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses 402system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses 403system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses 404system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses 405system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses 406system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency 408system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency 409system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency 411system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.dcache.fast_writes 0 # number of fast writes performed 418system.cpu.dcache.cache_copies 0 # number of cache copies performed 419system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits 420system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 421system.cpu.dcache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits 422system.cpu.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits 423system.cpu.dcache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits 424system.cpu.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits 425system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses 426system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses 427system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses 428system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses 429system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 430system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 431system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 432system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 433system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2574000 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles 437system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles 441system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses 442system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses 443system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses 444system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses 445system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency 446system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency 447system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency 448system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency 449system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.cpu.l2cache.replacements 0 # number of replacements 451system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use 452system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 453system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. 454system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. 455system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor 457system.cpu.l2cache.occ_blocks::cpu.data 34.388427 # Average occupied blocks per requestor 458system.cpu.l2cache.occ_percent::cpu.inst 0.004432 # Average percentage of cache occupancy 459system.cpu.l2cache.occ_percent::cpu.data 0.001049 # Average percentage of cache occupancy 460system.cpu.l2cache.occ_percent::total 0.005482 # Average percentage of cache occupancy 461system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 462system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 463system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 464system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 465system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 466system.cpu.l2cache.overall_hits::total 2 # number of overall hits 467system.cpu.l2cache.ReadReq_misses::cpu.inst 302 # number of ReadReq misses 468system.cpu.l2cache.ReadReq_misses::cpu.data 73 # number of ReadReq misses 469system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses 470system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses 471system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses 472system.cpu.l2cache.demand_misses::cpu.inst 302 # number of demand (read+write) misses 473system.cpu.l2cache.demand_misses::cpu.data 149 # number of demand (read+write) misses 474system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses 475system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses 476system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses 477system.cpu.l2cache.overall_misses::total 451 # number of overall misses 478system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10368000 # number of ReadReq miss cycles 479system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles 480system.cpu.l2cache.ReadReq_miss_latency::total 12854500 # number of ReadReq miss cycles 481system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles 482system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles 483system.cpu.l2cache.demand_miss_latency::cpu.inst 10368000 # number of demand (read+write) miss cycles 484system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles 485system.cpu.l2cache.demand_miss_latency::total 15457500 # number of demand (read+write) miss cycles 486system.cpu.l2cache.overall_miss_latency::cpu.inst 10368000 # number of overall miss cycles 487system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles 488system.cpu.l2cache.overall_miss_latency::total 15457500 # number of overall miss cycles 489system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 490system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) 491system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) 492system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) 493system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) 494system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 495system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 496system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 497system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 498system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 499system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 500system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses 501system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 502system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses 504system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 505system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses 506system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 507system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency 508system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency 509system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency 510system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 511system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 512system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency 513system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency 514system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 518system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 519system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 520system.cpu.l2cache.fast_writes 0 # number of fast writes performed 521system.cpu.l2cache.cache_copies 0 # number of cache copies performed 522system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses 523system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses 524system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses 525system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses 526system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses 527system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses 528system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 529system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses 530system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses 531system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 532system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses 533system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9394000 # number of ReadReq MSHR miss cycles 534system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2263500 # number of ReadReq MSHR miss cycles 535system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11657500 # number of ReadReq MSHR miss cycles 536system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles 537system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles 538system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles 539system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles 540system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles 541system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles 542system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles 543system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles 544system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses 545system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 546system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 547system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses 548system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 549system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses 550system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 551system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency 552system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency 553system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency 554system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 555system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency 556system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency 557system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency 558system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 559 560---------- End Simulation Statistics ---------- 561