stats.txt revision 11456:c0fb4435b80f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21273500 # Number of ticks simulated 5final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 70008 # Simulator instruction rate (inst/s) 8host_op_rate 126817 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 276755373 # Simulator tick rate (ticks/s) 10host_mem_usage 271684 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5380 # Number of instructions simulated 13sim_ops 9747 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26624 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 416 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 416 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 31 # Per bank write bursts 45system.physmem.perBankRdBursts::1 1 # Per bank write bursts 46system.physmem.perBankRdBursts::2 5 # Per bank write bursts 47system.physmem.perBankRdBursts::3 8 # Per bank write bursts 48system.physmem.perBankRdBursts::4 51 # Per bank write bursts 49system.physmem.perBankRdBursts::5 44 # Per bank write bursts 50system.physmem.perBankRdBursts::6 21 # Per bank write bursts 51system.physmem.perBankRdBursts::7 37 # Per bank write bursts 52system.physmem.perBankRdBursts::8 23 # Per bank write bursts 53system.physmem.perBankRdBursts::9 71 # Per bank write bursts 54system.physmem.perBankRdBursts::10 64 # Per bank write bursts 55system.physmem.perBankRdBursts::11 16 # Per bank write bursts 56system.physmem.perBankRdBursts::12 2 # Per bank write bursts 57system.physmem.perBankRdBursts::13 19 # Per bank write bursts 58system.physmem.perBankRdBursts::14 6 # Per bank write bursts 59system.physmem.perBankRdBursts::15 17 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 21151500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 416 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation 203system.physmem.totQLat 4187000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.78 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 309 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 50844.95 # Average gap between requests 224system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ) 233system.physmem_0.averagePower 823.803884 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) 247system.physmem_1.averagePower 883.874941 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 3510 # Number of BP lookups 254system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 0 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 268system.cpu.workload.num_syscalls 11 # Number of system calls 269system.cpu.numCycles 42548 # number of cpu cycles simulated 270system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 271system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 272system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss 273system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed 274system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered 275system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken 276system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked 277system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing 278system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 279system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps 280system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions 281system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR 282system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched 283system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed 284system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle 302system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle 303system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle 304system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked 305system.cpu.decode.RunCycles 3404 # Number of cycles decode is running 306system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking 307system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing 308system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode 309system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing 310system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle 311system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking 312system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst 313system.cpu.rename.RunCycles 3557 # Number of cycles rename is running 314system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking 315system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename 316system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full 317system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full 318system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full 319system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed 320system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made 321system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups 322system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 323system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed 324system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing 325system.cpu.rename.serializingInsts 25 # count of serializing insts renamed 326system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed 327system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer 328system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. 329system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit. 330system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. 331system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 332system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec) 333system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ 334system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued 335system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued 336system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling 337system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph 338system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 339system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle 356system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 357system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available 358system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available 359system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available 361system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available 386system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available 387system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 389system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 390system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued 391system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued 392system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued 393system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued 395system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued 420system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued 421system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued 422system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 423system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 424system.cpu.iq.FU_type_0::total 18142 # Type of FU issued 425system.cpu.iq.rate 0.426389 # Inst issue rate 426system.cpu.iq.fu_busy_cnt 277 # FU busy when requested 427system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst) 428system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads 429system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes 430system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses 431system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads 432system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes 433system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses 434system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses 435system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses 436system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores 437system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 438system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed 439system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed 440system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 441system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed 442system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 443system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 444system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 445system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked 446system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 447system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing 448system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking 449system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking 450system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ 451system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch 452system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions 453system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions 454system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions 455system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 456system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall 457system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations 458system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly 459system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly 460system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute 461system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions 462system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed 463system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute 464system.cpu.iew.exec_swp 0 # number of swp insts executed 465system.cpu.iew.exec_nop 0 # number of nop insts executed 466system.cpu.iew.exec_refs 3326 # number of memory reference insts executed 467system.cpu.iew.exec_branches 1722 # Number of branches executed 468system.cpu.iew.exec_stores 1245 # Number of stores executed 469system.cpu.iew.exec_rate 0.400959 # Inst execution rate 470system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit 471system.cpu.iew.wb_count 16440 # cumulative count of insts written-back 472system.cpu.iew.wb_producers 11045 # num instructions producing a value 473system.cpu.iew.wb_consumers 17238 # num instructions consuming a value 474system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle 475system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back 476system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit 477system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards 478system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted 479system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle 496system.cpu.commit.committedInsts 5380 # Number of instructions committed 497system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed 498system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 499system.cpu.commit.refs 1988 # Number of memory references committed 500system.cpu.commit.loads 1053 # Number of loads committed 501system.cpu.commit.membars 0 # Number of memory barriers committed 502system.cpu.commit.branches 1208 # Number of branches committed 503system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 504system.cpu.commit.int_insts 9653 # Number of committed integer instructions. 505system.cpu.commit.function_calls 106 # Number of function calls committed. 506system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction 507system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction 508system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction 509system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction 510system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction 511system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction 512system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction 513system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction 514system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction 515system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction 536system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction 537system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction 538system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 539system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 540system.cpu.commit.op_class_0::total 9747 # Class of committed instruction 541system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached 542system.cpu.rob.rob_reads 42878 # The number of ROB reads 543system.cpu.rob.rob_writes 45859 # The number of ROB writes 544system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself 545system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling 546system.cpu.committedInsts 5380 # Number of Instructions Simulated 547system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated 548system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction 549system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads 550system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle 551system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads 552system.cpu.int_regfile_reads 21687 # number of integer regfile reads 553system.cpu.int_regfile_writes 13280 # number of integer regfile writes 554system.cpu.fp_regfile_reads 4 # number of floating regfile reads 555system.cpu.cc_regfile_reads 8296 # number of cc regfile reads 556system.cpu.cc_regfile_writes 5092 # number of cc regfile writes 557system.cpu.misc_regfile_reads 7660 # number of misc regfile reads 558system.cpu.misc_regfile_writes 1 # number of misc regfile writes 559system.cpu.dcache.tags.replacements 0 # number of replacements 560system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use 561system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. 562system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. 563system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. 564system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 565system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor 566system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy 567system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy 568system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id 569system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 570system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id 571system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id 572system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses 573system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses 574system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits 575system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits 576system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits 577system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits 578system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits 579system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits 580system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits 581system.cpu.dcache.overall_hits::total 2583 # number of overall hits 582system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 583system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 584system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses 585system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses 586system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses 587system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses 588system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses 589system.cpu.dcache.overall_misses::total 190 # number of overall misses 590system.cpu.dcache.ReadReq_miss_latency::cpu.data 9038500 # number of ReadReq miss cycles 591system.cpu.dcache.ReadReq_miss_latency::total 9038500 # number of ReadReq miss cycles 592system.cpu.dcache.WriteReq_miss_latency::cpu.data 6225500 # number of WriteReq miss cycles 593system.cpu.dcache.WriteReq_miss_latency::total 6225500 # number of WriteReq miss cycles 594system.cpu.dcache.demand_miss_latency::cpu.data 15264000 # number of demand (read+write) miss cycles 595system.cpu.dcache.demand_miss_latency::total 15264000 # number of demand (read+write) miss cycles 596system.cpu.dcache.overall_miss_latency::cpu.data 15264000 # number of overall miss cycles 597system.cpu.dcache.overall_miss_latency::total 15264000 # number of overall miss cycles 598system.cpu.dcache.ReadReq_accesses::cpu.data 1838 # number of ReadReq accesses(hits+misses) 599system.cpu.dcache.ReadReq_accesses::total 1838 # number of ReadReq accesses(hits+misses) 600system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) 601system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) 602system.cpu.dcache.demand_accesses::cpu.data 2773 # number of demand (read+write) accesses 603system.cpu.dcache.demand_accesses::total 2773 # number of demand (read+write) accesses 604system.cpu.dcache.overall_accesses::cpu.data 2773 # number of overall (read+write) accesses 605system.cpu.dcache.overall_accesses::total 2773 # number of overall (read+write) accesses 606system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062568 # miss rate for ReadReq accesses 607system.cpu.dcache.ReadReq_miss_rate::total 0.062568 # miss rate for ReadReq accesses 608system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses 609system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses 610system.cpu.dcache.demand_miss_rate::cpu.data 0.068518 # miss rate for demand accesses 611system.cpu.dcache.demand_miss_rate::total 0.068518 # miss rate for demand accesses 612system.cpu.dcache.overall_miss_rate::cpu.data 0.068518 # miss rate for overall accesses 613system.cpu.dcache.overall_miss_rate::total 0.068518 # miss rate for overall accesses 614system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78595.652174 # average ReadReq miss latency 615system.cpu.dcache.ReadReq_avg_miss_latency::total 78595.652174 # average ReadReq miss latency 616system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83006.666667 # average WriteReq miss latency 617system.cpu.dcache.WriteReq_avg_miss_latency::total 83006.666667 # average WriteReq miss latency 618system.cpu.dcache.demand_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 619system.cpu.dcache.demand_avg_miss_latency::total 80336.842105 # average overall miss latency 620system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency 621system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency 622system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked 623system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 625system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked 627system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 628system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits 629system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5459500 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 5459500 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6150500 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6150500 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11610000 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 11610000 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11610000 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 11610000 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034820 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034820 # mshr miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.050126 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.050126 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency 666system.cpu.icache.tags.replacements 0 # number of replacements 667system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use 668system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. 669system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. 670system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. 671system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 672system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor 673system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 678system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id 679system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses 680system.cpu.icache.tags.data_accesses 4350 # Number of data accesses 681system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits 682system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits 683system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits 684system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits 685system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits 686system.cpu.icache.overall_hits::total 1651 # number of overall hits 687system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 688system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses 689system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses 690system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses 691system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses 692system.cpu.icache.overall_misses::total 385 # number of overall misses 693system.cpu.icache.ReadReq_miss_latency::cpu.inst 28516500 # number of ReadReq miss cycles 694system.cpu.icache.ReadReq_miss_latency::total 28516500 # number of ReadReq miss cycles 695system.cpu.icache.demand_miss_latency::cpu.inst 28516500 # number of demand (read+write) miss cycles 696system.cpu.icache.demand_miss_latency::total 28516500 # number of demand (read+write) miss cycles 697system.cpu.icache.overall_miss_latency::cpu.inst 28516500 # number of overall miss cycles 698system.cpu.icache.overall_miss_latency::total 28516500 # number of overall miss cycles 699system.cpu.icache.ReadReq_accesses::cpu.inst 2036 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.demand_accesses::cpu.inst 2036 # number of demand (read+write) accesses 702system.cpu.icache.demand_accesses::total 2036 # number of demand (read+write) accesses 703system.cpu.icache.overall_accesses::cpu.inst 2036 # number of overall (read+write) accesses 704system.cpu.icache.overall_accesses::total 2036 # number of overall (read+write) accesses 705system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189096 # miss rate for ReadReq accesses 706system.cpu.icache.ReadReq_miss_rate::total 0.189096 # miss rate for ReadReq accesses 707system.cpu.icache.demand_miss_rate::cpu.inst 0.189096 # miss rate for demand accesses 708system.cpu.icache.demand_miss_rate::total 0.189096 # miss rate for demand accesses 709system.cpu.icache.overall_miss_rate::cpu.inst 0.189096 # miss rate for overall accesses 710system.cpu.icache.overall_miss_rate::total 0.189096 # miss rate for overall accesses 711system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74068.831169 # average ReadReq miss latency 712system.cpu.icache.ReadReq_avg_miss_latency::total 74068.831169 # average ReadReq miss latency 713system.cpu.icache.demand_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 714system.cpu.icache.demand_avg_miss_latency::total 74068.831169 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency 717system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked 718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked 722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 724system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 725system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 726system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 727system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 728system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits 729system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 730system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses 731system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 732system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses 733system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 734system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses 735system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21868500 # number of ReadReq MSHR miss cycles 736system.cpu.icache.ReadReq_mshr_miss_latency::total 21868500 # number of ReadReq MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21868500 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::total 21868500 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21868500 # number of overall MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::total 21868500 # number of overall MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136542 # mshr miss rate for ReadReq accesses 743system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for demand accesses 744system.cpu.icache.demand_mshr_miss_rate::total 0.136542 # mshr miss rate for demand accesses 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency 753system.cpu.l2cache.tags.replacements 0 # number of replacements 754system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use 755system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 756system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. 757system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. 758system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 765system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 766system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 767system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id 768system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses 769system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses 770system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 771system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 772system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 773system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 774system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 775system.cpu.l2cache.overall_hits::total 1 # number of overall hits 776system.cpu.l2cache.ReadExReq_misses::cpu.data 75 # number of ReadExReq misses 777system.cpu.l2cache.ReadExReq_misses::total 75 # number of ReadExReq misses 778system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses 779system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses 780system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses 781system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses 782system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses 783system.cpu.l2cache.demand_misses::cpu.data 139 # number of demand (read+write) misses 784system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses 785system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses 786system.cpu.l2cache.overall_misses::cpu.data 139 # number of overall misses 787system.cpu.l2cache.overall_misses::total 416 # number of overall misses 788system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037500 # number of ReadExReq miss cycles 789system.cpu.l2cache.ReadExReq_miss_latency::total 6037500 # number of ReadExReq miss cycles 790system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21439500 # number of ReadCleanReq miss cycles 791system.cpu.l2cache.ReadCleanReq_miss_latency::total 21439500 # number of ReadCleanReq miss cycles 792system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5362500 # number of ReadSharedReq miss cycles 793system.cpu.l2cache.ReadSharedReq_miss_latency::total 5362500 # number of ReadSharedReq miss cycles 794system.cpu.l2cache.demand_miss_latency::cpu.inst 21439500 # number of demand (read+write) miss cycles 795system.cpu.l2cache.demand_miss_latency::cpu.data 11400000 # number of demand (read+write) miss cycles 796system.cpu.l2cache.demand_miss_latency::total 32839500 # number of demand (read+write) miss cycles 797system.cpu.l2cache.overall_miss_latency::cpu.inst 21439500 # number of overall miss cycles 798system.cpu.l2cache.overall_miss_latency::cpu.data 11400000 # number of overall miss cycles 799system.cpu.l2cache.overall_miss_latency::total 32839500 # number of overall miss cycles 800system.cpu.l2cache.ReadExReq_accesses::cpu.data 75 # number of ReadExReq accesses(hits+misses) 801system.cpu.l2cache.ReadExReq_accesses::total 75 # number of ReadExReq accesses(hits+misses) 802system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) 803system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) 804system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) 805system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) 806system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses 807system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses 808system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses 809system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses 810system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses 811system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses 812system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 813system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses 815system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses 816system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 817system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 818system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::total 0.997602 # miss rate for demand accesses 821system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::total 0.997602 # miss rate for overall accesses 824system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80500 # average ReadExReq miss latency 825system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80500 # average ReadExReq miss latency 826system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77398.916968 # average ReadCleanReq miss latency 827system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77398.916968 # average ReadCleanReq miss latency 828system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83789.062500 # average ReadSharedReq miss latency 829system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83789.062500 # average ReadSharedReq miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 832system.cpu.l2cache.demand_avg_miss_latency::total 78941.105769 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency 835system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency 836system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 839system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 841system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 842system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses 843system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses 844system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses 845system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses 846system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 847system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses 853system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses 854system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5287500 # number of ReadExReq MSHR miss cycles 855system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5287500 # number of ReadExReq MSHR miss cycles 856system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18669500 # number of ReadCleanReq MSHR miss cycles 857system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles 858system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles 859system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles 865system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles 866system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses 870system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 871system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 872system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses 873system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 874system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses 875system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses 876system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 877system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses 878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency 881system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency 882system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency 883system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency 890system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. 891system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 892system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 893system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 894system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 895system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 896system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution 900system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 901system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) 906system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) 907system.cpu.toL2Bus.snoops 0 # Total snoops (count) 908system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 917system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram 919system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) 920system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 923system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) 924system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 925system.membus.trans_dist::ReadResp 341 # Transaction distribution 926system.membus.trans_dist::ReadExReq 75 # Transaction distribution 927system.membus.trans_dist::ReadExResp 75 # Transaction distribution 928system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution 929system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) 930system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) 931system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) 932system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) 933system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) 934system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) 935system.membus.snoops 0 # Total snoops (count) 936system.membus.snoop_fanout::samples 416 # Request fanout histogram 937system.membus.snoop_fanout::mean 0 # Request fanout histogram 938system.membus.snoop_fanout::stdev 0 # Request fanout histogram 939system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 940system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram 941system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 942system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 943system.membus.snoop_fanout::min_value 0 # Request fanout histogram 944system.membus.snoop_fanout::max_value 0 # Request fanout histogram 945system.membus.snoop_fanout::total 416 # Request fanout histogram 946system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) 947system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 948system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) 949system.membus.respLayer1.utilization 10.4 # Layer utilization (%) 950 951---------- End Simulation Statistics ---------- 952