config.ini revision 11312:3d7a85d71bd1
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58activity=0 59backComSize=5 60branchPred=system.cpu.branchPred 61cachePorts=200 62checker=Null 63clk_domain=system.cpu_clk_domain 64commitToDecodeDelay=1 65commitToFetchDelay=1 66commitToIEWDelay=1 67commitToRenameDelay=1 68commitWidth=8 69cpu_id=0 70decodeToFetchDelay=1 71decodeToRenameDelay=1 72decodeWidth=8 73dispatchWidth=8 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=true 102numIQEntries=64 103numPhysCCRegs=1280 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.apic_clk_domain] 139type=DerivedClockDomain 140clk_divider=16 141clk_domain=system.cpu_clk_domain 142eventq_index=0 143 144[system.cpu.branchPred] 145type=TournamentBP 146BTBEntries=4096 147BTBTagSize=16 148RASSize=16 149choiceCtrBits=2 150choicePredictorSize=8192 151eventq_index=0 152globalCtrBits=2 153globalPredictorSize=8192 154instShiftAmt=2 155localCtrBits=2 156localHistoryTableSize=2048 157localPredictorSize=2048 158numThreads=1 159 160[system.cpu.dcache] 161type=Cache 162children=tags 163addr_ranges=0:18446744073709551615 164assoc=2 165clk_domain=system.cpu_clk_domain 166clusivity=mostly_incl 167demand_mshr_reserve=1 168eventq_index=0 169forward_snoops=true 170hit_latency=2 171is_read_only=false 172max_miss_count=0 173mshrs=4 174prefetch_on_access=false 175prefetcher=Null 176response_latency=2 177sequential_access=false 178size=262144 179system=system 180tags=system.cpu.dcache.tags 181tgts_per_mshr=20 182write_buffers=8 183writeback_clean=false 184cpu_side=system.cpu.dcache_port 185mem_side=system.cpu.toL2Bus.slave[1] 186 187[system.cpu.dcache.tags] 188type=LRU 189assoc=2 190block_size=64 191clk_domain=system.cpu_clk_domain 192eventq_index=0 193hit_latency=2 194sequential_access=false 195size=262144 196 197[system.cpu.dtb] 198type=X86TLB 199children=walker 200eventq_index=0 201size=64 202walker=system.cpu.dtb.walker 203 204[system.cpu.dtb.walker] 205type=X86PagetableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208num_squash_per_cycle=4 209system=system 210port=system.cpu.toL2Bus.slave[3] 211 212[system.cpu.fuPool] 213type=FUPool 214children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 215FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 216eventq_index=0 217 218[system.cpu.fuPool.FUList0] 219type=FUDesc 220children=opList 221count=6 222eventq_index=0 223opList=system.cpu.fuPool.FUList0.opList 224 225[system.cpu.fuPool.FUList0.opList] 226type=OpDesc 227eventq_index=0 228opClass=IntAlu 229opLat=1 230pipelined=true 231 232[system.cpu.fuPool.FUList1] 233type=FUDesc 234children=opList0 opList1 235count=2 236eventq_index=0 237opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 238 239[system.cpu.fuPool.FUList1.opList0] 240type=OpDesc 241eventq_index=0 242opClass=IntMult 243opLat=3 244pipelined=true 245 246[system.cpu.fuPool.FUList1.opList1] 247type=OpDesc 248eventq_index=0 249opClass=IntDiv 250opLat=1 251pipelined=false 252 253[system.cpu.fuPool.FUList2] 254type=FUDesc 255children=opList0 opList1 opList2 256count=4 257eventq_index=0 258opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 259 260[system.cpu.fuPool.FUList2.opList0] 261type=OpDesc 262eventq_index=0 263opClass=FloatAdd 264opLat=2 265pipelined=true 266 267[system.cpu.fuPool.FUList2.opList1] 268type=OpDesc 269eventq_index=0 270opClass=FloatCmp 271opLat=2 272pipelined=true 273 274[system.cpu.fuPool.FUList2.opList2] 275type=OpDesc 276eventq_index=0 277opClass=FloatCvt 278opLat=2 279pipelined=true 280 281[system.cpu.fuPool.FUList3] 282type=FUDesc 283children=opList0 opList1 opList2 284count=2 285eventq_index=0 286opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 287 288[system.cpu.fuPool.FUList3.opList0] 289type=OpDesc 290eventq_index=0 291opClass=FloatMult 292opLat=4 293pipelined=true 294 295[system.cpu.fuPool.FUList3.opList1] 296type=OpDesc 297eventq_index=0 298opClass=FloatDiv 299opLat=12 300pipelined=false 301 302[system.cpu.fuPool.FUList3.opList2] 303type=OpDesc 304eventq_index=0 305opClass=FloatSqrt 306opLat=24 307pipelined=false 308 309[system.cpu.fuPool.FUList4] 310type=FUDesc 311children=opList 312count=0 313eventq_index=0 314opList=system.cpu.fuPool.FUList4.opList 315 316[system.cpu.fuPool.FUList4.opList] 317type=OpDesc 318eventq_index=0 319opClass=MemRead 320opLat=1 321pipelined=true 322 323[system.cpu.fuPool.FUList5] 324type=FUDesc 325children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 326count=4 327eventq_index=0 328opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 329 330[system.cpu.fuPool.FUList5.opList00] 331type=OpDesc 332eventq_index=0 333opClass=SimdAdd 334opLat=1 335pipelined=true 336 337[system.cpu.fuPool.FUList5.opList01] 338type=OpDesc 339eventq_index=0 340opClass=SimdAddAcc 341opLat=1 342pipelined=true 343 344[system.cpu.fuPool.FUList5.opList02] 345type=OpDesc 346eventq_index=0 347opClass=SimdAlu 348opLat=1 349pipelined=true 350 351[system.cpu.fuPool.FUList5.opList03] 352type=OpDesc 353eventq_index=0 354opClass=SimdCmp 355opLat=1 356pipelined=true 357 358[system.cpu.fuPool.FUList5.opList04] 359type=OpDesc 360eventq_index=0 361opClass=SimdCvt 362opLat=1 363pipelined=true 364 365[system.cpu.fuPool.FUList5.opList05] 366type=OpDesc 367eventq_index=0 368opClass=SimdMisc 369opLat=1 370pipelined=true 371 372[system.cpu.fuPool.FUList5.opList06] 373type=OpDesc 374eventq_index=0 375opClass=SimdMult 376opLat=1 377pipelined=true 378 379[system.cpu.fuPool.FUList5.opList07] 380type=OpDesc 381eventq_index=0 382opClass=SimdMultAcc 383opLat=1 384pipelined=true 385 386[system.cpu.fuPool.FUList5.opList08] 387type=OpDesc 388eventq_index=0 389opClass=SimdShift 390opLat=1 391pipelined=true 392 393[system.cpu.fuPool.FUList5.opList09] 394type=OpDesc 395eventq_index=0 396opClass=SimdShiftAcc 397opLat=1 398pipelined=true 399 400[system.cpu.fuPool.FUList5.opList10] 401type=OpDesc 402eventq_index=0 403opClass=SimdSqrt 404opLat=1 405pipelined=true 406 407[system.cpu.fuPool.FUList5.opList11] 408type=OpDesc 409eventq_index=0 410opClass=SimdFloatAdd 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList5.opList12] 415type=OpDesc 416eventq_index=0 417opClass=SimdFloatAlu 418opLat=1 419pipelined=true 420 421[system.cpu.fuPool.FUList5.opList13] 422type=OpDesc 423eventq_index=0 424opClass=SimdFloatCmp 425opLat=1 426pipelined=true 427 428[system.cpu.fuPool.FUList5.opList14] 429type=OpDesc 430eventq_index=0 431opClass=SimdFloatCvt 432opLat=1 433pipelined=true 434 435[system.cpu.fuPool.FUList5.opList15] 436type=OpDesc 437eventq_index=0 438opClass=SimdFloatDiv 439opLat=1 440pipelined=true 441 442[system.cpu.fuPool.FUList5.opList16] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatMisc 446opLat=1 447pipelined=true 448 449[system.cpu.fuPool.FUList5.opList17] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatMult 453opLat=1 454pipelined=true 455 456[system.cpu.fuPool.FUList5.opList18] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatMultAcc 460opLat=1 461pipelined=true 462 463[system.cpu.fuPool.FUList5.opList19] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatSqrt 467opLat=1 468pipelined=true 469 470[system.cpu.fuPool.FUList6] 471type=FUDesc 472children=opList 473count=0 474eventq_index=0 475opList=system.cpu.fuPool.FUList6.opList 476 477[system.cpu.fuPool.FUList6.opList] 478type=OpDesc 479eventq_index=0 480opClass=MemWrite 481opLat=1 482pipelined=true 483 484[system.cpu.fuPool.FUList7] 485type=FUDesc 486children=opList0 opList1 487count=4 488eventq_index=0 489opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 490 491[system.cpu.fuPool.FUList7.opList0] 492type=OpDesc 493eventq_index=0 494opClass=MemRead 495opLat=1 496pipelined=true 497 498[system.cpu.fuPool.FUList7.opList1] 499type=OpDesc 500eventq_index=0 501opClass=MemWrite 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList8] 506type=FUDesc 507children=opList 508count=1 509eventq_index=0 510opList=system.cpu.fuPool.FUList8.opList 511 512[system.cpu.fuPool.FUList8.opList] 513type=OpDesc 514eventq_index=0 515opClass=IprAccess 516opLat=3 517pipelined=false 518 519[system.cpu.icache] 520type=Cache 521children=tags 522addr_ranges=0:18446744073709551615 523assoc=2 524clk_domain=system.cpu_clk_domain 525clusivity=mostly_incl 526demand_mshr_reserve=1 527eventq_index=0 528forward_snoops=true 529hit_latency=2 530is_read_only=true 531max_miss_count=0 532mshrs=4 533prefetch_on_access=false 534prefetcher=Null 535response_latency=2 536sequential_access=false 537size=131072 538system=system 539tags=system.cpu.icache.tags 540tgts_per_mshr=20 541write_buffers=8 542writeback_clean=true 543cpu_side=system.cpu.icache_port 544mem_side=system.cpu.toL2Bus.slave[0] 545 546[system.cpu.icache.tags] 547type=LRU 548assoc=2 549block_size=64 550clk_domain=system.cpu_clk_domain 551eventq_index=0 552hit_latency=2 553sequential_access=false 554size=131072 555 556[system.cpu.interrupts] 557type=X86LocalApic 558clk_domain=system.cpu.apic_clk_domain 559eventq_index=0 560int_latency=1000 561pio_addr=2305843009213693952 562pio_latency=100000 563system=system 564int_master=system.membus.slave[2] 565int_slave=system.membus.master[2] 566pio=system.membus.master[1] 567 568[system.cpu.isa] 569type=X86ISA 570eventq_index=0 571 572[system.cpu.itb] 573type=X86TLB 574children=walker 575eventq_index=0 576size=64 577walker=system.cpu.itb.walker 578 579[system.cpu.itb.walker] 580type=X86PagetableWalker 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583num_squash_per_cycle=4 584system=system 585port=system.cpu.toL2Bus.slave[2] 586 587[system.cpu.l2cache] 588type=Cache 589children=tags 590addr_ranges=0:18446744073709551615 591assoc=8 592clk_domain=system.cpu_clk_domain 593clusivity=mostly_incl 594demand_mshr_reserve=1 595eventq_index=0 596forward_snoops=true 597hit_latency=20 598is_read_only=false 599max_miss_count=0 600mshrs=20 601prefetch_on_access=false 602prefetcher=Null 603response_latency=20 604sequential_access=false 605size=2097152 606system=system 607tags=system.cpu.l2cache.tags 608tgts_per_mshr=12 609write_buffers=8 610writeback_clean=false 611cpu_side=system.cpu.toL2Bus.master[0] 612mem_side=system.membus.slave[1] 613 614[system.cpu.l2cache.tags] 615type=LRU 616assoc=8 617block_size=64 618clk_domain=system.cpu_clk_domain 619eventq_index=0 620hit_latency=20 621sequential_access=false 622size=2097152 623 624[system.cpu.toL2Bus] 625type=CoherentXBar 626children=snoop_filter 627clk_domain=system.cpu_clk_domain 628eventq_index=0 629forward_latency=0 630frontend_latency=1 631response_latency=1 632snoop_filter=system.cpu.toL2Bus.snoop_filter 633snoop_response_latency=1 634system=system 635use_default_range=false 636width=32 637master=system.cpu.l2cache.cpu_side 638slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 639 640[system.cpu.toL2Bus.snoop_filter] 641type=SnoopFilter 642eventq_index=0 643lookup_latency=0 644max_capacity=8388608 645system=system 646 647[system.cpu.tracer] 648type=ExeTracer 649eventq_index=0 650 651[system.cpu.workload] 652type=LiveProcess 653cmd=hello 654cwd= 655drivers= 656egid=100 657env= 658errout=cerr 659euid=100 660eventq_index=0 661executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello 662gid=100 663input=cin 664kvmInSE=false 665max_stack_size=67108864 666output=cout 667pid=100 668ppid=99 669simpoint=0 670system=system 671uid=100 672useArchPT=false 673 674[system.cpu_clk_domain] 675type=SrcClockDomain 676clock=500 677domain_id=-1 678eventq_index=0 679init_perf_level=0 680voltage_domain=system.voltage_domain 681 682[system.dvfs_handler] 683type=DVFSHandler 684domains= 685enable=false 686eventq_index=0 687sys_clk_domain=system.clk_domain 688transition_latency=100000000 689 690[system.membus] 691type=CoherentXBar 692clk_domain=system.clk_domain 693eventq_index=0 694forward_latency=4 695frontend_latency=3 696response_latency=2 697snoop_filter=Null 698snoop_response_latency=4 699system=system 700use_default_range=false 701width=16 702master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 703slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 704 705[system.physmem] 706type=DRAMCtrl 707IDD0=0.075000 708IDD02=0.000000 709IDD2N=0.050000 710IDD2N2=0.000000 711IDD2P0=0.000000 712IDD2P02=0.000000 713IDD2P1=0.000000 714IDD2P12=0.000000 715IDD3N=0.057000 716IDD3N2=0.000000 717IDD3P0=0.000000 718IDD3P02=0.000000 719IDD3P1=0.000000 720IDD3P12=0.000000 721IDD4R=0.187000 722IDD4R2=0.000000 723IDD4W=0.165000 724IDD4W2=0.000000 725IDD5=0.220000 726IDD52=0.000000 727IDD6=0.000000 728IDD62=0.000000 729VDD=1.500000 730VDD2=0.000000 731activation_limit=4 732addr_mapping=RoRaBaCoCh 733bank_groups_per_rank=0 734banks_per_rank=8 735burst_length=8 736channels=1 737clk_domain=system.clk_domain 738conf_table_reported=true 739device_bus_width=8 740device_rowbuffer_size=1024 741device_size=536870912 742devices_per_rank=8 743dll=true 744eventq_index=0 745in_addr_map=true 746max_accesses_per_row=16 747mem_sched_policy=frfcfs 748min_writes_per_switch=16 749null=false 750page_policy=open_adaptive 751range=0:134217727 752ranks_per_channel=2 753read_buffer_size=32 754static_backend_latency=10000 755static_frontend_latency=10000 756tBURST=5000 757tCCD_L=0 758tCK=1250 759tCL=13750 760tCS=2500 761tRAS=35000 762tRCD=13750 763tREFI=7800000 764tRFC=260000 765tRP=13750 766tRRD=6000 767tRRD_L=0 768tRTP=7500 769tRTW=2500 770tWR=15000 771tWTR=7500 772tXAW=30000 773tXP=0 774tXPDLL=0 775tXS=0 776tXSDLL=0 777write_buffer_size=64 778write_high_thresh_perc=85 779write_low_thresh_perc=50 780port=system.membus.master[0] 781 782[system.voltage_domain] 783type=VoltageDomain 784eventq_index=0 785voltage=1.000000 786 787