stats.txt revision 10488:7c27480a5031
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27800000 # Number of ticks simulated 5final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 583909 # Simulator instruction rate (inst/s) 8host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3038583452 # Simulator tick rate (ticks/s) 10host_mem_usage 285748 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24896 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 389 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) 32system.membus.trans_dist::ReadReq 308 # Transaction distribution 33system.membus.trans_dist::ReadResp 308 # Transaction distribution 34system.membus.trans_dist::ReadExReq 81 # Transaction distribution 35system.membus.trans_dist::ReadExResp 81 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 389 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 389 # Request fanout histogram 51system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 53system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 12.6 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.workload.num_syscalls 11 # Number of system calls 57system.cpu.numCycles 55600 # number of cpu cycles simulated 58system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 59system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 60system.cpu.committedInsts 5327 # Number of instructions committed 61system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 62system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 63system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 64system.cpu.num_func_calls 146 # number of times a function call or return occured 65system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 66system.cpu.num_int_insts 4505 # number of integer instructions 67system.cpu.num_fp_insts 0 # number of float instructions 68system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 69system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 70system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 71system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 72system.cpu.num_mem_refs 1401 # number of memory refs 73system.cpu.num_load_insts 723 # Number of load instructions 74system.cpu.num_store_insts 678 # Number of store instructions 75system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 76system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles 77system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 78system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 79system.cpu.Branches 1121 # Number of branches fetched 80system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 81system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 82system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 83system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 84system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 85system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 86system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 87system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 88system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 89system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 90system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 91system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 92system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 93system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 94system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 95system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 96system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 97system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 98system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 99system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 100system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 101system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 102system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 103system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 104system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 105system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 106system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 107system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 109system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 110system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 111system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 112system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 113system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 114system.cpu.op_class::total 5370 # Class of executed instruction 115system.cpu.icache.tags.replacements 0 # number of replacements 116system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use 117system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. 118system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. 119system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. 120system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor 122system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy 123system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy 124system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 125system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 126system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 127system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id 128system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses 129system.cpu.icache.tags.data_accesses 10999 # Number of data accesses 130system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits 131system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits 132system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits 133system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits 134system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits 135system.cpu.icache.overall_hits::total 5114 # number of overall hits 136system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses 137system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses 138system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses 139system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses 140system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses 141system.cpu.icache.overall_misses::total 257 # number of overall misses 142system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles 143system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles 144system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles 145system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles 146system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles 147system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles 148system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) 149system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) 150system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses 151system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses 152system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses 153system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses 154system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 155system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses 156system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses 157system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses 158system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses 159system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses 160system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency 161system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency 162system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 163system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency 164system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency 165system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency 166system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.icache.fast_writes 0 # number of fast writes performed 173system.cpu.icache.cache_copies 0 # number of cache copies performed 174system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses 175system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses 176system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses 177system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses 178system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses 179system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses 180system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles 181system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles 182system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles 183system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles 184system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles 185system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles 186system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses 187system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses 188system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 189system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses 190system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses 191system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses 192system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency 193system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency 194system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 195system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 196system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency 197system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency 198system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 199system.cpu.l2cache.tags.replacements 0 # number of replacements 200system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use 201system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 202system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. 203system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. 204system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 205system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor 206system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor 207system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy 208system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy 209system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy 210system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id 211system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 212system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 213system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id 214system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses 215system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses 216system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 217system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 218system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 219system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 220system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 221system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 222system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 223system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 224system.cpu.l2cache.overall_hits::total 3 # number of overall hits 225system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses 226system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses 227system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses 228system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses 229system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses 230system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 231system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 232system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses 233system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses 234system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 235system.cpu.l2cache.overall_misses::total 389 # number of overall misses 236system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles 237system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles 238system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles 239system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles 240system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles 241system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles 242system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles 243system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles 244system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles 245system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles 246system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles 247system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) 248system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) 249system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) 250system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) 251system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) 252system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses 253system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses 254system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses 255system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses 256system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses 257system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses 258system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses 260system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses 261system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 262system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 263system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses 264system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses 265system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses 266system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses 267system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses 268system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses 269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 270system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 271system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 272system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 273system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 274system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 275system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 276system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 277system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 278system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 279system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 280system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 281system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 282system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 283system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 284system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 285system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286system.cpu.l2cache.fast_writes 0 # number of fast writes performed 287system.cpu.l2cache.cache_copies 0 # number of cache copies performed 288system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses 289system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses 290system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses 291system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses 292system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses 293system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses 294system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses 295system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses 296system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses 297system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses 298system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses 299system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles 300system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles 302system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles 303system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles 304system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles 305system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles 306system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles 307system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles 308system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles 309system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles 310system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses 311system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses 312system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses 313system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 314system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 315system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses 316system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses 317system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses 318system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses 319system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses 320system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses 321system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 322system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 323system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 324system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 325system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 326system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 327system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 328system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 329system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 330system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 331system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 332system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 333system.cpu.dcache.tags.replacements 0 # number of replacements 334system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use 335system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. 336system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. 337system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. 338system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 339system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor 340system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy 341system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy 342system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id 343system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 344system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 345system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id 346system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses 347system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses 348system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits 349system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits 350system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits 351system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits 352system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits 353system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits 354system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits 355system.cpu.dcache.overall_hits::total 1253 # number of overall hits 356system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 357system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses 358system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses 359system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses 360system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses 361system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses 362system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses 363system.cpu.dcache.overall_misses::total 135 # number of overall misses 364system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles 365system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles 366system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles 367system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles 368system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles 369system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles 370system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles 371system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles 372system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) 373system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) 374system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) 375system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) 376system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses 377system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses 378system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses 379system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses 380system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses 381system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses 382system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses 383system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses 384system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses 385system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses 386system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses 387system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses 388system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency 389system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency 390system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 391system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 392system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 393system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency 394system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency 395system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency 396system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.dcache.fast_writes 0 # number of fast writes performed 403system.cpu.dcache.cache_copies 0 # number of cache copies performed 404system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 405system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses 406system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses 407system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses 408system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses 409system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses 410system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses 411system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses 412system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles 413system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles 414system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles 415system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles 416system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles 417system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles 418system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles 419system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles 420system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses 421system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses 422system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses 423system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses 424system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses 425system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses 426system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses 427system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses 428system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency 429system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency 430system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 431system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 432system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 433system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 434system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency 435system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency 436system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 437system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution 441system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.snoops 0 # Total snoops (count) 448system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram 449system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram 459system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) 460system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 461system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) 462system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 463system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) 464system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 465 466---------- End Simulation Statistics ---------- 467