stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000096 # Number of seconds simulated 4sim_ticks 95989 # Number of ticks simulated 5final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 73101 # Simulator instruction rate (inst/s) 8host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1316740 # Simulator tick rate (ticks/s) 10host_mem_usage 448980 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 5327 # Number of instructions simulated 13sim_ops 5327 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1289 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1285 # Number of write requests accepted 32system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 37760 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 45312 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 590 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 557 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 30 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 111 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 57 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 63 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 15 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 31 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 15 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 120 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 148 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 37 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 12 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 18 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 95925 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 699 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 50 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 47 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 43 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 43 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 43 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 43 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 43 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 43 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 43 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 43 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 230 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 387.339130 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 262.668395 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 318.441590 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 45 19.57% 19.57% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 51 22.17% 41.74% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 39 16.96% 58.70% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 22 9.57% 68.26% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 23 10.00% 78.26% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 5 2.17% 80.43% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 12 5.22% 85.65% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 9 3.91% 89.57% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 24 10.43% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 230 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 43 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 16.186047 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 15.978763 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 3.231215 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::14-15 22 51.16% 51.16% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::16-17 14 32.56% 83.72% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::18-19 5 11.63% 95.35% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::20-21 1 2.33% 97.67% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::34-35 1 2.33% 100.00% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::total 43 # Reads before turning the bus around for writes 211system.mem_ctrls.wrPerTurnAround::samples 43 # Writes before turning the bus around for reads 212system.mem_ctrls.wrPerTurnAround::mean 16.465116 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::gmean 16.435760 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::stdev 1.031615 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::16 35 81.40% 81.40% # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads 220system.mem_ctrls.totQLat 8743 # Total ticks spent queuing 221system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM 222system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers 223system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst 224system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 225system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst 226system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s 227system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s 228system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s 229system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s 230system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 231system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage 232system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads 233system.mem_ctrls.busUtilWrite 3.69 # Data bus utilization in percentage for writes 234system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 235system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing 236system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads 237system.mem_ctrls.writeRowHits 676 # Number of row buffer hits during writes 238system.mem_ctrls.readRowHitRate 70.96 # Row buffer hit rate for reads 239system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes 240system.mem_ctrls.avgGap 37.27 # Average gap between requests 241system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined 242system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) 243system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) 244system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) 245system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) 246system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 247system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) 248system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) 249system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) 250system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) 251system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states 255system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) 257system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) 258system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) 259system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) 260system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 261system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) 262system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) 263system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) 264system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) 265system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states 269system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 270system.cpu.clk_domain.clock 1 # Clock period in ticks 271system.cpu.workload.num_syscalls 11 # Number of system calls 272system.cpu.numCycles 95989 # number of cpu cycles simulated 273system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 274system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 275system.cpu.committedInsts 5327 # Number of instructions committed 276system.cpu.committedOps 5327 # Number of ops (including micro ops) committed 277system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 278system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 279system.cpu.num_func_calls 146 # number of times a function call or return occured 280system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 281system.cpu.num_int_insts 4505 # number of integer instructions 282system.cpu.num_fp_insts 0 # number of float instructions 283system.cpu.num_int_register_reads 10598 # number of times the integer registers were read 284system.cpu.num_int_register_writes 4845 # number of times the integer registers were written 285system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 286system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 287system.cpu.num_mem_refs 1401 # number of memory refs 288system.cpu.num_load_insts 723 # Number of load instructions 289system.cpu.num_store_insts 678 # Number of store instructions 290system.cpu.num_idle_cycles 0.999990 # Number of idle cycles 291system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles 292system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles 293system.cpu.idle_fraction 0.000010 # Percentage of idle cycles 294system.cpu.Branches 1121 # Number of branches fetched 295system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 296system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 297system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 298system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 299system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 300system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 301system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 302system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 303system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 304system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 305system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 306system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 307system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 308system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 309system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 310system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 311system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 312system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 313system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 314system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 315system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 316system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 317system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 318system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 319system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 320system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 321system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 322system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 323system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 324system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 325system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 326system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 327system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 328system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 329system.cpu.op_class::total 5370 # Class of executed instruction 330system.ruby.clk_domain.clock 1 # Clock period in ticks 331system.ruby.delayHist::bucket_size 1 # delay histogram for all message 332system.ruby.delayHist::max_bucket 9 # delay histogram for all message 333system.ruby.delayHist::samples 2574 # delay histogram for all message 334system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 335system.ruby.delayHist::total 2574 # delay histogram for all message 336system.ruby.outstanding_req_hist::bucket_size 1 337system.ruby.outstanding_req_hist::max_bucket 9 338system.ruby.outstanding_req_hist::samples 6759 339system.ruby.outstanding_req_hist::mean 1 340system.ruby.outstanding_req_hist::gmean 1 341system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 342system.ruby.outstanding_req_hist::total 6759 343system.ruby.latency_hist::bucket_size 64 344system.ruby.latency_hist::max_bucket 639 345system.ruby.latency_hist::samples 6758 346system.ruby.latency_hist::mean 13.203759 347system.ruby.latency_hist::gmean 5.149407 348system.ruby.latency_hist::stdev 25.345890 349system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 350system.ruby.latency_hist::total 6758 351system.ruby.hit_latency_hist::bucket_size 1 352system.ruby.hit_latency_hist::max_bucket 9 353system.ruby.hit_latency_hist::samples 5469 354system.ruby.hit_latency_hist::mean 3 355system.ruby.hit_latency_hist::gmean 3.000000 356system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 357system.ruby.hit_latency_hist::total 5469 358system.ruby.miss_latency_hist::bucket_size 64 359system.ruby.miss_latency_hist::max_bucket 639 360system.ruby.miss_latency_hist::samples 1289 361system.ruby.miss_latency_hist::mean 56.496509 362system.ruby.miss_latency_hist::gmean 50.965481 363system.ruby.miss_latency_hist::stdev 32.440273 364system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 365system.ruby.miss_latency_hist::total 1289 366system.ruby.Directory.incomplete_times 1288 367system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits 368system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses 369system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses 370system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 371system.ruby.network.routers0.percent_links_utilized 6.703893 372system.ruby.network.routers0.msg_count.Control::2 1289 373system.ruby.network.routers0.msg_count.Data::2 1285 374system.ruby.network.routers0.msg_count.Response_Data::4 1289 375system.ruby.network.routers0.msg_count.Writeback_Control::3 1285 376system.ruby.network.routers0.msg_bytes.Control::2 10312 377system.ruby.network.routers0.msg_bytes.Data::2 92520 378system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 379system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 380system.ruby.network.routers1.percent_links_utilized 6.703893 381system.ruby.network.routers1.msg_count.Control::2 1289 382system.ruby.network.routers1.msg_count.Data::2 1285 383system.ruby.network.routers1.msg_count.Response_Data::4 1289 384system.ruby.network.routers1.msg_count.Writeback_Control::3 1285 385system.ruby.network.routers1.msg_bytes.Control::2 10312 386system.ruby.network.routers1.msg_bytes.Data::2 92520 387system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 388system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 389system.ruby.network.routers2.percent_links_utilized 6.703893 390system.ruby.network.routers2.msg_count.Control::2 1289 391system.ruby.network.routers2.msg_count.Data::2 1285 392system.ruby.network.routers2.msg_count.Response_Data::4 1289 393system.ruby.network.routers2.msg_count.Writeback_Control::3 1285 394system.ruby.network.routers2.msg_bytes.Control::2 10312 395system.ruby.network.routers2.msg_bytes.Data::2 92520 396system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 397system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 398system.ruby.network.msg_count.Control 3867 399system.ruby.network.msg_count.Data 3855 400system.ruby.network.msg_count.Response_Data 3867 401system.ruby.network.msg_count.Writeback_Control 3855 402system.ruby.network.msg_byte.Control 30936 403system.ruby.network.msg_byte.Data 277560 404system.ruby.network.msg_byte.Response_Data 278424 405system.ruby.network.msg_byte.Writeback_Control 30840 406system.ruby.network.routers0.throttle0.link_utilization 6.712227 407system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 408system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 409system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 410system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 411system.ruby.network.routers0.throttle1.link_utilization 6.695559 412system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 413system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 414system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 415system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 416system.ruby.network.routers1.throttle0.link_utilization 6.695559 417system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 418system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 419system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 420system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 421system.ruby.network.routers1.throttle1.link_utilization 6.712227 422system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 423system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 424system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 425system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 426system.ruby.network.routers2.throttle0.link_utilization 6.712227 427system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 428system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 429system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 430system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 431system.ruby.network.routers2.throttle1.link_utilization 6.695559 432system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 433system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 434system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 435system.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 436system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 437system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 438system.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 439system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 440system.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 441system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 442system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 443system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 444system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 445system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 446system.ruby.LD.latency_hist::bucket_size 32 447system.ruby.LD.latency_hist::max_bucket 319 448system.ruby.LD.latency_hist::samples 715 449system.ruby.LD.latency_hist::mean 30.924476 450system.ruby.LD.latency_hist::gmean 13.876278 451system.ruby.LD.latency_hist::stdev 34.776798 452system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% 453system.ruby.LD.latency_hist::total 715 454system.ruby.LD.hit_latency_hist::bucket_size 1 455system.ruby.LD.hit_latency_hist::max_bucket 9 456system.ruby.LD.hit_latency_hist::samples 320 457system.ruby.LD.hit_latency_hist::mean 3 458system.ruby.LD.hit_latency_hist::gmean 3.000000 459system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 460system.ruby.LD.hit_latency_hist::total 320 461system.ruby.LD.miss_latency_hist::bucket_size 32 462system.ruby.LD.miss_latency_hist::max_bucket 319 463system.ruby.LD.miss_latency_hist::samples 395 464system.ruby.LD.miss_latency_hist::mean 53.546835 465system.ruby.LD.miss_latency_hist::gmean 47.987716 466system.ruby.LD.miss_latency_hist::stdev 32.331244 467system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% 468system.ruby.LD.miss_latency_hist::total 395 469system.ruby.ST.latency_hist::bucket_size 32 470system.ruby.ST.latency_hist::max_bucket 319 471system.ruby.ST.latency_hist::samples 673 472system.ruby.ST.latency_hist::mean 17.843982 473system.ruby.ST.latency_hist::gmean 6.493774 474system.ruby.ST.latency_hist::stdev 27.592771 475system.ruby.ST.latency_hist | 494 73.40% 73.40% | 145 21.55% 94.95% | 28 4.16% 99.11% | 1 0.15% 99.26% | 2 0.30% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 476system.ruby.ST.latency_hist::total 673 477system.ruby.ST.hit_latency_hist::bucket_size 1 478system.ruby.ST.hit_latency_hist::max_bucket 9 479system.ruby.ST.hit_latency_hist::samples 494 480system.ruby.ST.hit_latency_hist::mean 3 481system.ruby.ST.hit_latency_hist::gmean 3.000000 482system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 483system.ruby.ST.hit_latency_hist::total 494 484system.ruby.ST.miss_latency_hist::bucket_size 32 485system.ruby.ST.miss_latency_hist::max_bucket 319 486system.ruby.ST.miss_latency_hist::samples 179 487system.ruby.ST.miss_latency_hist::mean 58.810056 488system.ruby.ST.miss_latency_hist::gmean 54.709109 489system.ruby.ST.miss_latency_hist::stdev 23.983086 490system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 491system.ruby.ST.miss_latency_hist::total 179 492system.ruby.IFETCH.latency_hist::bucket_size 64 493system.ruby.IFETCH.latency_hist::max_bucket 639 494system.ruby.IFETCH.latency_hist::samples 5370 495system.ruby.IFETCH.latency_hist::mean 10.262756 496system.ruby.IFETCH.latency_hist::gmean 4.383388 497system.ruby.IFETCH.latency_hist::stdev 22.342607 498system.ruby.IFETCH.latency_hist | 5246 97.69% 97.69% | 101 1.88% 99.57% | 16 0.30% 99.87% | 1 0.02% 99.89% | 5 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 499system.ruby.IFETCH.latency_hist::total 5370 500system.ruby.IFETCH.hit_latency_hist::bucket_size 1 501system.ruby.IFETCH.hit_latency_hist::max_bucket 9 502system.ruby.IFETCH.hit_latency_hist::samples 4655 503system.ruby.IFETCH.hit_latency_hist::mean 3 504system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 505system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 506system.ruby.IFETCH.hit_latency_hist::total 4655 507system.ruby.IFETCH.miss_latency_hist::bucket_size 64 508system.ruby.IFETCH.miss_latency_hist::max_bucket 639 509system.ruby.IFETCH.miss_latency_hist::samples 715 510system.ruby.IFETCH.miss_latency_hist::mean 57.546853 511system.ruby.IFETCH.miss_latency_hist::gmean 51.762329 512system.ruby.IFETCH.miss_latency_hist::stdev 34.218674 513system.ruby.IFETCH.miss_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 514system.ruby.IFETCH.miss_latency_hist::total 715 515system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 516system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 517system.ruby.Directory.miss_mach_latency_hist::samples 1289 518system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 519system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 520system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 521system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 522system.ruby.Directory.miss_mach_latency_hist::total 1289 523system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 524system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 525system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 526system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 527system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 528system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 529system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 530system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 531system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 532system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 533system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 534system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 535system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 536system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 537system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 538system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 539system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 540system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 541system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 542system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 543system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 544system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 545system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 546system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 547system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 548system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 549system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 550system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 551system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 552system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 553system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 554system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 555system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% 556system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 557system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 558system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 559system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 560system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 58.810056 561system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 54.709109 562system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.983086 563system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 564system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 565system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 566system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 567system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 568system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.546853 569system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 570system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 571system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 572system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 573system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% 574system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% 575system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% 576system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% 577system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% 578system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% 579system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% 580system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% 581system.ruby.L1Cache_Controller.Load 715 0.00% 0.00% 582system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% 583system.ruby.L1Cache_Controller.Store 673 0.00% 0.00% 584system.ruby.L1Cache_Controller.Data 1289 0.00% 0.00% 585system.ruby.L1Cache_Controller.Replacement 1285 0.00% 0.00% 586system.ruby.L1Cache_Controller.Writeback_Ack 1285 0.00% 0.00% 587system.ruby.L1Cache_Controller.I.Load 395 0.00% 0.00% 588system.ruby.L1Cache_Controller.I.Ifetch 715 0.00% 0.00% 589system.ruby.L1Cache_Controller.I.Store 179 0.00% 0.00% 590system.ruby.L1Cache_Controller.M.Load 320 0.00% 0.00% 591system.ruby.L1Cache_Controller.M.Ifetch 4655 0.00% 0.00% 592system.ruby.L1Cache_Controller.M.Store 494 0.00% 0.00% 593system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% 594system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% 595system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% 596system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% 597 598---------- End Simulation Statistics ---------- 599