stats.txt revision 10628
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 310526Snilay@cs.wisc.edusim_seconds 0.000096 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 95989 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68343SN/Asim_freq 1000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 73101 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 73087 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 1316740 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 448980 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 0.07 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5327 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5327 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory 1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory 1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory 1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory 2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory 2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory 2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory 2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory 2410628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) 2510628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) 2610628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) 2710628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) 2810628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) 2910628Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) 3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs 1289 # Number of read requests accepted 3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs 1285 # Number of write requests accepted 3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue 3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue 3410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM 3510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ 37760 # Total number of bytes read from write queue 3610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten 45312 # Total number of bytes written to DRAM 3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side 3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side 3910526Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ 590 # Number of DRAM read bursts serviced by the write queue 4010526Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts 557 # Number of DRAM write bursts merged with an existing one 4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0 30 # Per bank write bursts 4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts 4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts 4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts 4610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts 4710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5 111 # Per bank write bursts 4810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts 4910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts 5010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8 57 # Per bank write bursts 5110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts 5210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts 5310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts 5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts 5510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13 63 # Per bank write bursts 5610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14 15 # Per bank write bursts 5710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts 5810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0 31 # Per bank write bursts 5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1 15 # Per bank write bursts 6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts 6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts 6210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts 6310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts 6410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6 120 # Per bank write bursts 6510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7 148 # Per bank write bursts 6610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts 6710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9 37 # Per bank write bursts 6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10 12 # Per bank write bursts 6910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts 7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts 7110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts 7210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14 18 # Per bank write bursts 7310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts 7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 7610628Sandreas.hansson@arm.comsystem.mem_ctrls.totGap 95925 # Total gap between requests 7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2) 8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) 9110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0 699 # What read queue length does an incoming req see 9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 13910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see 14010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see 14110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see 14210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19 50 # What write queue length does an incoming req see 14310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20 47 # What write queue length does an incoming req see 14410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see 14510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see 14610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23 43 # What write queue length does an incoming req see 14710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24 43 # What write queue length does an incoming req see 14810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see 14910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26 43 # What write queue length does an incoming req see 15010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27 43 # What write queue length does an incoming req see 15110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28 43 # What write queue length does an incoming req see 15210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29 43 # What write queue length does an incoming req see 15310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30 43 # What write queue length does an incoming req see 15410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31 43 # What write queue length does an incoming req see 15510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see 15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see 15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 18710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples 230 # Bytes accessed per row activation 18810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean 387.339130 # Bytes accessed per row activation 18910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean 262.668395 # Bytes accessed per row activation 19010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev 318.441590 # Bytes accessed per row activation 19110526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127 45 19.57% 19.57% # Bytes accessed per row activation 19210526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255 51 22.17% 41.74% # Bytes accessed per row activation 19310526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383 39 16.96% 58.70% # Bytes accessed per row activation 19410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511 22 9.57% 68.26% # Bytes accessed per row activation 19510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639 23 10.00% 78.26% # Bytes accessed per row activation 19610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767 5 2.17% 80.43% # Bytes accessed per row activation 19710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895 12 5.22% 85.65% # Bytes accessed per row activation 19810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023 9 3.91% 89.57% # Bytes accessed per row activation 19910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151 24 10.43% 100.00% # Bytes accessed per row activation 20010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total 230 # Bytes accessed per row activation 20110526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples 43 # Reads before turning the bus around for writes 20210526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean 16.186047 # Reads before turning the bus around for writes 20310526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::gmean 15.978763 # Reads before turning the bus around for writes 20410526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev 3.231215 # Reads before turning the bus around for writes 20510526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::14-15 22 51.16% 51.16% # Reads before turning the bus around for writes 20610526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::16-17 14 32.56% 83.72% # Reads before turning the bus around for writes 20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::18-19 5 11.63% 95.35% # Reads before turning the bus around for writes 20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::20-21 1 2.33% 97.67% # Reads before turning the bus around for writes 20910526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::34-35 1 2.33% 100.00% # Reads before turning the bus around for writes 21010526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total 43 # Reads before turning the bus around for writes 21110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples 43 # Writes before turning the bus around for reads 21210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean 16.465116 # Writes before turning the bus around for reads 21310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean 16.435760 # Writes before turning the bus around for reads 21410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev 1.031615 # Writes before turning the bus around for reads 21510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16 35 81.40% 81.40% # Writes before turning the bus around for reads 21610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Writes before turning the bus around for reads 21710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads 21810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads 21910526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads 22010628Sandreas.hansson@arm.comsystem.mem_ctrls.totQLat 8743 # Total ticks spent queuing 22110628Sandreas.hansson@arm.comsystem.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM 22210526Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers 22310526Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst 22410526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 22510526Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst 22610628Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s 22710628Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s 22810628Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s 22910628Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s 23010526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage 23210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads 23310526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite 3.69 # Data bus utilization in percentage for writes 23410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 23510526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing 23610526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads 23710526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits 676 # Number of row buffer hits during writes 23810526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate 70.96 # Row buffer hit rate for reads 23910526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes 24010526Snilay@cs.wisc.edusystem.mem_ctrls.avgGap 37.27 # Average gap between requests 24110526Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined 24210628Sandreas.hansson@arm.comsystem.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) 24410628Sandreas.hansson@arm.comsystem.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) 24510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) 24610628Sandreas.hansson@arm.comsystem.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 24710628Sandreas.hansson@arm.comsystem.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) 24810628Sandreas.hansson@arm.comsystem.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) 24910628Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) 25010628Sandreas.hansson@arm.comsystem.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) 25110628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states 25310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 25410628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states 25510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 25610628Sandreas.hansson@arm.comsystem.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) 25710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) 25810628Sandreas.hansson@arm.comsystem.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) 25910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) 26010628Sandreas.hansson@arm.comsystem.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 26110628Sandreas.hansson@arm.comsystem.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) 26210628Sandreas.hansson@arm.comsystem.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) 26310628Sandreas.hansson@arm.comsystem.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) 26410628Sandreas.hansson@arm.comsystem.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) 26510628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states 26610628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states 26710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 26810628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states 26910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27010526Snilay@cs.wisc.edusystem.cpu.clk_domain.clock 1 # Clock period in ticks 2718343SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 27210628Sandreas.hansson@arm.comsystem.cpu.numCycles 95989 # number of cpu cycles simulated 2738343SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2747935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2759150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5327 # Number of instructions committed 2769150SAli.Saidi@ARM.comsystem.cpu.committedOps 5327 # Number of ops (including micro ops) committed 2779150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 2787935SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2798343SN/Asystem.cpu.num_func_calls 146 # number of times a function call or return occured 2809150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 2819150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 4505 # number of integer instructions 2827935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2839150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 10598 # number of times the integer registers were read 2849150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4845 # number of times the integer registers were written 2857935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2867935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2879150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 1401 # number of memory refs 2889150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 723 # Number of load instructions 2898343SN/Asystem.cpu.num_store_insts 678 # Number of store instructions 29010526Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 0.999990 # Number of idle cycles 29110628Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 95988.000010 # Number of busy cycles 29210526Snilay@cs.wisc.edusystem.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles 29310526Snilay@cs.wisc.edusystem.cpu.idle_fraction 0.000010 # Percentage of idle cycles 29410063Snilay@cs.wisc.edusystem.cpu.Branches 1121 # Number of branches fetched 29510220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 29610220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 29710220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 29810220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 29910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 30010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 30110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 30210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 30310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 30410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 30510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 30610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 30710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 30810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 30910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 31010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 31110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 31210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 31310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 31410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 31510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 31610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 31710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 31810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 31910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 32010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 32110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 32210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 32310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 32410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 32510220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 32610220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 32710220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 32810220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 32910220Sandreas.hansson@arm.comsystem.cpu.op_class::total 5370 # Class of executed instruction 33010628Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 33110628Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 33210628Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 33310628Sandreas.hansson@arm.comsystem.ruby.delayHist::samples 2574 # delay histogram for all message 33410628Sandreas.hansson@arm.comsystem.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 33510628Sandreas.hansson@arm.comsystem.ruby.delayHist::total 2574 # delay histogram for all message 33610628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size 1 33710628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket 9 33810628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::samples 6759 33910628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::mean 1 34010628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::gmean 1 34110628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 34210628Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::total 6759 34310628Sandreas.hansson@arm.comsystem.ruby.latency_hist::bucket_size 64 34410628Sandreas.hansson@arm.comsystem.ruby.latency_hist::max_bucket 639 34510628Sandreas.hansson@arm.comsystem.ruby.latency_hist::samples 6758 34610628Sandreas.hansson@arm.comsystem.ruby.latency_hist::mean 13.203759 34710628Sandreas.hansson@arm.comsystem.ruby.latency_hist::gmean 5.149407 34810628Sandreas.hansson@arm.comsystem.ruby.latency_hist::stdev 25.345890 34910628Sandreas.hansson@arm.comsystem.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35010628Sandreas.hansson@arm.comsystem.ruby.latency_hist::total 6758 35110628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size 1 35210628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket 9 35310628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::samples 5469 35410628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::mean 3 35510628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::gmean 3.000000 35610628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 35710628Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::total 5469 35810628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::bucket_size 64 35910628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::max_bucket 639 36010628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::samples 1289 36110628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::mean 56.496509 36210628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::gmean 50.965481 36310628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::stdev 32.440273 36410628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 36510628Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::total 1289 36610628Sandreas.hansson@arm.comsystem.ruby.Directory.incomplete_times 1288 36710628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits 36810628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses 36910628Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses 37010628Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 37110628Sandreas.hansson@arm.comsystem.ruby.network.routers0.percent_links_utilized 6.703893 37210628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::2 1289 37310628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Data::2 1285 37410628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::4 1289 37510628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::3 1285 37610628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::2 10312 37710628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Data::2 92520 37810628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::4 92808 37910628Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 38010628Sandreas.hansson@arm.comsystem.ruby.network.routers1.percent_links_utilized 6.703893 38110628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::2 1289 38210628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Data::2 1285 38310628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::4 1289 38410628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::3 1285 38510628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::2 10312 38610628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Data::2 92520 38710628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::4 92808 38810628Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 38910628Sandreas.hansson@arm.comsystem.ruby.network.routers2.percent_links_utilized 6.703893 39010628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::2 1289 39110628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Data::2 1285 39210628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::4 1289 39310628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::3 1285 39410628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::2 10312 39510628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Data::2 92520 39610628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::4 92808 39710628Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 39810628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control 3867 39910628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Data 3855 40010628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data 3867 40110628Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control 3855 40210628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control 30936 40310628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Data 277560 40410628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data 278424 40510628Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control 30840 40610628Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.link_utilization 6.712227 4079864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 4089864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 4099864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 4109864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 41110628Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.link_utilization 6.695559 4129864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1289 4139864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1285 4149864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 4159864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 41610628Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.link_utilization 6.695559 4179864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1289 4189864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1285 4199864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 4209864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 42110628Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.link_utilization 6.712227 4229864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 4239864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 4249864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 4259864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 42610628Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.link_utilization 6.712227 4279864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 4289864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 4299864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 4309864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 43110628Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.link_utilization 6.695559 4329864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1289 4339864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1285 4349864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 4359864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 43610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 43710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 43810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 43910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 44010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 44110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 44210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 44310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 44410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 44510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 44610526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size 32 44710526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket 319 44810013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 715 44910628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::mean 30.924476 45010628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::gmean 13.876278 45110628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::stdev 34.776798 45210526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% 45310013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 715 45410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 45510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 45610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 320 45710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 45810013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 45910013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 46010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 320 46110526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size 32 46210526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket 319 46310013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 395 46410628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::mean 53.546835 46510628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::gmean 47.987716 46610628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::stdev 32.331244 46710526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% 46810013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 395 46910526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 32 47010526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 319 47110013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 673 47210526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean 17.843982 47310526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean 6.493774 47410526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev 27.592771 47510526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist | 494 73.40% 73.40% | 145 21.55% 94.95% | 28 4.16% 99.11% | 1 0.15% 99.26% | 2 0.30% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 47610013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 673 47710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 47810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 47910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 494 48010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 48110013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 48210013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 48310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 494 48410526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 32 48510526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 319 48610013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 179 48710526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean 58.810056 48810526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean 54.709109 48910526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev 23.983086 49010526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 49110013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 179 49210526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 64 49310526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 639 49410013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 5370 49510526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean 10.262756 49610526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean 4.383388 49710526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev 22.342607 49810526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist | 5246 97.69% 97.69% | 101 1.88% 99.57% | 16 0.30% 99.87% | 1 0.02% 99.89% | 5 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 49910013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 5370 50010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 50110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 50210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 4655 50310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 50410013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 50510013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 50610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 4655 50710526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 64 50810526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 639 50910013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 715 51010526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean 57.546853 51110526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean 51.762329 51210526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev 34.218674 51310526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 51410013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 715 51510526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 64 51610526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 639 51710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1289 51810628Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::mean 56.496509 51910628Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 52010628Sandreas.hansson@arm.comsystem.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 52110526Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 52210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1289 52310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 52410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 52510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 52610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 52710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 52810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 52910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 53010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 53110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 53210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 53310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 53410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 53510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 53610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 53710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 53810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 53910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 54010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 54110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 54210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 54310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 54410526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 54510526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 54610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 54710526Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 54810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 54910526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 55010526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 55110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 55210628Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 55310628Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 55410628Sandreas.hansson@arm.comsystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 55510526Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% 55610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 55710526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 55810526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 55910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 56010526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 58.810056 56110526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 54.709109 56210526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.983086 56310526Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 56410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 56510526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 56610526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 56710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 56810526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.546853 56910526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 57010526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 57110526Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 57210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 57310628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.GETX 1289 0.00% 0.00% 57410628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% 57510628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% 57610628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% 57710628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% 57810628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% 57910628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% 58010628Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% 58110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 715 0.00% 0.00% 58210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% 58310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 673 0.00% 0.00% 58410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1289 0.00% 0.00% 58510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1285 0.00% 0.00% 58610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1285 0.00% 0.00% 58710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 395 0.00% 0.00% 58810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 715 0.00% 0.00% 58910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 179 0.00% 0.00% 59010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 320 0.00% 0.00% 59110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 4655 0.00% 0.00% 59210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 494 0.00% 0.00% 59310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% 59410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% 59510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% 59610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% 5976167SN/A 5986167SN/A---------- End Simulation Statistics ---------- 599