stats.txt revision 10220
16167SN/A 26167SN/A---------- Begin Simulation Statistics ---------- 39204Sandreas.hansson@arm.comsim_seconds 0.000108 # Number of seconds simulated 49204Sandreas.hansson@arm.comsim_ticks 107952 # Number of ticks simulated 59204Sandreas.hansson@arm.comfinal_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68343SN/Asim_freq 1000000000 # Frequency of simulated ticks 710220Sandreas.hansson@arm.comhost_inst_rate 57135 # Simulator instruction rate (inst/s) 810220Sandreas.hansson@arm.comhost_op_rate 57126 # Simulator op (including micro ops) rate (op/s) 910220Sandreas.hansson@arm.comhost_tick_rate 1157488 # Simulator tick rate (ticks/s) 1010220Sandreas.hansson@arm.comhost_mem_usage 168948 # Number of bytes of host memory used 1110220Sandreas.hansson@arm.comhost_seconds 0.09 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 5327 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 5327 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1 # Clock period in ticks 1610036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock 1 # Clock period in ticks 1710013Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size 1 # delay histogram for all message 1810013Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket 9 # delay histogram for all message 1910013Snilay@cs.wisc.edusystem.ruby.delayHist::samples 2574 # delay histogram for all message 2010013Snilay@cs.wisc.edusystem.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 2110013Snilay@cs.wisc.edusystem.ruby.delayHist::total 2574 # delay histogram for all message 2210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size 1 2310013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket 9 2410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples 6759 2510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean 1 2610013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean 1 2710013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 2810013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total 6759 2910013Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size 16 3010013Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket 159 3110013Snilay@cs.wisc.edusystem.ruby.latency_hist::samples 6758 3210013Snilay@cs.wisc.edusystem.ruby.latency_hist::mean 14.973957 3310013Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean 5.402086 3410013Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev 24.830446 3510013Snilay@cs.wisc.edusystem.ruby.latency_hist | 5469 80.93% 80.93% | 0 0.00% 80.93% | 0 0.00% 80.93% | 306 4.53% 85.45% | 913 13.51% 98.96% | 68 1.01% 99.97% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 3610013Snilay@cs.wisc.edusystem.ruby.latency_hist::total 6758 3710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size 1 3810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket 9 3910013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples 5469 4010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean 3 4110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean 3.000000 4210013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 4310013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total 5469 4410013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size 16 4510013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket 159 4610013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples 1289 4710013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean 65.777347 4810013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean 65.516328 4910013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev 6.536157 5010013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 5110013Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total 1289 5210013Snilay@cs.wisc.edusystem.ruby.Directory.incomplete_times 1288 5310036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 549698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits 559698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses 569698Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses 579864Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized 5.960983 589864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::2 1289 599864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Data::2 1285 609864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::4 1289 619864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::3 1285 629864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::2 10312 639864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Data::2 92520 649864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::4 92808 659864Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 669748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests 679748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads 689748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes 699748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes 709748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue 719748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue 729748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles 739748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request 749748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank 759748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus 769748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround 779748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration 789748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank 799748Snilay@cs.wisc.edusystem.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank 809864Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized 5.960983 819864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::2 1289 829864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Data::2 1285 839864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::4 1289 849864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::3 1285 859864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::2 10312 869864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Data::2 92520 879864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::4 92808 889864Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 899864Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized 5.960983 909864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::2 1289 919864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Data::2 1285 929864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::4 1289 939864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::3 1285 949864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::2 10312 959864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Data::2 92520 969864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::4 92808 979864Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 989885Sstever@gmail.comsystem.ruby.network.msg_count.Control 3867 999885Sstever@gmail.comsystem.ruby.network.msg_count.Data 3855 1009885Sstever@gmail.comsystem.ruby.network.msg_count.Response_Data 3867 1019885Sstever@gmail.comsystem.ruby.network.msg_count.Writeback_Control 3855 1029885Sstever@gmail.comsystem.ruby.network.msg_byte.Control 30936 1039885Sstever@gmail.comsystem.ruby.network.msg_byte.Data 277560 1049885Sstever@gmail.comsystem.ruby.network.msg_byte.Response_Data 278424 1059885Sstever@gmail.comsystem.ruby.network.msg_byte.Writeback_Control 30840 10610036SAli.Saidi@ARM.comsystem.cpu.clk_domain.clock 1 # Clock period in ticks 1078343SN/Asystem.cpu.workload.num_syscalls 11 # Number of system calls 1089204Sandreas.hansson@arm.comsystem.cpu.numCycles 107952 # number of cpu cycles simulated 1098343SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1107935SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1119150SAli.Saidi@ARM.comsystem.cpu.committedInsts 5327 # Number of instructions committed 1129150SAli.Saidi@ARM.comsystem.cpu.committedOps 5327 # Number of ops (including micro ops) committed 1139150SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses 1147935SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 1158343SN/Asystem.cpu.num_func_calls 146 # number of times a function call or return occured 1169150SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls 1179150SAli.Saidi@ARM.comsystem.cpu.num_int_insts 4505 # number of integer instructions 1187935SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 1199150SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 10598 # number of times the integer registers were read 1209150SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 4845 # number of times the integer registers were written 1217935SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 1227935SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1239150SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 1401 # number of memory refs 1249150SAli.Saidi@ARM.comsystem.cpu.num_load_insts 723 # Number of load instructions 1258343SN/Asystem.cpu.num_store_insts 678 # Number of store instructions 1267935SN/Asystem.cpu.num_idle_cycles 0 # Number of idle cycles 1279204Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 107952 # Number of busy cycles 1288343SN/Asystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 1298343SN/Asystem.cpu.idle_fraction 0 # Percentage of idle cycles 13010063Snilay@cs.wisc.edusystem.cpu.Branches 1121 # Number of branches fetched 13110220Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction 13210220Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction 13310220Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction 13410220Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction 13510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction 13610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction 13710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction 13810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction 13910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction 14010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction 14110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction 14210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction 14310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction 14410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction 14510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction 14610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction 14710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction 14810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction 14910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction 15010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction 15110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction 15210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction 15310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction 15410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction 15510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction 15610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction 15710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction 15810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction 15910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction 16010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction 16110220Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction 16210220Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction 16310220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 16410220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 16510220Sandreas.hansson@arm.comsystem.cpu.op_class::total 5370 # Class of executed instruction 1669864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization 5.968393 1679864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 1689864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 1699864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 1709864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 1719864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization 5.953572 1729864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::2 1289 1739864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Data::2 1285 1749864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 1759864Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 1769864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization 5.953572 1779864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Control::2 1289 1789864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Data::2 1285 1799864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 1809864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 1819864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization 5.968393 1829864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 1839864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 1849864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 1859864Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 1869864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization 5.968393 1879864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 1889864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 1899864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 1909864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 1919864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization 5.953572 1929864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::2 1289 1939864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Data::2 1285 1949864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 1959864Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 19610013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 19710013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 19810013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 19910013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 20010013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 20110013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 20210013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 20310013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 20410013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 20510013Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 20610013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size 16 20710013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket 159 20810013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples 715 20910013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean 37.334266 21010013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean 16.405583 21110013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev 31.171638 21210013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist | 320 44.76% 44.76% | 0 0.00% 44.76% | 0 0.00% 44.76% | 105 14.69% 59.44% | 276 38.60% 98.04% | 14 1.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 21310013Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total 715 21410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size 1 21510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket 9 21610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples 320 21710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean 3 21810013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean 3.000000 21910013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 22010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total 320 22110013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size 16 22210013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket 159 22310013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples 395 22410013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean 65.149367 22510013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean 64.977069 22610013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev 5.269438 22710013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 26.58% 26.58% | 276 69.87% 96.46% | 14 3.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 22810013Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total 395 22910013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size 16 23010013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket 159 23110013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples 673 23210013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean 20.022288 23310013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean 6.840248 23410013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev 28.682599 23510013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist | 494 73.40% 73.40% | 0 0.00% 73.40% | 0 0.00% 73.40% | 45 6.69% 80.09% | 117 17.38% 97.47% | 16 2.38% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 23610013Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total 673 23710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size 1 23810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket 9 23910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples 494 24010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean 3 24110013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean 3.000000 24210013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 24310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total 494 24410013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size 16 24510013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket 159 24610013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples 179 24710013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean 67 24810013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean 66.517437 24910013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev 9.078930 25010013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 25.14% 25.14% | 117 65.36% 90.50% | 16 8.94% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 25110013Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total 179 25210013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size 16 25310013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket 159 25410013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples 5370 25510013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean 11.364060 25610013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean 4.523558 25710013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev 21.469550 25810013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist | 4655 86.69% 86.69% | 0 0.00% 86.69% | 0 0.00% 86.69% | 156 2.91% 89.59% | 520 9.68% 99.27% | 38 0.71% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 25910013Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total 5370 26010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size 1 26110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket 9 26210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples 4655 26310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean 3 26410013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean 3.000000 26510013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 26610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total 4655 26710013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size 16 26810013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket 159 26910013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples 715 27010013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean 65.818182 27110013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean 65.566761 27210013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev 6.371809 27310013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 156 21.82% 21.82% | 520 72.73% 94.55% | 38 5.31% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 27410013Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total 715 27510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::bucket_size 16 27610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::max_bucket 159 27710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::samples 1289 27810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::mean 65.777347 27910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::gmean 65.516328 28010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::stdev 6.536157 28110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_mach_latency_hist::total 1289 28310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 28410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 28510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 28610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 28710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 28810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 28910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 29010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 29110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 29210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 29310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 29410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 29510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 29610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 29710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 29810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 29910013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30010013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 30110013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 30210013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 30310013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 30410013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61 30510013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000 30610013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 30710013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 30810013Snilay@cs.wisc.edusystem.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 30910013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 31010013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 31110013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 31210013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.149367 31310013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 64.977069 31410013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.269438 31510013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 26.58% 26.58% | 276 69.87% 96.46% | 14 3.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 31610013Snilay@cs.wisc.edusystem.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 31710013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 31810013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 31910013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 32010013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::mean 67 32110013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 66.517437 32210013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 9.078930 32310013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 25.14% 25.14% | 117 65.36% 90.50% | 16 8.94% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 32410013Snilay@cs.wisc.edusystem.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 32510013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 32610013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 32710013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 32810013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.818182 32910013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.566761 33010013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 6.371809 33110013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 156 21.82% 21.82% | 520 72.73% 94.55% | 38 5.31% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 33210013Snilay@cs.wisc.edusystem.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 33310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load 715 0.00% 0.00% 33410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% 33510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store 673 0.00% 0.00% 33610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data 1289 0.00% 0.00% 33710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Replacement 1285 0.00% 0.00% 33810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Writeback_Ack 1285 0.00% 0.00% 33910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load 395 0.00% 0.00% 34010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch 715 0.00% 0.00% 34110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store 179 0.00% 0.00% 34210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load 320 0.00% 0.00% 34310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Ifetch 4655 0.00% 0.00% 34410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store 494 0.00% 0.00% 34510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% 34610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% 34710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% 34810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% 34910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.GETX 1289 0.00% 0.00% 35010013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% 35110013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% 35210013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% 35310013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% 35410013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% 35510013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% 35610013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% 3576167SN/A 3586167SN/A---------- End Simulation Statistics ---------- 359