stats.txt revision 11731:c473ca7cc650
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 11602500 # Number of ticks simulated 5final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 36172 # Simulator instruction rate (inst/s) 8host_op_rate 36155 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 264212858 # Simulator tick rate (ticks/s) 10host_mem_usage 230876 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 1587 # Number of instructions simulated 13sim_ops 1587 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9728 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 152 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.read_hits 0 # DTB read hits 36system.cpu.dtb.read_misses 0 # DTB read misses 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_hits 0 # DTB write hits 39system.cpu.dtb.write_misses 0 # DTB write misses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.hits 0 # DTB hits 42system.cpu.dtb.misses 0 # DTB misses 43system.cpu.dtb.accesses 0 # DTB accesses 44system.cpu.itb.read_hits 0 # DTB read hits 45system.cpu.itb.read_misses 0 # DTB read misses 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_accesses 0 # DTB write accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 9 # Number of system calls 54system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states 55system.cpu.numCycles 23205 # number of cpu cycles simulated 56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58system.cpu.committedInsts 1587 # Number of instructions committed 59system.cpu.committedOps 1587 # Number of ops (including micro ops) committed 60system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses 61system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 62system.cpu.num_func_calls 142 # number of times a function call or return occured 63system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls 64system.cpu.num_int_insts 1588 # number of integer instructions 65system.cpu.num_fp_insts 0 # number of float instructions 66system.cpu.num_int_register_reads 2062 # number of times the integer registers were read 67system.cpu.num_int_register_writes 1077 # number of times the integer registers were written 68system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 69system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 70system.cpu.num_mem_refs 569 # number of memory refs 71system.cpu.num_load_insts 289 # Number of load instructions 72system.cpu.num_store_insts 280 # Number of store instructions 73system.cpu.num_idle_cycles 0 # Number of idle cycles 74system.cpu.num_busy_cycles 23205 # Number of busy cycles 75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 76system.cpu.idle_fraction 0 # Percentage of idle cycles 77system.cpu.Branches 373 # Number of branches fetched 78system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction 79system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction 80system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction 81system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction 82system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction 83system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction 84system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction 85system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction 86system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction 87system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction 88system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction 89system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction 90system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction 91system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction 92system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction 93system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction 94system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction 95system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction 96system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction 97system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction 98system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction 99system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction 100system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction 101system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction 102system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction 103system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction 104system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction 105system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction 106system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction 107system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction 108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction 109system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction 110system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction 111system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction 112system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction 113system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction 114system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 115system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 116system.cpu.op_class::total 1597 # Class of executed instruction 117system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 118system.cpu.dcache.tags.replacements 0 # number of replacements 119system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use 120system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks. 121system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. 122system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks. 123system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 124system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor 125system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy 126system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy 127system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id 128system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 129system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 130system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id 131system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses 132system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses 133system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 134system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits 135system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits 136system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits 137system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits 138system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits 139system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits 140system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits 141system.cpu.dcache.overall_hits::total 537 # number of overall hits 142system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses 143system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses 144system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses 145system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses 146system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses 147system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses 148system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses 149system.cpu.dcache.overall_misses::total 31 # number of overall misses 150system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles 151system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles 152system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles 153system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles 154system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles 155system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles 156system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles 157system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles 158system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses) 159system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses) 160system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) 161system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) 162system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses 163system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses 164system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses 165system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses 166system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses 167system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses 168system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses 169system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses 170system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses 171system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses 172system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses 173system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses 174system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency 175system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 177system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 178system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency 179system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency 180system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency 181system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency 182system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 183system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 184system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 185system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 186system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 187system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses 189system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses 191system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses 192system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses 193system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses 194system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses 195system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses 196system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles 198system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles 199system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles 200system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles 201system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles 202system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles 203system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles 204system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses 205system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses 206system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses 207system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses 208system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses 209system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses 210system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses 211system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses 212system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency 213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency 214system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 216system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency 217system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency 218system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency 219system.cpu.dcache.overall_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency 220system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 221system.cpu.icache.tags.replacements 0 # number of replacements 222system.cpu.icache.tags.tagsinuse 56.912998 # Cycle average of tags in use 223system.cpu.icache.tags.total_refs 1476 # Total number of references to valid blocks. 224system.cpu.icache.tags.sampled_refs 122 # Sample count of references to valid blocks. 225system.cpu.icache.tags.avg_refs 12.098361 # Average number of references to valid blocks. 226system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 227system.cpu.icache.tags.occ_blocks::cpu.inst 56.912998 # Average occupied blocks per requestor 228system.cpu.icache.tags.occ_percent::cpu.inst 0.027790 # Average percentage of cache occupancy 229system.cpu.icache.tags.occ_percent::total 0.027790 # Average percentage of cache occupancy 230system.cpu.icache.tags.occ_task_id_blocks::1024 122 # Occupied blocks per task id 231system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 232system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.059570 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.tag_accesses 3318 # Number of tag accesses 235system.cpu.icache.tags.data_accesses 3318 # Number of data accesses 236system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 237system.cpu.icache.ReadReq_hits::cpu.inst 1476 # number of ReadReq hits 238system.cpu.icache.ReadReq_hits::total 1476 # number of ReadReq hits 239system.cpu.icache.demand_hits::cpu.inst 1476 # number of demand (read+write) hits 240system.cpu.icache.demand_hits::total 1476 # number of demand (read+write) hits 241system.cpu.icache.overall_hits::cpu.inst 1476 # number of overall hits 242system.cpu.icache.overall_hits::total 1476 # number of overall hits 243system.cpu.icache.ReadReq_misses::cpu.inst 122 # number of ReadReq misses 244system.cpu.icache.ReadReq_misses::total 122 # number of ReadReq misses 245system.cpu.icache.demand_misses::cpu.inst 122 # number of demand (read+write) misses 246system.cpu.icache.demand_misses::total 122 # number of demand (read+write) misses 247system.cpu.icache.overall_misses::cpu.inst 122 # number of overall misses 248system.cpu.icache.overall_misses::total 122 # number of overall misses 249system.cpu.icache.ReadReq_miss_latency::cpu.inst 7686500 # number of ReadReq miss cycles 250system.cpu.icache.ReadReq_miss_latency::total 7686500 # number of ReadReq miss cycles 251system.cpu.icache.demand_miss_latency::cpu.inst 7686500 # number of demand (read+write) miss cycles 252system.cpu.icache.demand_miss_latency::total 7686500 # number of demand (read+write) miss cycles 253system.cpu.icache.overall_miss_latency::cpu.inst 7686500 # number of overall miss cycles 254system.cpu.icache.overall_miss_latency::total 7686500 # number of overall miss cycles 255system.cpu.icache.ReadReq_accesses::cpu.inst 1598 # number of ReadReq accesses(hits+misses) 256system.cpu.icache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) 257system.cpu.icache.demand_accesses::cpu.inst 1598 # number of demand (read+write) accesses 258system.cpu.icache.demand_accesses::total 1598 # number of demand (read+write) accesses 259system.cpu.icache.overall_accesses::cpu.inst 1598 # number of overall (read+write) accesses 260system.cpu.icache.overall_accesses::total 1598 # number of overall (read+write) accesses 261system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076345 # miss rate for ReadReq accesses 262system.cpu.icache.ReadReq_miss_rate::total 0.076345 # miss rate for ReadReq accesses 263system.cpu.icache.demand_miss_rate::cpu.inst 0.076345 # miss rate for demand accesses 264system.cpu.icache.demand_miss_rate::total 0.076345 # miss rate for demand accesses 265system.cpu.icache.overall_miss_rate::cpu.inst 0.076345 # miss rate for overall accesses 266system.cpu.icache.overall_miss_rate::total 0.076345 # miss rate for overall accesses 267system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63004.098361 # average ReadReq miss latency 268system.cpu.icache.ReadReq_avg_miss_latency::total 63004.098361 # average ReadReq miss latency 269system.cpu.icache.demand_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency 270system.cpu.icache.demand_avg_miss_latency::total 63004.098361 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total 63004.098361 # average overall miss latency 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses 280system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses 281system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses 282system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses 283system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses 284system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses 285system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles 286system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles 287system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles 288system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles 289system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles 290system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles 291system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses 292system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses 293system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses 294system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses 295system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses 296system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses 297system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency 298system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency 299system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency 300system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency 301system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency 302system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency 303system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 304system.cpu.l2cache.tags.replacements 0 # number of replacements 305system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use 306system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 307system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks. 308system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks. 309system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 310system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor 312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy 314system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy 315system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id 316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id 318system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id 319system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses 320system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses 321system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 322system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 323system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 324system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 326system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 327system.cpu.l2cache.overall_hits::total 1 # number of overall hits 328system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses 329system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses 330system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses 331system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses 332system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses 333system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses 334system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses 337system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses 338system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses 339system.cpu.l2cache.overall_misses::total 152 # number of overall misses 340system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles 342system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles 343system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles 344system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles 345system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles 352system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) 353system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) 354system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses) 355system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses) 356system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses) 357system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses) 358system.cpu.l2cache.demand_accesses::cpu.inst 122 # number of demand (read+write) accesses 359system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses 361system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses 364system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 365system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 366system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 367system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 368system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses 369system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses 370system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::total 0.993464 # miss rate for demand accesses 373system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses 376system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 377system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 378system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency 379system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency 380system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 381system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 382system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency 383system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 384system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency 388system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 392system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 394system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses 395system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses 396system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses 397system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses 398system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses 399system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses 400system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses 401system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses 404system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses 405system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses 406system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles 407system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles 408system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles 409system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles 410system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles 411system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles 412system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles 418system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 419system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 420system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 421system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 422system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses 423system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses 430system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 431system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 432system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency 433system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency 434system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 435system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency 442system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter. 443system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 444system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 445system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 446system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 447system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 448system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 449system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution 451system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution 454system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes) 455system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes) 456system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes) 457system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes) 459system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes) 460system.cpu.toL2Bus.snoops 0 # Total snoops (count) 461system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 462system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 469system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 470system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram 473system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks) 474system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 475system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks) 476system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 477system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks) 478system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 479system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter. 480system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 481system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 482system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 483system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 484system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 485system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states 486system.membus.trans_dist::ReadResp 134 # Transaction distribution 487system.membus.trans_dist::ReadExReq 18 # Transaction distribution 488system.membus.trans_dist::ReadExResp 18 # Transaction distribution 489system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution 490system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes) 491system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes) 492system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes) 493system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes) 494system.membus.snoops 0 # Total snoops (count) 495system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 496system.membus.snoop_fanout::samples 152 # Request fanout histogram 497system.membus.snoop_fanout::mean 0 # Request fanout histogram 498system.membus.snoop_fanout::stdev 0 # Request fanout histogram 499system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 500system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram 501system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 502system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 503system.membus.snoop_fanout::min_value 0 # Request fanout histogram 504system.membus.snoop_fanout::max_value 0 # Request fanout histogram 505system.membus.snoop_fanout::total 152 # Request fanout histogram 506system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks) 507system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 508system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks) 509system.membus.respLayer1.utilization 6.6 # Layer utilization (%) 510 511---------- End Simulation Statistics ---------- 512