simout revision 11731:c473ca7cc650
111986Sandreas.sandberg@arm.comRedirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout 211986Sandreas.sandberg@arm.comRedirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr 311986Sandreas.sandberg@arm.comgem5 Simulator System. http://gem5.org 411986Sandreas.sandberg@arm.comgem5 is copyrighted software; use the --copyright option for details. 511986Sandreas.sandberg@arm.com 611986Sandreas.sandberg@arm.comgem5 compiled Nov 30 2016 14:33:35 711986Sandreas.sandberg@arm.comgem5 started Nov 30 2016 16:18:29 811986Sandreas.sandberg@arm.comgem5 executing on zizzer, pid 34060 911986Sandreas.sandberg@arm.comcommand line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby 1011986Sandreas.sandberg@arm.com 1111986Sandreas.sandberg@arm.comGlobal frequency set at 1000000000 ticks per second 1211986Sandreas.sandberg@arm.cominfo: Entering event queue @ 0. Starting simulation... 1311986Sandreas.sandberg@arm.cominfo: Increasing stack size by one page. 1411986Sandreas.sandberg@arm.comHello world! 1511986Sandreas.sandberg@arm.comExiting @ tick 27947 because target called exit() 1611986Sandreas.sandberg@arm.com