stats.txt revision 11731
111731Sjason@lowepower.com 211731Sjason@lowepower.com---------- Begin Simulation Statistics ---------- 311731Sjason@lowepower.comsim_seconds 0.000008 # Number of seconds simulated 411731Sjason@lowepower.comsim_ticks 7939500 # Number of ticks simulated 511731Sjason@lowepower.comfinal_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611731Sjason@lowepower.comsim_freq 1000000000000 # Frequency of simulated ticks 711731Sjason@lowepower.comhost_inst_rate 22942 # Simulator instruction rate (inst/s) 811731Sjason@lowepower.comhost_op_rate 22935 # Simulator op (including micro ops) rate (op/s) 911731Sjason@lowepower.comhost_tick_rate 114711600 # Simulator tick rate (ticks/s) 1011731Sjason@lowepower.comhost_mem_usage 232976 # Number of bytes of host memory used 1111731Sjason@lowepower.comhost_seconds 0.07 # Real time elapsed on the host 1211731Sjason@lowepower.comsim_insts 1587 # Number of instructions simulated 1311731Sjason@lowepower.comsim_ops 1587 # Number of ops (including micro ops) simulated 1411731Sjason@lowepower.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511731Sjason@lowepower.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611731Sjason@lowepower.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 1711731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory 1811731Sjason@lowepower.comsystem.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory 1911731Sjason@lowepower.comsystem.physmem.bytes_read::total 11648 # Number of bytes read from this memory 2011731Sjason@lowepower.comsystem.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory 2111731Sjason@lowepower.comsystem.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory 2211731Sjason@lowepower.comsystem.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory 2311731Sjason@lowepower.comsystem.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory 2411731Sjason@lowepower.comsystem.physmem.num_reads::total 182 # Number of read requests responded to by this memory 2511731Sjason@lowepower.comsystem.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s) 2611731Sjason@lowepower.comsystem.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s) 2711731Sjason@lowepower.comsystem.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s) 2811731Sjason@lowepower.comsystem.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s) 2911731Sjason@lowepower.comsystem.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s) 3011731Sjason@lowepower.comsystem.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s) 3111731Sjason@lowepower.comsystem.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s) 3211731Sjason@lowepower.comsystem.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s) 3311731Sjason@lowepower.comsystem.physmem.readReqs 184 # Number of read requests accepted 3411731Sjason@lowepower.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511731Sjason@lowepower.comsystem.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue 3611731Sjason@lowepower.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711731Sjason@lowepower.comsystem.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM 3811731Sjason@lowepower.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911731Sjason@lowepower.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011731Sjason@lowepower.comsystem.physmem.bytesReadSys 11776 # Total read bytes from the system interface side 4111731Sjason@lowepower.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211731Sjason@lowepower.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311731Sjason@lowepower.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411731Sjason@lowepower.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::0 93 # Per bank write bursts 4611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::1 62 # Per bank write bursts 4711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::2 18 # Per bank write bursts 4811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::3 9 # Per bank write bursts 4911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::4 0 # Per bank write bursts 5011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::5 0 # Per bank write bursts 5111731Sjason@lowepower.comsystem.physmem.perBankRdBursts::6 0 # Per bank write bursts 5211731Sjason@lowepower.comsystem.physmem.perBankRdBursts::7 0 # Per bank write bursts 5311731Sjason@lowepower.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 5411731Sjason@lowepower.comsystem.physmem.perBankRdBursts::9 0 # Per bank write bursts 5511731Sjason@lowepower.comsystem.physmem.perBankRdBursts::10 0 # Per bank write bursts 5611731Sjason@lowepower.comsystem.physmem.perBankRdBursts::11 0 # Per bank write bursts 5711731Sjason@lowepower.comsystem.physmem.perBankRdBursts::12 0 # Per bank write bursts 5811731Sjason@lowepower.comsystem.physmem.perBankRdBursts::13 0 # Per bank write bursts 5911731Sjason@lowepower.comsystem.physmem.perBankRdBursts::14 0 # Per bank write bursts 6011731Sjason@lowepower.comsystem.physmem.perBankRdBursts::15 0 # Per bank write bursts 6111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711731Sjason@lowepower.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811731Sjason@lowepower.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911731Sjason@lowepower.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011731Sjason@lowepower.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111731Sjason@lowepower.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211731Sjason@lowepower.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311731Sjason@lowepower.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411731Sjason@lowepower.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511731Sjason@lowepower.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611731Sjason@lowepower.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711731Sjason@lowepower.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811731Sjason@lowepower.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911731Sjason@lowepower.comsystem.physmem.totGap 7854500 # Total gap between requests 8011731Sjason@lowepower.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111731Sjason@lowepower.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211731Sjason@lowepower.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311731Sjason@lowepower.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411731Sjason@lowepower.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511731Sjason@lowepower.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611731Sjason@lowepower.comsystem.physmem.readPktSize::6 184 # Read request sizes (log2) 8711731Sjason@lowepower.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811731Sjason@lowepower.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911731Sjason@lowepower.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011731Sjason@lowepower.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111731Sjason@lowepower.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211731Sjason@lowepower.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311731Sjason@lowepower.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see 9511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see 9611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see 9711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see 9811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 9911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611731Sjason@lowepower.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711731Sjason@lowepower.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811731Sjason@lowepower.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911731Sjason@lowepower.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011731Sjason@lowepower.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111731Sjason@lowepower.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211731Sjason@lowepower.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311731Sjason@lowepower.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411731Sjason@lowepower.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511731Sjason@lowepower.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011731Sjason@lowepower.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111731Sjason@lowepower.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211731Sjason@lowepower.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311731Sjason@lowepower.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411731Sjason@lowepower.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511731Sjason@lowepower.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611731Sjason@lowepower.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711731Sjason@lowepower.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811731Sjason@lowepower.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911731Sjason@lowepower.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011731Sjason@lowepower.comsystem.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation 19111731Sjason@lowepower.comsystem.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation 19211731Sjason@lowepower.comsystem.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation 19311731Sjason@lowepower.comsystem.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation 19411731Sjason@lowepower.comsystem.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation 19511731Sjason@lowepower.comsystem.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation 19611731Sjason@lowepower.comsystem.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation 19711731Sjason@lowepower.comsystem.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation 19811731Sjason@lowepower.comsystem.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation 19911731Sjason@lowepower.comsystem.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation 20011731Sjason@lowepower.comsystem.physmem.totQLat 1405000 # Total ticks spent queuing 20111731Sjason@lowepower.comsystem.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM 20211731Sjason@lowepower.comsystem.physmem.totBusLat 910000 # Total ticks spent in databus transfers 20311731Sjason@lowepower.comsystem.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst 20411731Sjason@lowepower.comsystem.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst 20511731Sjason@lowepower.comsystem.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst 20611731Sjason@lowepower.comsystem.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s 20711731Sjason@lowepower.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 20811731Sjason@lowepower.comsystem.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s 20911731Sjason@lowepower.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21011731Sjason@lowepower.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21111731Sjason@lowepower.comsystem.physmem.busUtil 11.46 # Data bus utilization in percentage 21211731Sjason@lowepower.comsystem.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads 21311731Sjason@lowepower.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21411731Sjason@lowepower.comsystem.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing 21511731Sjason@lowepower.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21611731Sjason@lowepower.comsystem.physmem.readRowHits 169 # Number of row buffer hits during reads 21711731Sjason@lowepower.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 21811731Sjason@lowepower.comsystem.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads 21911731Sjason@lowepower.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22011731Sjason@lowepower.comsystem.physmem.avgGap 42687.50 # Average gap between requests 22111731Sjason@lowepower.comsystem.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined 22211731Sjason@lowepower.comsystem.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ) 22311731Sjason@lowepower.comsystem.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) 22411731Sjason@lowepower.comsystem.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ) 22511731Sjason@lowepower.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22611731Sjason@lowepower.comsystem.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 22711731Sjason@lowepower.comsystem.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ) 22811731Sjason@lowepower.comsystem.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ) 22911731Sjason@lowepower.comsystem.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ) 23011731Sjason@lowepower.comsystem.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) 23111731Sjason@lowepower.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23211731Sjason@lowepower.comsystem.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ) 23311731Sjason@lowepower.comsystem.physmem_0.averagePower 711.322044 # Core power per rank (mW) 23411731Sjason@lowepower.comsystem.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank 23511731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 23611731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::REF 139500 # Time in different power states 23711731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 23811731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23911731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states 24011731Sjason@lowepower.comsystem.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states 24111731Sjason@lowepower.comsystem.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) 24211731Sjason@lowepower.comsystem.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) 24311731Sjason@lowepower.comsystem.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) 24411731Sjason@lowepower.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24511731Sjason@lowepower.comsystem.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) 24611731Sjason@lowepower.comsystem.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) 24711731Sjason@lowepower.comsystem.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ) 24811731Sjason@lowepower.comsystem.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) 24911731Sjason@lowepower.comsystem.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) 25011731Sjason@lowepower.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25111731Sjason@lowepower.comsystem.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ) 25211731Sjason@lowepower.comsystem.physmem_1.averagePower 462.726424 # Core power per rank (mW) 25311731Sjason@lowepower.comsystem.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank 25411731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states 25511731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::REF 153250 # Time in different power states 25611731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 25711731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25811731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT 0 # Time in different power states 25911731Sjason@lowepower.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 26011731Sjason@lowepower.comsystem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 26111731Sjason@lowepower.comsystem.cpu.branchPred.lookups 1252 # Number of BP lookups 26211731Sjason@lowepower.comsystem.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted 26311731Sjason@lowepower.comsystem.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect 26411731Sjason@lowepower.comsystem.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups 26511731Sjason@lowepower.comsystem.cpu.branchPred.BTBHits 300 # Number of BTB hits 26611731Sjason@lowepower.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26711731Sjason@lowepower.comsystem.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage 26811731Sjason@lowepower.comsystem.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 26911731Sjason@lowepower.comsystem.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 27011731Sjason@lowepower.comsystem.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. 27111731Sjason@lowepower.comsystem.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 27211731Sjason@lowepower.comsystem.cpu.branchPred.indirectMisses 228 # Number of indirect misses. 27311731Sjason@lowepower.comsystem.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. 27411731Sjason@lowepower.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27511731Sjason@lowepower.comsystem.cpu.dtb.read_hits 0 # DTB read hits 27611731Sjason@lowepower.comsystem.cpu.dtb.read_misses 0 # DTB read misses 27711731Sjason@lowepower.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 27811731Sjason@lowepower.comsystem.cpu.dtb.write_hits 0 # DTB write hits 27911731Sjason@lowepower.comsystem.cpu.dtb.write_misses 0 # DTB write misses 28011731Sjason@lowepower.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 28111731Sjason@lowepower.comsystem.cpu.dtb.hits 0 # DTB hits 28211731Sjason@lowepower.comsystem.cpu.dtb.misses 0 # DTB misses 28311731Sjason@lowepower.comsystem.cpu.dtb.accesses 0 # DTB accesses 28411731Sjason@lowepower.comsystem.cpu.itb.read_hits 0 # DTB read hits 28511731Sjason@lowepower.comsystem.cpu.itb.read_misses 0 # DTB read misses 28611731Sjason@lowepower.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 28711731Sjason@lowepower.comsystem.cpu.itb.write_hits 0 # DTB write hits 28811731Sjason@lowepower.comsystem.cpu.itb.write_misses 0 # DTB write misses 28911731Sjason@lowepower.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 29011731Sjason@lowepower.comsystem.cpu.itb.hits 0 # DTB hits 29111731Sjason@lowepower.comsystem.cpu.itb.misses 0 # DTB misses 29211731Sjason@lowepower.comsystem.cpu.itb.accesses 0 # DTB accesses 29311731Sjason@lowepower.comsystem.cpu.workload.num_syscalls 9 # Number of system calls 29411731Sjason@lowepower.comsystem.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states 29511731Sjason@lowepower.comsystem.cpu.numCycles 15880 # number of cpu cycles simulated 29611731Sjason@lowepower.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 29711731Sjason@lowepower.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29811731Sjason@lowepower.comsystem.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss 29911731Sjason@lowepower.comsystem.cpu.fetch.Insts 4970 # Number of instructions fetch has processed 30011731Sjason@lowepower.comsystem.cpu.fetch.Branches 1252 # Number of branches that fetch encountered 30111731Sjason@lowepower.comsystem.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken 30211731Sjason@lowepower.comsystem.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked 30311731Sjason@lowepower.comsystem.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing 30411731Sjason@lowepower.comsystem.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30511731Sjason@lowepower.comsystem.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps 30611731Sjason@lowepower.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR 30711731Sjason@lowepower.comsystem.cpu.fetch.CacheLines 803 # Number of cache lines fetched 30811731Sjason@lowepower.comsystem.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed 30911731Sjason@lowepower.comsystem.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) 31011731Sjason@lowepower.comsystem.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) 31111731Sjason@lowepower.comsystem.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) 31211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) 31411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) 31511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) 31611731Sjason@lowepower.comsystem.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) 31711731Sjason@lowepower.comsystem.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) 31811731Sjason@lowepower.comsystem.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) 31911731Sjason@lowepower.comsystem.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) 32011731Sjason@lowepower.comsystem.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) 32111731Sjason@lowepower.comsystem.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) 32211731Sjason@lowepower.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 32311731Sjason@lowepower.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 32411731Sjason@lowepower.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32511731Sjason@lowepower.comsystem.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) 32611731Sjason@lowepower.comsystem.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle 32711731Sjason@lowepower.comsystem.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle 32811731Sjason@lowepower.comsystem.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle 32911731Sjason@lowepower.comsystem.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked 33011731Sjason@lowepower.comsystem.cpu.decode.RunCycles 756 # Number of cycles decode is running 33111731Sjason@lowepower.comsystem.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking 33211731Sjason@lowepower.comsystem.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing 33311731Sjason@lowepower.comsystem.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch 33411731Sjason@lowepower.comsystem.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction 33511731Sjason@lowepower.comsystem.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode 33611731Sjason@lowepower.comsystem.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode 33711731Sjason@lowepower.comsystem.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing 33811731Sjason@lowepower.comsystem.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle 33911731Sjason@lowepower.comsystem.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking 34011731Sjason@lowepower.comsystem.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst 34111731Sjason@lowepower.comsystem.cpu.rename.RunCycles 672 # Number of cycles rename is running 34211731Sjason@lowepower.comsystem.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking 34311731Sjason@lowepower.comsystem.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename 34411731Sjason@lowepower.comsystem.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full 34511731Sjason@lowepower.comsystem.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed 34611731Sjason@lowepower.comsystem.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made 34711731Sjason@lowepower.comsystem.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups 34811731Sjason@lowepower.comsystem.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed 34911731Sjason@lowepower.comsystem.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing 35011731Sjason@lowepower.comsystem.cpu.rename.serializingInsts 16 # count of serializing insts renamed 35111731Sjason@lowepower.comsystem.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed 35211731Sjason@lowepower.comsystem.cpu.rename.skidInsts 82 # count of insts added to the skid buffer 35311731Sjason@lowepower.comsystem.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. 35411731Sjason@lowepower.comsystem.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. 35511731Sjason@lowepower.comsystem.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. 35611731Sjason@lowepower.comsystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 35711731Sjason@lowepower.comsystem.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) 35811731Sjason@lowepower.comsystem.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ 35911731Sjason@lowepower.comsystem.cpu.iq.iqInstsIssued 2694 # Number of instructions issued 36011731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued 36111731Sjason@lowepower.comsystem.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling 36211731Sjason@lowepower.comsystem.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph 36311731Sjason@lowepower.comsystem.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed 36411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle 36511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle 36611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle 36711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 36811731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle 36911731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle 37011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle 37111731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle 37211731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle 37311731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle 37411731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle 37511731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle 37611731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle 37711731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 37811731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 37911731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38011731Sjason@lowepower.comsystem.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle 38111731Sjason@lowepower.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38211731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available 38311731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available 38411731Sjason@lowepower.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available 38511731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available 38611731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available 38711731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available 38811731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available 38911731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available 39011731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available 39111731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available 39211731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available 39311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available 39411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available 39511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available 39611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available 39711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available 39811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available 39911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available 40011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available 40111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available 40211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available 40311731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available 40411731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available 40511731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available 40611731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available 40711731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available 40811731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available 40911731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available 41011731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available 41111731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available 41211731Sjason@lowepower.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available 41311731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available 41411731Sjason@lowepower.comsystem.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available 41511731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 41611731Sjason@lowepower.comsystem.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 41711731Sjason@lowepower.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 41811731Sjason@lowepower.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 41911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued 42011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued 42111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued 42211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued 42311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued 42411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued 42511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued 42611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued 42711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued 42811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued 42911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued 43011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued 43111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued 43211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued 43311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued 43411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued 43511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued 43611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued 43711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued 43811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued 43911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued 44011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued 44111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued 44211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued 44311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued 44411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued 44511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued 44611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued 44711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued 44811731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued 44911731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued 45011731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued 45111731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued 45211731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued 45311731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 45411731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 45511731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 45611731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45711731Sjason@lowepower.comsystem.cpu.iq.FU_type_0::total 2694 # Type of FU issued 45811731Sjason@lowepower.comsystem.cpu.iq.rate 0.169647 # Inst issue rate 45911731Sjason@lowepower.comsystem.cpu.iq.fu_busy_cnt 70 # FU busy when requested 46011731Sjason@lowepower.comsystem.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) 46111731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads 46211731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes 46311731Sjason@lowepower.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses 46411731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 46511731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 46611731Sjason@lowepower.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 46711731Sjason@lowepower.comsystem.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses 46811731Sjason@lowepower.comsystem.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 46911731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores 47011731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 47111731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed 47211731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 47311731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations 47411731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed 47511731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 47611731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 47711731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 47811731Sjason@lowepower.comsystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 47911731Sjason@lowepower.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 48011731Sjason@lowepower.comsystem.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing 48111731Sjason@lowepower.comsystem.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking 48211731Sjason@lowepower.comsystem.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking 48311731Sjason@lowepower.comsystem.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ 48411731Sjason@lowepower.comsystem.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch 48511731Sjason@lowepower.comsystem.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions 48611731Sjason@lowepower.comsystem.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions 48711731Sjason@lowepower.comsystem.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions 48811731Sjason@lowepower.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 48911731Sjason@lowepower.comsystem.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 49011731Sjason@lowepower.comsystem.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations 49111731Sjason@lowepower.comsystem.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly 49211731Sjason@lowepower.comsystem.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly 49311731Sjason@lowepower.comsystem.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute 49411731Sjason@lowepower.comsystem.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions 49511731Sjason@lowepower.comsystem.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed 49611731Sjason@lowepower.comsystem.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute 49711731Sjason@lowepower.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 49811731Sjason@lowepower.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 49911731Sjason@lowepower.comsystem.cpu.iew.exec_refs 847 # number of memory reference insts executed 50011731Sjason@lowepower.comsystem.cpu.iew.exec_branches 563 # Number of branches executed 50111731Sjason@lowepower.comsystem.cpu.iew.exec_stores 375 # Number of stores executed 50211731Sjason@lowepower.comsystem.cpu.iew.exec_rate 0.154408 # Inst execution rate 50311731Sjason@lowepower.comsystem.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit 50411731Sjason@lowepower.comsystem.cpu.iew.wb_count 2310 # cumulative count of insts written-back 50511731Sjason@lowepower.comsystem.cpu.iew.wb_producers 793 # num instructions producing a value 50611731Sjason@lowepower.comsystem.cpu.iew.wb_consumers 1130 # num instructions consuming a value 50711731Sjason@lowepower.comsystem.cpu.iew.wb_rate 0.145466 # insts written-back per cycle 50811731Sjason@lowepower.comsystem.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back 50911731Sjason@lowepower.comsystem.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit 51011731Sjason@lowepower.comsystem.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 51111731Sjason@lowepower.comsystem.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted 51211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle 51311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle 51411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle 51511731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51611731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle 51711731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle 51811731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle 51911731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle 52011731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle 52111731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle 52211731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle 52311731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle 52411731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle 52511731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 52611731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 52711731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52811731Sjason@lowepower.comsystem.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle 52911731Sjason@lowepower.comsystem.cpu.commit.committedInsts 1587 # Number of instructions committed 53011731Sjason@lowepower.comsystem.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed 53111731Sjason@lowepower.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 53211731Sjason@lowepower.comsystem.cpu.commit.refs 568 # Number of memory references committed 53311731Sjason@lowepower.comsystem.cpu.commit.loads 289 # Number of loads committed 53411731Sjason@lowepower.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 53511731Sjason@lowepower.comsystem.cpu.commit.branches 373 # Number of branches committed 53611731Sjason@lowepower.comsystem.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 53711731Sjason@lowepower.comsystem.cpu.commit.int_insts 1587 # Number of committed integer instructions. 53811731Sjason@lowepower.comsystem.cpu.commit.function_calls 142 # Number of function calls committed. 53911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 54011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction 54111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction 54211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction 54311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction 54411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction 54511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction 54611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction 54711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction 54811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction 54911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction 55011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction 55111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction 55211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction 55311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction 55411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction 55511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction 55611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction 55711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction 55811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction 55911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction 56011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction 56111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction 56211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction 56311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction 56411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction 56511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction 56611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction 56711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction 56811731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction 56911731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction 57011731Sjason@lowepower.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction 57111731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction 57211731Sjason@lowepower.comsystem.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction 57311731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 57411731Sjason@lowepower.comsystem.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 57511731Sjason@lowepower.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 57611731Sjason@lowepower.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 57711731Sjason@lowepower.comsystem.cpu.commit.op_class_0::total 1587 # Class of committed instruction 57811731Sjason@lowepower.comsystem.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached 57911731Sjason@lowepower.comsystem.cpu.rob.rob_reads 7041 # The number of ROB reads 58011731Sjason@lowepower.comsystem.cpu.rob.rob_writes 6340 # The number of ROB writes 58111731Sjason@lowepower.comsystem.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself 58211731Sjason@lowepower.comsystem.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling 58311731Sjason@lowepower.comsystem.cpu.committedInsts 1587 # Number of Instructions Simulated 58411731Sjason@lowepower.comsystem.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated 58511731Sjason@lowepower.comsystem.cpu.cpi 10.006301 # CPI: Cycles Per Instruction 58611731Sjason@lowepower.comsystem.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads 58711731Sjason@lowepower.comsystem.cpu.ipc 0.099937 # IPC: Instructions Per Cycle 58811731Sjason@lowepower.comsystem.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads 58911731Sjason@lowepower.comsystem.cpu.int_regfile_reads 3068 # number of integer regfile reads 59011731Sjason@lowepower.comsystem.cpu.int_regfile_writes 1663 # number of integer regfile writes 59111731Sjason@lowepower.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 59211731Sjason@lowepower.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 59311731Sjason@lowepower.comsystem.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use 59411731Sjason@lowepower.comsystem.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. 59511731Sjason@lowepower.comsystem.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. 59611731Sjason@lowepower.comsystem.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. 59711731Sjason@lowepower.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59811731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor 59911731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy 60011731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy 60111731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id 60211731Sjason@lowepower.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 60311731Sjason@lowepower.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id 60411731Sjason@lowepower.comsystem.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses 60511731Sjason@lowepower.comsystem.cpu.dcache.tags.data_accesses 1497 # Number of data accesses 60611731Sjason@lowepower.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 60711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits 60811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits 60911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits 61011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits 61111731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits 61211731Sjason@lowepower.comsystem.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits 61311731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits 61411731Sjason@lowepower.comsystem.cpu.dcache.overall_hits::total 626 # number of overall hits 61511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses 61611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses 61711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses 61811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses 61911731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses 62011731Sjason@lowepower.comsystem.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses 62111731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses 62211731Sjason@lowepower.comsystem.cpu.dcache.overall_misses::total 106 # number of overall misses 62311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles 62411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles 62511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles 62611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles 62711731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles 62811731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles 62911731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles 63011731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles 63111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) 63211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) 63311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) 63411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) 63511731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses 63611731Sjason@lowepower.comsystem.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses 63711731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses 63811731Sjason@lowepower.comsystem.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses 63911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses 64011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses 64111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses 64211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses 64311731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses 64411731Sjason@lowepower.comsystem.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses 64511731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses 64611731Sjason@lowepower.comsystem.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses 64711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency 64811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency 64911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency 65011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency 65111731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 65211731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency 65311731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency 65411731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency 65511731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 65611731Sjason@lowepower.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65711731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 65811731Sjason@lowepower.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 65911731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 66011731Sjason@lowepower.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66111731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 66211731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 66311731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits 66411731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits 66511731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits 66611731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 66711731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits 66811731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits 66911731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses 67011731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses 67111731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses 67211731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses 67311731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses 67411731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses 67511731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses 67611731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses 67711731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles 67811731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles 67911731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles 68011731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles 68111731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles 68211731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles 68311731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles 68411731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles 68511731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses 68611731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses 68711731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses 68811731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses 68911731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses 69011731Sjason@lowepower.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses 69111731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses 69211731Sjason@lowepower.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses 69311731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency 69411731Sjason@lowepower.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency 69511731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency 69611731Sjason@lowepower.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency 69711731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 69811731Sjason@lowepower.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency 69911731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency 70011731Sjason@lowepower.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency 70111731Sjason@lowepower.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 70211731Sjason@lowepower.comsystem.cpu.icache.tags.replacements 0 # number of replacements 70311731Sjason@lowepower.comsystem.cpu.icache.tags.tagsinuse 76.387250 # Cycle average of tags in use 70411731Sjason@lowepower.comsystem.cpu.icache.tags.total_refs 579 # Total number of references to valid blocks. 70511731Sjason@lowepower.comsystem.cpu.icache.tags.sampled_refs 151 # Sample count of references to valid blocks. 70611731Sjason@lowepower.comsystem.cpu.icache.tags.avg_refs 3.834437 # Average number of references to valid blocks. 70711731Sjason@lowepower.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70811731Sjason@lowepower.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 76.387250 # Average occupied blocks per requestor 70911731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.037298 # Average percentage of cache occupancy 71011731Sjason@lowepower.comsystem.cpu.icache.tags.occ_percent::total 0.037298 # Average percentage of cache occupancy 71111731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 151 # Occupied blocks per task id 71211731Sjason@lowepower.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 71311731Sjason@lowepower.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id 71411731Sjason@lowepower.comsystem.cpu.icache.tags.tag_accesses 1753 # Number of tag accesses 71511731Sjason@lowepower.comsystem.cpu.icache.tags.data_accesses 1753 # Number of data accesses 71611731Sjason@lowepower.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 71711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::cpu.inst 579 # number of ReadReq hits 71811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_hits::total 579 # number of ReadReq hits 71911731Sjason@lowepower.comsystem.cpu.icache.demand_hits::cpu.inst 579 # number of demand (read+write) hits 72011731Sjason@lowepower.comsystem.cpu.icache.demand_hits::total 579 # number of demand (read+write) hits 72111731Sjason@lowepower.comsystem.cpu.icache.overall_hits::cpu.inst 579 # number of overall hits 72211731Sjason@lowepower.comsystem.cpu.icache.overall_hits::total 579 # number of overall hits 72311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::cpu.inst 222 # number of ReadReq misses 72411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_misses::total 222 # number of ReadReq misses 72511731Sjason@lowepower.comsystem.cpu.icache.demand_misses::cpu.inst 222 # number of demand (read+write) misses 72611731Sjason@lowepower.comsystem.cpu.icache.demand_misses::total 222 # number of demand (read+write) misses 72711731Sjason@lowepower.comsystem.cpu.icache.overall_misses::cpu.inst 222 # number of overall misses 72811731Sjason@lowepower.comsystem.cpu.icache.overall_misses::total 222 # number of overall misses 72911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16076000 # number of ReadReq miss cycles 73011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_latency::total 16076000 # number of ReadReq miss cycles 73111731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16076000 # number of demand (read+write) miss cycles 73211731Sjason@lowepower.comsystem.cpu.icache.demand_miss_latency::total 16076000 # number of demand (read+write) miss cycles 73311731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16076000 # number of overall miss cycles 73411731Sjason@lowepower.comsystem.cpu.icache.overall_miss_latency::total 16076000 # number of overall miss cycles 73511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses) 73611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_accesses::total 801 # number of ReadReq accesses(hits+misses) 73711731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 73811731Sjason@lowepower.comsystem.cpu.icache.demand_accesses::total 801 # number of demand (read+write) accesses 73911731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 74011731Sjason@lowepower.comsystem.cpu.icache.overall_accesses::total 801 # number of overall (read+write) accesses 74111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.277154 # miss rate for ReadReq accesses 74211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_miss_rate::total 0.277154 # miss rate for ReadReq accesses 74311731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.277154 # miss rate for demand accesses 74411731Sjason@lowepower.comsystem.cpu.icache.demand_miss_rate::total 0.277154 # miss rate for demand accesses 74511731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.277154 # miss rate for overall accesses 74611731Sjason@lowepower.comsystem.cpu.icache.overall_miss_rate::total 0.277154 # miss rate for overall accesses 74711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72414.414414 # average ReadReq miss latency 74811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 72414.414414 # average ReadReq miss latency 74911731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency 75011731Sjason@lowepower.comsystem.cpu.icache.demand_avg_miss_latency::total 72414.414414 # average overall miss latency 75111731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency 75211731Sjason@lowepower.comsystem.cpu.icache.overall_avg_miss_latency::total 72414.414414 # average overall miss latency 75311731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_mshrs 447 # number of cycles access was blocked 75411731Sjason@lowepower.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75511731Sjason@lowepower.comsystem.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 75611731Sjason@lowepower.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 75711731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 89.400000 # average number of cycles each access was blocked 75811731Sjason@lowepower.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 75911731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 76011731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 76111731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 76211731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 76311731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 76411731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits 76511731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 153 # number of ReadReq MSHR misses 76611731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses 76711731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 153 # number of demand (read+write) MSHR misses 76811731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_misses::total 153 # number of demand (read+write) MSHR misses 76911731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 153 # number of overall MSHR misses 77011731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_misses::total 153 # number of overall MSHR misses 77111731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11858500 # number of ReadReq MSHR miss cycles 77211731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11858500 # number of ReadReq MSHR miss cycles 77311731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11858500 # number of demand (read+write) MSHR miss cycles 77411731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_latency::total 11858500 # number of demand (read+write) MSHR miss cycles 77511731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11858500 # number of overall MSHR miss cycles 77611731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_latency::total 11858500 # number of overall MSHR miss cycles 77711731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for ReadReq accesses 77811731Sjason@lowepower.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.191011 # mshr miss rate for ReadReq accesses 77911731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for demand accesses 78011731Sjason@lowepower.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.191011 # mshr miss rate for demand accesses 78111731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for overall accesses 78211731Sjason@lowepower.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.191011 # mshr miss rate for overall accesses 78311731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77506.535948 # average ReadReq mshr miss latency 78411731Sjason@lowepower.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77506.535948 # average ReadReq mshr miss latency 78511731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency 78611731Sjason@lowepower.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency 78711731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency 78811731Sjason@lowepower.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency 78911731Sjason@lowepower.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 79011731Sjason@lowepower.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 79111731Sjason@lowepower.comsystem.cpu.l2cache.tags.tagsinuse 99.069725 # Cycle average of tags in use 79211731Sjason@lowepower.comsystem.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 79311731Sjason@lowepower.comsystem.cpu.l2cache.tags.sampled_refs 182 # Sample count of references to valid blocks. 79411731Sjason@lowepower.comsystem.cpu.l2cache.tags.avg_refs 0.010989 # Average number of references to valid blocks. 79511731Sjason@lowepower.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79611731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 75.716364 # Average occupied blocks per requestor 79711731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 23.353361 # Average occupied blocks per requestor 79811731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.002311 # Average percentage of cache occupancy 79911731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.000713 # Average percentage of cache occupancy 80011731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_percent::total 0.003023 # Average percentage of cache occupancy 80111731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 182 # Occupied blocks per task id 80211731Sjason@lowepower.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 80311731Sjason@lowepower.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.005554 # Percentage of cache occupancy per task id 80411731Sjason@lowepower.comsystem.cpu.l2cache.tags.tag_accesses 1678 # Number of tag accesses 80511731Sjason@lowepower.comsystem.cpu.l2cache.tags.data_accesses 1678 # Number of data accesses 80611731Sjason@lowepower.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 80711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 80811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 80911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 81011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 81111731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 81211731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 81311731Sjason@lowepower.comsystem.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 81411731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 81511731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 81611731Sjason@lowepower.comsystem.cpu.l2cache.overall_hits::total 2 # number of overall hits 81711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses 81811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses 81911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 152 # number of ReadCleanReq misses 82011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_misses::total 152 # number of ReadCleanReq misses 82111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses 82211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses 82311731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.inst 152 # number of demand (read+write) misses 82411731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::cpu.data 33 # number of demand (read+write) misses 82511731Sjason@lowepower.comsystem.cpu.l2cache.demand_misses::total 185 # number of demand (read+write) misses 82611731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.inst 152 # number of overall misses 82711731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::cpu.data 33 # number of overall misses 82811731Sjason@lowepower.comsystem.cpu.l2cache.overall_misses::total 185 # number of overall misses 82911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404500 # number of ReadExReq miss cycles 83011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1404500 # number of ReadExReq miss cycles 83111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11620000 # number of ReadCleanReq miss cycles 83211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 11620000 # number of ReadCleanReq miss cycles 83311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1106000 # number of ReadSharedReq miss cycles 83411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 1106000 # number of ReadSharedReq miss cycles 83511731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11620000 # number of demand (read+write) miss cycles 83611731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 2510500 # number of demand (read+write) miss cycles 83711731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_latency::total 14130500 # number of demand (read+write) miss cycles 83811731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11620000 # number of overall miss cycles 83911731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 2510500 # number of overall miss cycles 84011731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_latency::total 14130500 # number of overall miss cycles 84111731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) 84211731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) 84311731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 153 # number of ReadCleanReq accesses(hits+misses) 84411731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 153 # number of ReadCleanReq accesses(hits+misses) 84511731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) 84611731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) 84711731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.inst 153 # number of demand (read+write) accesses 84811731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::cpu.data 34 # number of demand (read+write) accesses 84911731Sjason@lowepower.comsystem.cpu.l2cache.demand_accesses::total 187 # number of demand (read+write) accesses 85011731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.inst 153 # number of overall (read+write) accesses 85111731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::cpu.data 34 # number of overall (read+write) accesses 85211731Sjason@lowepower.comsystem.cpu.l2cache.overall_accesses::total 187 # number of overall (read+write) accesses 85311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 85411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 85511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993464 # miss rate for ReadCleanReq accesses 85611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993464 # miss rate for ReadCleanReq accesses 85711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses 85811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses 85911731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993464 # miss rate for demand accesses 86011731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.970588 # miss rate for demand accesses 86111731Sjason@lowepower.comsystem.cpu.l2cache.demand_miss_rate::total 0.989305 # miss rate for demand accesses 86211731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993464 # miss rate for overall accesses 86311731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.970588 # miss rate for overall accesses 86411731Sjason@lowepower.comsystem.cpu.l2cache.overall_miss_rate::total 0.989305 # miss rate for overall accesses 86511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78027.777778 # average ReadExReq miss latency 86611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78027.777778 # average ReadExReq miss latency 86711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76447.368421 # average ReadCleanReq miss latency 86811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76447.368421 # average ReadCleanReq miss latency 86911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73733.333333 # average ReadSharedReq miss latency 87011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73733.333333 # average ReadSharedReq miss latency 87111731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency 87211731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency 87311731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_miss_latency::total 76381.081081 # average overall miss latency 87411731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency 87511731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency 87611731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_miss_latency::total 76381.081081 # average overall miss latency 87711731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87811731Sjason@lowepower.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87911731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 88011731Sjason@lowepower.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 88111731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 88211731Sjason@lowepower.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88311731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses 88411731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses 88511731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 152 # number of ReadCleanReq MSHR misses 88611731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 152 # number of ReadCleanReq MSHR misses 88711731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses 88811731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses 88911731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 152 # number of demand (read+write) MSHR misses 89011731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses 89111731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses 89211731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 152 # number of overall MSHR misses 89311731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses 89411731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_misses::total 185 # number of overall MSHR misses 89511731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1224500 # number of ReadExReq MSHR miss cycles 89611731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1224500 # number of ReadExReq MSHR miss cycles 89711731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10120000 # number of ReadCleanReq MSHR miss cycles 89811731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10120000 # number of ReadCleanReq MSHR miss cycles 89911731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 966000 # number of ReadSharedReq MSHR miss cycles 90011731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 966000 # number of ReadSharedReq MSHR miss cycles 90111731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10120000 # number of demand (read+write) MSHR miss cycles 90211731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2190500 # number of demand (read+write) MSHR miss cycles 90311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 12310500 # number of demand (read+write) MSHR miss cycles 90411731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10120000 # number of overall MSHR miss cycles 90511731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2190500 # number of overall MSHR miss cycles 90611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 12310500 # number of overall MSHR miss cycles 90711731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 90811731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 90911731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for ReadCleanReq accesses 91011731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993464 # mshr miss rate for ReadCleanReq accesses 91111731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses 91211731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses 91311731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for demand accesses 91411731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for demand accesses 91511731Sjason@lowepower.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.989305 # mshr miss rate for demand accesses 91611731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for overall accesses 91711731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for overall accesses 91811731Sjason@lowepower.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.989305 # mshr miss rate for overall accesses 91911731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency 92011731Sjason@lowepower.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency 92111731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency 92211731Sjason@lowepower.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency 92311731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency 92411731Sjason@lowepower.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency 92511731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency 92611731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency 92711731Sjason@lowepower.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency 92811731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency 92911731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency 93011731Sjason@lowepower.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency 93111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter. 93211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 93311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 93411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 93511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 93611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 93711731Sjason@lowepower.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 93811731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution 93911731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution 94011731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution 94111731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution 94211731Sjason@lowepower.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution 94311731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes) 94411731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes) 94511731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes) 94611731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes) 94711731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) 94811731Sjason@lowepower.comsystem.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes) 94911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 95011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 95111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram 95211731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram 95311731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram 95411731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 95511731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram 95611731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram 95711731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 95811731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95911731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 96011731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 96111731Sjason@lowepower.comsystem.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram 96211731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks) 96311731Sjason@lowepower.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 96411731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks) 96511731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 96611731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) 96711731Sjason@lowepower.comsystem.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 96811731Sjason@lowepower.comsystem.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter. 96911731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 97011731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 97111731Sjason@lowepower.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 97211731Sjason@lowepower.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 97311731Sjason@lowepower.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 97411731Sjason@lowepower.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states 97511731Sjason@lowepower.comsystem.membus.trans_dist::ReadResp 164 # Transaction distribution 97611731Sjason@lowepower.comsystem.membus.trans_dist::ReadExReq 18 # Transaction distribution 97711731Sjason@lowepower.comsystem.membus.trans_dist::ReadExResp 18 # Transaction distribution 97811731Sjason@lowepower.comsystem.membus.trans_dist::ReadSharedReq 166 # Transaction distribution 97911731Sjason@lowepower.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes) 98011731Sjason@lowepower.comsystem.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes) 98111731Sjason@lowepower.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes) 98211731Sjason@lowepower.comsystem.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes) 98311731Sjason@lowepower.comsystem.membus.snoops 0 # Total snoops (count) 98411731Sjason@lowepower.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 98511731Sjason@lowepower.comsystem.membus.snoop_fanout::samples 184 # Request fanout histogram 98611731Sjason@lowepower.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 98711731Sjason@lowepower.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 98811731Sjason@lowepower.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 98911731Sjason@lowepower.comsystem.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram 99011731Sjason@lowepower.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 99111731Sjason@lowepower.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99211731Sjason@lowepower.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 99311731Sjason@lowepower.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 99411731Sjason@lowepower.comsystem.membus.snoop_fanout::total 184 # Request fanout histogram 99511731Sjason@lowepower.comsystem.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) 99611731Sjason@lowepower.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 99711731Sjason@lowepower.comsystem.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks) 99811731Sjason@lowepower.comsystem.membus.respLayer1.utilization 11.9 # Layer utilization (%) 99911731Sjason@lowepower.com 100011731Sjason@lowepower.com---------- End Simulation Statistics ---------- 1001