simout revision 12062:d6ee16239a26
1Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simout
2Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simerr
3gem5 Simulator System.  http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
6gem5 compiled May 31 2017 18:33:59
7gem5 started May 31 2017 18:34:13
8gem5 executing on boldrock, pid 15720
9command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing
10
11Global frequency set at 1000000000000 ticks per second
12Hello world!
13Exiting @ tick 21876000 because exiting with last active thread context
14