stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000015 # Number of seconds simulated 4sim_ticks 14724500 # Number of ticks simulated 5final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 11850 # Simulator instruction rate (inst/s) 8host_op_rate 11850 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30123505 # Simulator tick rate (ticks/s) 10host_mem_usage 266600 # Number of bytes of host memory used 11host_seconds 0.49 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 446 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 28544 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 14617000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 446 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 2285750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests 154system.physmem.totBusLat 2230000 # Total cycles spent in databus access 155system.physmem.totBankLat 8263750 # Total cycles spent in bank access 156system.physmem.avgQLat 5125.00 # Average queueing delay per request 157system.physmem.avgBankLat 18528.59 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 28653.59 # Average memory access latency 160system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 15.14 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.87 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 338 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 32773.54 # Average gap between requests 173system.cpu.branchPred.lookups 2226 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 599 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. 182system.cpu.dtb.read_hits 0 # DTB read hits 183system.cpu.dtb.read_misses 0 # DTB read misses 184system.cpu.dtb.read_accesses 0 # DTB read accesses 185system.cpu.dtb.write_hits 0 # DTB write hits 186system.cpu.dtb.write_misses 0 # DTB write misses 187system.cpu.dtb.write_accesses 0 # DTB write accesses 188system.cpu.dtb.hits 0 # DTB hits 189system.cpu.dtb.misses 0 # DTB misses 190system.cpu.dtb.accesses 0 # DTB accesses 191system.cpu.itb.read_hits 0 # DTB read hits 192system.cpu.itb.read_misses 0 # DTB read misses 193system.cpu.itb.read_accesses 0 # DTB read accesses 194system.cpu.itb.write_hits 0 # DTB write hits 195system.cpu.itb.write_misses 0 # DTB write misses 196system.cpu.itb.write_accesses 0 # DTB write accesses 197system.cpu.itb.hits 0 # DTB hits 198system.cpu.itb.misses 0 # DTB misses 199system.cpu.itb.accesses 0 # DTB accesses 200system.cpu.workload.num_syscalls 9 # Number of system calls 201system.cpu.numCycles 29450 # number of cpu cycles simulated 202system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 203system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 204system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss 205system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed 206system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered 207system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken 208system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked 209system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing 210system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked 211system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched 212system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed 213system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle 231system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle 232system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle 233system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked 234system.cpu.decode.RunCycles 2083 # Number of cycles decode is running 235system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking 236system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing 237system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch 238system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction 239system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode 240system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode 241system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing 242system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle 243system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking 244system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst 245system.cpu.rename.RunCycles 1969 # Number of cycles rename is running 246system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking 247system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename 248system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 249system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full 250system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed 251system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made 252system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups 253system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups 254system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 255system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing 256system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 257system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 258system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer 259system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit. 260system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. 261system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. 262system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 263system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec) 264system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ 265system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued 266system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued 267system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling 268system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph 269system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed 270system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle 287system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 288system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available 289system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available 290system.cpu.iq.fu_full::IntDiv 0 0.00% 4.68% # attempts to use FU when none available 291system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.68% # attempts to use FU when none available 292system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.68% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.68% # attempts to use FU when none available 294system.cpu.iq.fu_full::FloatMult 0 0.00% 4.68% # attempts to use FU when none available 295system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.68% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.68% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.68% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.68% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.68% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.68% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.68% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdMult 0 0.00% 4.68% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.68% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdShift 0 0.00% 4.68% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.68% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.68% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.68% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.68% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.68% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.68% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.68% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.68% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available 317system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available 318system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available 319system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 320system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 321system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 322system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued 323system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued 324system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued 325system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued 326system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued 328system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued 329system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued 330system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued 351system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued 352system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued 353system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 354system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 355system.cpu.iq.FU_type_0::total 8907 # Type of FU issued 356system.cpu.iq.rate 0.302445 # Inst issue rate 357system.cpu.iq.fu_busy_cnt 171 # FU busy when requested 358system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) 359system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads 360system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes 361system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses 362system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 363system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 364system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 365system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses 366system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 367system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores 368system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 369system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed 370system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 371system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations 372system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed 373system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 374system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 375system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 376system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 377system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 378system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing 379system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking 380system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking 381system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ 382system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch 383system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions 384system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions 385system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions 386system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 387system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 388system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations 389system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly 390system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly 391system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute 392system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions 393system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed 394system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute 395system.cpu.iew.exec_swp 0 # number of swp insts executed 396system.cpu.iew.exec_nop 0 # number of nop insts executed 397system.cpu.iew.exec_refs 3204 # number of memory reference insts executed 398system.cpu.iew.exec_branches 1349 # Number of branches executed 399system.cpu.iew.exec_stores 1531 # Number of stores executed 400system.cpu.iew.exec_rate 0.288387 # Inst execution rate 401system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit 402system.cpu.iew.wb_count 8150 # cumulative count of insts written-back 403system.cpu.iew.wb_producers 4198 # num instructions producing a value 404system.cpu.iew.wb_consumers 6619 # num instructions consuming a value 405system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 406system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle 407system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back 408system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 409system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit 410system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 411system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted 412system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle 429system.cpu.commit.committedInsts 5792 # Number of instructions committed 430system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 431system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 432system.cpu.commit.refs 2007 # Number of memory references committed 433system.cpu.commit.loads 961 # Number of loads committed 434system.cpu.commit.membars 7 # Number of memory barriers committed 435system.cpu.commit.branches 1037 # Number of branches committed 436system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 437system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 438system.cpu.commit.function_calls 103 # Number of function calls committed. 439system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached 440system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 441system.cpu.rob.rob_reads 21027 # The number of ROB reads 442system.cpu.rob.rob_writes 21246 # The number of ROB writes 443system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 444system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling 445system.cpu.committedInsts 5792 # Number of Instructions Simulated 446system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 447system.cpu.committedInsts_total 5792 # Number of Instructions Simulated 448system.cpu.cpi 5.084599 # CPI: Cycles Per Instruction 449system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads 450system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle 451system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads 452system.cpu.int_regfile_reads 13468 # number of integer regfile reads 453system.cpu.int_regfile_writes 7037 # number of integer regfile writes 454system.cpu.fp_regfile_reads 25 # number of floating regfile reads 455system.cpu.fp_regfile_writes 2 # number of floating regfile writes 456system.cpu.icache.replacements 0 # number of replacements 457system.cpu.icache.tagsinuse 167.837630 # Cycle average of tags in use 458system.cpu.icache.total_refs 1361 # Total number of references to valid blocks. 459system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. 460system.cpu.icache.avg_refs 3.877493 # Average number of references to valid blocks. 461system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 462system.cpu.icache.occ_blocks::cpu.inst 167.837630 # Average occupied blocks per requestor 463system.cpu.icache.occ_percent::cpu.inst 0.081952 # Average percentage of cache occupancy 464system.cpu.icache.occ_percent::total 0.081952 # Average percentage of cache occupancy 465system.cpu.icache.ReadReq_hits::cpu.inst 1361 # number of ReadReq hits 466system.cpu.icache.ReadReq_hits::total 1361 # number of ReadReq hits 467system.cpu.icache.demand_hits::cpu.inst 1361 # number of demand (read+write) hits 468system.cpu.icache.demand_hits::total 1361 # number of demand (read+write) hits 469system.cpu.icache.overall_hits::cpu.inst 1361 # number of overall hits 470system.cpu.icache.overall_hits::total 1361 # number of overall hits 471system.cpu.icache.ReadReq_misses::cpu.inst 441 # number of ReadReq misses 472system.cpu.icache.ReadReq_misses::total 441 # number of ReadReq misses 473system.cpu.icache.demand_misses::cpu.inst 441 # number of demand (read+write) misses 474system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses 475system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses 476system.cpu.icache.overall_misses::total 441 # number of overall misses 477system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles 478system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles 479system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles 480system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles 481system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles 482system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles 483system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) 484system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses 486system.cpu.icache.demand_accesses::total 1802 # number of demand (read+write) accesses 487system.cpu.icache.overall_accesses::cpu.inst 1802 # number of overall (read+write) accesses 488system.cpu.icache.overall_accesses::total 1802 # number of overall (read+write) accesses 489system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.244728 # miss rate for ReadReq accesses 490system.cpu.icache.ReadReq_miss_rate::total 0.244728 # miss rate for ReadReq accesses 491system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 # miss rate for demand accesses 492system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses 493system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses 494system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses 495system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency 496system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency 497system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency 498system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency 499system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency 501system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked 502system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 504system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.avg_blocked_cycles::no_mshrs 52.500000 # average number of cycles each access was blocked 506system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.icache.fast_writes 0 # number of fast writes performed 508system.cpu.icache.cache_copies 0 # number of cache copies performed 509system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits 510system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 511system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits 512system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 513system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits 514system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits 515system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses 516system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 517system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses 518system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses 519system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses 520system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses 521system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17781500 # number of ReadReq MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_latency::total 17781500 # number of ReadReq MSHR miss cycles 523system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17781500 # number of demand (read+write) MSHR miss cycles 524system.cpu.icache.demand_mshr_miss_latency::total 17781500 # number of demand (read+write) MSHR miss cycles 525system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17781500 # number of overall MSHR miss cycles 526system.cpu.icache.overall_mshr_miss_latency::total 17781500 # number of overall MSHR miss cycles 527system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_mshr_miss_rate::total 0.194784 # mshr miss rate for ReadReq accesses 529system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for demand accesses 530system.cpu.icache.demand_mshr_miss_rate::total 0.194784 # mshr miss rate for demand accesses 531system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.194784 # mshr miss rate for overall accesses 532system.cpu.icache.overall_mshr_miss_rate::total 0.194784 # mshr miss rate for overall accesses 533system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50659.544160 # average ReadReq mshr miss latency 534system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50659.544160 # average ReadReq mshr miss latency 535system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency 536system.cpu.icache.demand_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency 537system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 # average overall mshr miss latency 538system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency 539system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.l2cache.replacements 0 # number of replacements 541system.cpu.l2cache.tagsinuse 198.145720 # Cycle average of tags in use 542system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. 543system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. 544system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. 545system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 546system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor 547system.cpu.l2cache.occ_blocks::cpu.data 31.359554 # Average occupied blocks per requestor 548system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy 549system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy 550system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy 551system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 552system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 553system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 554system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 555system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits 557system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 558system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 559system.cpu.l2cache.overall_hits::total 7 # number of overall hits 560system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses 561system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 562system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses 563system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 564system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 565system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 567system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 570system.cpu.l2cache.overall_misses::total 446 # number of overall misses 571system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # number of ReadReq miss cycles 573system.cpu.l2cache.ReadReq_miss_latency::total 20541000 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles 576system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.data 6079000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::total 23449000 # number of demand (read+write) miss cycles 579system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.data 6079000 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::total 23449000 # number of overall miss cycles 582system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 586system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 587system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses 588system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 589system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 590system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses 591system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses 592system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 593system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses 594system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses 595system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses 596system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 597system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 598system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses 599system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 600system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses 601system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses 602system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 603system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses 604system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency 605system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency 606system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency 607system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency 608system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency 609system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency 610system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency 611system.cpu.l2cache.demand_avg_miss_latency::total 52576.233184 # average overall miss latency 612system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency 613system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::total 52576.233184 # average overall miss latency 615system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 620system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 621system.cpu.l2cache.fast_writes 0 # number of fast writes performed 622system.cpu.l2cache.cache_copies 0 # number of cache copies performed 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 625system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 627system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 628system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses 629system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 630system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses 632system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 633system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13080769 # number of ReadReq MSHR miss cycles 635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509277 # number of ReadReq MSHR miss cycles 636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590046 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332772 # number of ReadExReq MSHR miss cycles 638system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332772 # number of ReadExReq MSHR miss cycles 639system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13080769 # number of demand (read+write) MSHR miss cycles 640system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842049 # number of demand (read+write) MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::total 17922818 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13080769 # number of overall MSHR miss cycles 643system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::total 17922818 # number of overall MSHR miss cycles 645system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses 651system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 652system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses 653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses 654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 655system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses 656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency 659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency 663system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency 665system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency 666system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency 667system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 668system.cpu.dcache.replacements 0 # number of replacements 669system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use 670system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. 671system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. 672system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. 673system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 674system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor 675system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy 676system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy 677system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits 678system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits 679system.cpu.dcache.WriteReq_hits::cpu.data 709 # number of WriteReq hits 680system.cpu.dcache.WriteReq_hits::total 709 # number of WriteReq hits 681system.cpu.dcache.demand_hits::cpu.data 2181 # number of demand (read+write) hits 682system.cpu.dcache.demand_hits::total 2181 # number of demand (read+write) hits 683system.cpu.dcache.overall_hits::cpu.data 2181 # number of overall hits 684system.cpu.dcache.overall_hits::total 2181 # number of overall hits 685system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 686system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses 687system.cpu.dcache.WriteReq_misses::cpu.data 337 # number of WriteReq misses 688system.cpu.dcache.WriteReq_misses::total 337 # number of WriteReq misses 689system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses 692system.cpu.dcache.overall_misses::total 438 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles 697system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles 698system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles 699system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles 700system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles 701system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) 702system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) 703system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 704system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 705system.cpu.dcache.demand_accesses::cpu.data 2619 # number of demand (read+write) accesses 706system.cpu.dcache.demand_accesses::total 2619 # number of demand (read+write) accesses 707system.cpu.dcache.overall_accesses::cpu.data 2619 # number of overall (read+write) accesses 708system.cpu.dcache.overall_accesses::total 2619 # number of overall (read+write) accesses 709system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064209 # miss rate for ReadReq accesses 710system.cpu.dcache.ReadReq_miss_rate::total 0.064209 # miss rate for ReadReq accesses 711system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.322180 # miss rate for WriteReq accesses 712system.cpu.dcache.WriteReq_miss_rate::total 0.322180 # miss rate for WriteReq accesses 713system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 # miss rate for demand accesses 714system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses 715system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses 716system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses 717system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency 718system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency 719system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency 720system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency 721system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency 722system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency 723system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency 724system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency 725system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked 726system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked 728system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 729system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked 730system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.dcache.fast_writes 0 # number of fast writes performed 732system.cpu.dcache.cache_copies 0 # number of cache copies performed 733system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits 734system.cpu.dcache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits 735system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits 736system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits 737system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits 738system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits 739system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits 740system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits 741system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 742system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 743system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 744system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 745system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 746system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 747system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 748system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses 749system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles 750system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles 751system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles 752system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles 753system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles 754system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles 755system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles 756system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles 757system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses 758system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses 759system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 760system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for demand accesses 762system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses 763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses 764system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses 765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency 769system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency 770system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency 771system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency 772system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency 773system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 774 775---------- End Simulation Statistics ---------- 776