stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000011 # Number of seconds simulated 4sim_ticks 11243500 # Number of ticks simulated 5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 72271 # Simulator instruction rate (inst/s) 8host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 140039967 # Simulator tick rate (ticks/s) 10host_mem_usage 211876 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5800 # Number of instructions simulated 13sim_ops 5800 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 449 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses 38system.cpu.dtb.accesses 0 # DTB accesses 39system.cpu.itb.read_hits 0 # DTB read hits 40system.cpu.itb.read_misses 0 # DTB read misses 41system.cpu.itb.read_accesses 0 # DTB read accesses 42system.cpu.itb.write_hits 0 # DTB write hits 43system.cpu.itb.write_misses 0 # DTB write misses 44system.cpu.itb.write_accesses 0 # DTB write accesses 45system.cpu.itb.hits 0 # DTB hits 46system.cpu.itb.misses 0 # DTB misses 47system.cpu.itb.accesses 0 # DTB accesses 48system.cpu.workload.num_syscalls 9 # Number of system calls 49system.cpu.numCycles 22488 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.BPredUnit.lookups 2514 # Number of BP lookups 53system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted 54system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect 55system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups 56system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits 57system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 58system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. 59system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. 60system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss 61system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed 62system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered 63system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken 64system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked 65system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing 66system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked 67system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 68system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched 69system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed 70system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) 71system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) 72system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) 73system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 74system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle 88system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle 89system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle 90system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked 91system.cpu.decode.RunCycles 2252 # Number of cycles decode is running 92system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 93system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing 94system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch 95system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction 96system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode 97system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode 98system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing 99system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle 100system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking 101system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst 102system.cpu.rename.RunCycles 2095 # Number of cycles rename is running 103system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking 104system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename 105system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full 106system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full 107system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed 108system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made 109system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups 110system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups 111system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed 112system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing 113system.cpu.rename.serializingInsts 25 # count of serializing insts renamed 114system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 115system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer 116system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. 117system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. 118system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. 119system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. 120system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) 121system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ 122system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued 123system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued 124system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling 125system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph 126system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed 127system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle 128system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle 129system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle 130system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 131system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle 132system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle 144system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 145system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available 146system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available 147system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available 148system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available 149system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available 150system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available 151system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available 152system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available 153system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available 154system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available 155system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available 156system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available 157system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available 174system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available 175system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available 176system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 177system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 178system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 179system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued 180system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued 181system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued 182system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued 183system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued 184system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued 185system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued 186system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued 187system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued 188system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued 189system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued 190system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued 191system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued 208system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued 209system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued 210system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 211system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 212system.cpu.iq.FU_type_0::total 9284 # Type of FU issued 213system.cpu.iq.rate 0.412842 # Inst issue rate 214system.cpu.iq.fu_busy_cnt 173 # FU busy when requested 215system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) 216system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads 217system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes 218system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses 219system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 220system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 221system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 222system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses 223system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 224system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores 225system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 226system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed 227system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 228system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 229system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed 230system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 231system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 232system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 233system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 234system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 235system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing 236system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking 237system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 238system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ 239system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch 240system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions 241system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions 242system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions 243system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 244system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall 245system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 246system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly 247system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly 248system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute 249system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions 250system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed 251system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute 252system.cpu.iew.exec_swp 0 # number of swp insts executed 253system.cpu.iew.exec_nop 0 # number of nop insts executed 254system.cpu.iew.exec_refs 3258 # number of memory reference insts executed 255system.cpu.iew.exec_branches 1391 # Number of branches executed 256system.cpu.iew.exec_stores 1554 # Number of stores executed 257system.cpu.iew.exec_rate 0.389274 # Inst execution rate 258system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit 259system.cpu.iew.wb_count 8387 # cumulative count of insts written-back 260system.cpu.iew.wb_producers 4351 # num instructions producing a value 261system.cpu.iew.wb_consumers 7020 # num instructions consuming a value 262system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 263system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle 264system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back 265system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 266system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions 267system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions 268system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit 269system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 270system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted 271system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle 272system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle 273system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle 274system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 275system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle 276system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle 288system.cpu.commit.committedInsts 5800 # Number of instructions committed 289system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed 290system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 291system.cpu.commit.refs 2008 # Number of memory references committed 292system.cpu.commit.loads 962 # Number of loads committed 293system.cpu.commit.membars 7 # Number of memory barriers committed 294system.cpu.commit.branches 1038 # Number of branches committed 295system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 296system.cpu.commit.int_insts 5706 # Number of committed integer instructions. 297system.cpu.commit.function_calls 103 # Number of function calls committed. 298system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached 299system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 300system.cpu.rob.rob_reads 21145 # The number of ROB reads 301system.cpu.rob.rob_writes 22688 # The number of ROB writes 302system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself 303system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling 304system.cpu.committedInsts 5800 # Number of Instructions Simulated 305system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated 306system.cpu.committedInsts_total 5800 # Number of Instructions Simulated 307system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction 308system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads 309system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle 310system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads 311system.cpu.int_regfile_reads 13921 # number of integer regfile reads 312system.cpu.int_regfile_writes 7265 # number of integer regfile writes 313system.cpu.fp_regfile_reads 25 # number of floating regfile reads 314system.cpu.fp_regfile_writes 2 # number of floating regfile writes 315system.cpu.icache.replacements 0 # number of replacements 316system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use 317system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. 318system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. 319system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. 320system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor 322system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy 323system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy 324system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits 325system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits 326system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits 327system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits 328system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits 329system.cpu.icache.overall_hits::total 1462 # number of overall hits 330system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 331system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 332system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 333system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 334system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 335system.cpu.icache.overall_misses::total 437 # number of overall misses 336system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles 337system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles 338system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles 339system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles 340system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles 341system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles 342system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) 343system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) 344system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses 345system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses 346system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses 347system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses 348system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses 349system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses 350system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses 351system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses 352system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses 353system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses 354system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency 355system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency 356system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 357system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency 359system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency 360system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.icache.fast_writes 0 # number of fast writes performed 367system.cpu.icache.cache_copies 0 # number of cache copies performed 368system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits 369system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 370system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits 371system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits 372system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits 373system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits 374system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses 375system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses 376system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses 377system.cpu.icache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses 378system.cpu.icache.overall_mshr_misses::cpu.inst 355 # number of overall MSHR misses 379system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses 380system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles 381system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles 382system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles 383system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles 384system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles 385system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles 386system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses 387system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses 388system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses 389system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses 390system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses 391system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses 392system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency 393system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency 394system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency 395system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency 396system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency 397system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency 398system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 399system.cpu.dcache.replacements 0 # number of replacements 400system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use 401system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. 402system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. 403system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. 404system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 405system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor 406system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy 407system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy 408system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits 409system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits 410system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits 411system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits 412system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits 413system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits 414system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits 415system.cpu.dcache.overall_hits::total 2216 # number of overall hits 416system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 417system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses 418system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 419system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 420system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses 421system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses 422system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses 423system.cpu.dcache.overall_misses::total 399 # number of overall misses 424system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles 425system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles 426system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles 427system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles 428system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles 429system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles 430system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles 431system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles 432system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 436system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses 437system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses 438system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses 439system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses 440system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses 441system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses 442system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses 443system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses 444system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses 445system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses 446system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses 447system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses 448system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency 449system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency 450system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency 451system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency 452system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 453system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency 454system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency 455system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency 456system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 457system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 458system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 460system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 461system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 462system.cpu.dcache.fast_writes 0 # number of fast writes performed 463system.cpu.dcache.cache_copies 0 # number of cache copies performed 464system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits 465system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits 466system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits 467system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits 468system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits 469system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits 470system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits 471system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits 472system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses 473system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses 474system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses 475system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses 476system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses 477system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses 478system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses 479system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses 480system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles 481system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles 482system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles 483system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles 487system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles 488system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses 489system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses 493system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses 494system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses 495system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses 496system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency 497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency 498system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency 499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency 500system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency 501system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency 502system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency 503system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency 504system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 505system.cpu.l2cache.replacements 0 # number of replacements 506system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use 507system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. 508system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. 509system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. 510system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 511system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor 512system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor 513system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy 514system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy 515system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy 516system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 517system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits 518system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 519system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits 520system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 521system.cpu.l2cache.overall_hits::total 5 # number of overall hits 522system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses 523system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses 524system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses 525system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses 526system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses 527system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses 528system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses 529system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses 530system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses 531system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses 532system.cpu.l2cache.overall_misses::total 449 # number of overall misses 533system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles 534system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles 535system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles 536system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles 537system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles 538system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles 539system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles 540system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles 541system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles 542system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles 543system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles 544system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) 545system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) 546system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) 547system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) 548system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) 549system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses 550system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses 552system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses 555system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses 558system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 559system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 560system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses 561system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 562system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses 563system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses 564system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 565system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses 566system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency 567system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency 568system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency 569system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency 570system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency 571system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 572system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 573system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency 574system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency 575system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency 576system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency 577system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 583system.cpu.l2cache.fast_writes 0 # number of fast writes performed 584system.cpu.l2cache.cache_copies 0 # number of cache copies performed 585system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 586system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses 587system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses 588system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses 589system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses 590system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 591system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses 592system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses 593system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 594system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses 595system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses 596system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles 597system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles 598system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles 599system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles 600system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles 601system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles 602system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles 603system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles 604system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles 605system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles 606system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles 607system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses 608system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 609system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses 610system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 611system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 612system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses 613system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 614system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses 615system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses 616system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 617system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses 618system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency 619system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency 620system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency 621system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency 622system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency 623system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency 626system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency 627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency 628system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency 629system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 630 631---------- End Simulation Statistics ---------- 632