stats.txt revision 11214:966091379ded
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19923000 # Number of ticks simulated 5final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 101947 # Simulator instruction rate (inst/s) 8host_op_rate 101922 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 350504038 # Simulator tick rate (ticks/s) 10host_mem_usage 292056 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 71 # Per bank write bursts 45system.physmem.perBankRdBursts::1 42 # Per bank write bursts 46system.physmem.perBankRdBursts::2 55 # Per bank write bursts 47system.physmem.perBankRdBursts::3 58 # Per bank write bursts 48system.physmem.perBankRdBursts::4 53 # Per bank write bursts 49system.physmem.perBankRdBursts::5 61 # Per bank write bursts 50system.physmem.perBankRdBursts::6 52 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 9 # Per bank write bursts 53system.physmem.perBankRdBursts::9 28 # Per bank write bursts 54system.physmem.perBankRdBursts::10 1 # Per bank write bursts 55system.physmem.perBankRdBursts::11 0 # Per bank write bursts 56system.physmem.perBankRdBursts::12 0 # Per bank write bursts 57system.physmem.perBankRdBursts::13 0 # Per bank write bursts 58system.physmem.perBankRdBursts::14 4 # Per bank write bursts 59system.physmem.perBankRdBursts::15 0 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 19783500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 340.210526 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 203.437950 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 338.690117 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 26 34.21% 34.21% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 22.37% 56.58% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation 203system.physmem.totQLat 3746750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.14 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 359 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 44557.43 # Average gap between requests 224system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ) 233system.physmem_0.averagePower 949.326386 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) 247system.physmem_1.averagePower 748.283278 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2359 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 725 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 36.579213 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses 268system.cpu.dtb.write_accesses 0 # DTB write accesses 269system.cpu.dtb.hits 0 # DTB hits 270system.cpu.dtb.misses 0 # DTB misses 271system.cpu.dtb.accesses 0 # DTB accesses 272system.cpu.itb.read_hits 0 # DTB read hits 273system.cpu.itb.read_misses 0 # DTB read misses 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls 282system.cpu.numCycles 39847 # number of cpu cycles simulated 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing 291system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 292system.cpu.fetch.PendingTrapStallCycles 147 # Number of stall cycles due to pending traps 293system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 294system.cpu.fetch.CacheLines 1822 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12019 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.097263 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.493815 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::0 9698 80.69% 80.69% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 176 1.46% 82.15% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 221 1.84% 83.99% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 153 1.27% 85.26% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 238 1.98% 87.25% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 1924 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing 320system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction 322system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode 323system.cpu.decode.SquashedInsts 469 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 271 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 7350 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 927 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 518 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 1884 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 1069 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 10932 # Number of instructions processed by rename 331system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 332system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full 333system.cpu.rename.SQFullEvents 1028 # Number of times rename has blocked due to SQ full 334system.cpu.rename.RenamedOperands 9574 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 17720 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 17694 # Number of integer rename lookups 337system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 338system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 339system.cpu.rename.UndoneMaps 4576 # Number of HB maps that are undone due to squashing 340system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 342system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 1935 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1629 # Number of stores inserted to the mem dependence unit. 345system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. 346system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 347system.cpu.iq.iqInstsAdded 10141 # Number of instructions added to the IQ (excludes non-spec) 348system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ 349system.cpu.iq.iqInstsIssued 8840 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued 351system.cpu.iq.iqSquashedInstsExamined 4412 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph 353system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed 354system.cpu.iq.issued_per_cycle::samples 12019 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.735502 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.540494 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::0 8914 74.17% 74.17% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 959 7.98% 82.14% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 649 5.40% 87.54% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 465 3.87% 91.41% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 426 3.54% 94.96% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 281 2.34% 97.30% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 228 1.90% 99.19% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::7 65 0.54% 99.73% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::total 12019 # Number of insts issued each cycle 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntAlu 13 6.47% 6.47% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 6.47% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 6.47% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.47% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.47% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.47% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 6.47% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.47% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.47% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.47% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.47% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.47% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.47% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.47% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.47% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMult 0 0.00% 6.47% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.47% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShift 0 0.00% 6.47% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.47% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.47% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.47% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.47% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.47% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.47% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.47% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.47% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.47% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.47% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.47% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 95 47.26% 53.73% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 93 46.27% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 406system.cpu.iq.FU_type_0::IntAlu 5519 62.43% 62.43% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.43% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.45% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.45% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 8840 # Type of FU issued 440system.cpu.iq.rate 0.221849 # Inst issue rate 441system.cpu.iq.fu_busy_cnt 201 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 449system.cpu.iq.int_alu_accesses 9007 # Number of integer alu accesses 450system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 451system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 453system.cpu.iew.lsq.thread0.squashedLoads 974 # Number of loads squashed 454system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 455system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 456system.cpu.iew.lsq.thread0.squashedStores 583 # Number of stores squashed 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 462system.cpu.iew.iewSquashCycles 271 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 843 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking 465system.cpu.iew.iewDispatchedInsts 10204 # Number of instructions dispatched to IQ 466system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch 467system.cpu.iew.iewDispLoadInsts 1935 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1629 # Number of dispatched store instructions 469system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions 470system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall 472system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 72 # Number of branches that were predicted taken incorrectly 474system.cpu.iew.predictedNotTakenIncorrect 254 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 326 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed 481system.cpu.iew.exec_refs 3121 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1355 # Number of branches executed 483system.cpu.iew.exec_stores 1414 # Number of stores executed 484system.cpu.iew.exec_rate 0.212939 # Inst execution rate 485system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8147 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4452 # num instructions producing a value 488system.cpu.iew.wb_consumers 7114 # num instructions consuming a value 489system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back 491system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit 492system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 493system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted 494system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::0 9160 80.89% 80.89% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::1 847 7.48% 88.37% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::2 528 4.66% 93.03% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::3 216 1.91% 94.94% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::4 182 1.61% 96.55% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::5 106 0.94% 97.48% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::6 122 1.08% 98.56% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::7 53 0.47% 99.03% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::8 110 0.97% 100.00% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::total 11324 # Number of insts commited each cycle 511system.cpu.commit.committedInsts 5792 # Number of instructions committed 512system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 513system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 514system.cpu.commit.refs 2007 # Number of memory references committed 515system.cpu.commit.loads 961 # Number of loads committed 516system.cpu.commit.membars 7 # Number of memory barriers committed 517system.cpu.commit.branches 1037 # Number of branches committed 518system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 519system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 520system.cpu.commit.function_calls 103 # Number of function calls committed. 521system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 522system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction 523system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction 524system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction 525system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction 526system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 551system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 552system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 553system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 556system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached 557system.cpu.rob.rob_reads 21420 # The number of ROB reads 558system.cpu.rob.rob_writes 21108 # The number of ROB writes 559system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself 560system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling 561system.cpu.committedInsts 5792 # Number of Instructions Simulated 562system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 563system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction 564system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads 565system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle 566system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads 567system.cpu.int_regfile_reads 13451 # number of integer regfile reads 568system.cpu.int_regfile_writes 7138 # number of integer regfile writes 569system.cpu.fp_regfile_reads 25 # number of floating regfile reads 570system.cpu.fp_regfile_writes 2 # number of floating regfile writes 571system.cpu.dcache.tags.replacements 0 # number of replacements 572system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use 573system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. 574system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. 575system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. 576system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 577system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor 578system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy 579system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy 580system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id 581system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 582system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 583system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id 584system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses 585system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses 586system.cpu.dcache.ReadReq_hits::cpu.data 1492 # number of ReadReq hits 587system.cpu.dcache.ReadReq_hits::total 1492 # number of ReadReq hits 588system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits 589system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits 590system.cpu.dcache.demand_hits::cpu.data 2213 # number of demand (read+write) hits 591system.cpu.dcache.demand_hits::total 2213 # number of demand (read+write) hits 592system.cpu.dcache.overall_hits::cpu.data 2213 # number of overall hits 593system.cpu.dcache.overall_hits::total 2213 # number of overall hits 594system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses 595system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses 596system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses 597system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses 598system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses 599system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses 600system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses 601system.cpu.dcache.overall_misses::total 433 # number of overall misses 602system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles 603system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles 604system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles 605system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles 606system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles 607system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles 608system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles 609system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles 610system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) 611system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) 612system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 613system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 614system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses 615system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses 616system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses 617system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses 618system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses 619system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses 620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses 621system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency 630system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency 631system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency 632system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency 633system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency 634system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked 635system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 636system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 637system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked 639system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 640system.cpu.dcache.fast_writes 0 # number of fast writes performed 641system.cpu.dcache.cache_copies 0 # number of cache copies performed 642system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits 643system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits 644system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits 645system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits 646system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits 647system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits 648system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits 649system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits 650system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses 651system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses 652system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 653system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 654system.cpu.dcache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses 655system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses 656system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses 657system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses 658system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles 659system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles 660system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles 661system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses 667system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses 668system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 669system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 670system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for demand accesses 671system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses 672system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses 673system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses 674system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency 675system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency 676system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency 677system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency 678system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency 679system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency 680system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency 681system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency 682system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 683system.cpu.icache.tags.replacements 0 # number of replacements 684system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use 685system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. 686system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 687system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. 688system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 689system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor 690system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy 691system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy 692system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 693system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id 694system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id 695system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 696system.cpu.icache.tags.tag_accesses 3993 # Number of tag accesses 697system.cpu.icache.tags.data_accesses 3993 # Number of data accesses 698system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits 699system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits 700system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits 701system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits 702system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits 703system.cpu.icache.overall_hits::total 1389 # number of overall hits 704system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses 705system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses 706system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses 707system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses 708system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses 709system.cpu.icache.overall_misses::total 433 # number of overall misses 710system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles 711system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles 712system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles 713system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles 714system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles 715system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles 716system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) 717system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) 718system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses 719system.cpu.icache.demand_accesses::total 1822 # number of demand (read+write) accesses 720system.cpu.icache.overall_accesses::cpu.inst 1822 # number of overall (read+write) accesses 721system.cpu.icache.overall_accesses::total 1822 # number of overall (read+write) accesses 722system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.237651 # miss rate for ReadReq accesses 723system.cpu.icache.ReadReq_miss_rate::total 0.237651 # miss rate for ReadReq accesses 724system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 # miss rate for demand accesses 725system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses 726system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses 727system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses 728system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency 729system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency 730system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency 731system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency 732system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency 733system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency 734system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked 735system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 737system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked 739system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu.icache.fast_writes 0 # number of fast writes performed 741system.cpu.icache.cache_copies 0 # number of cache copies performed 742system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83 # number of ReadReq MSHR hits 743system.cpu.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits 744system.cpu.icache.demand_mshr_hits::cpu.inst 83 # number of demand (read+write) MSHR hits 745system.cpu.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits 746system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits 747system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits 748system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 749system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 750system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 751system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 752system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 753system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses 754system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles 755system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles 756system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles 757system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles 758system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles 759system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles 760system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses 761system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses 762system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses 763system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses 764system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses 765system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency 767system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency 769system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency 771system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency 772system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 773system.cpu.l2cache.tags.replacements 0 # number of replacements 774system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use 775system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. 776system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 777system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. 778system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 779system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor 780system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor 781system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy 784system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id 786system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id 787system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 788system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses 789system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses 790system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits 791system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits 792system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 793system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 794system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 795system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits 796system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits 797system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 798system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits 799system.cpu.l2cache.overall_hits::total 8 # number of overall hits 800system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 801system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 802system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses 803system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses 804system.cpu.l2cache.ReadSharedReq_misses::cpu.data 54 # number of ReadSharedReq misses 805system.cpu.l2cache.ReadSharedReq_misses::total 54 # number of ReadSharedReq misses 806system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 807system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 808system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 809system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 810system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 811system.cpu.l2cache.overall_misses::total 445 # number of overall misses 812system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles 813system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles 814system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles 815system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles 816system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles 817system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles 824system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 825system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 826system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) 827system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) 828system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) 829system.cpu.l2cache.ReadSharedReq_accesses::total 56 # number of ReadSharedReq accesses(hits+misses) 830system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 831system.cpu.l2cache.demand_accesses::cpu.data 103 # number of demand (read+write) accesses 832system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses 833system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses 834system.cpu.l2cache.overall_accesses::cpu.data 103 # number of overall (read+write) accesses 835system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses 836system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 837system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 838system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses 839system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses 840system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964286 # miss rate for ReadSharedReq accesses 841system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964286 # miss rate for ReadSharedReq accesses 842system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 843system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses 844system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses 845system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 846system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses 847system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses 848system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency 849system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency 850system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency 851system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency 852system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency 853system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency 854system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency 855system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency 856system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency 857system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency 858system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency 859system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency 860system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 861system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 862system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 863system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 864system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 865system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 866system.cpu.l2cache.fast_writes 0 # number of fast writes performed 867system.cpu.l2cache.cache_copies 0 # number of cache copies performed 868system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 869system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 870system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses 871system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses 872system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 54 # number of ReadSharedReq MSHR misses 873system.cpu.l2cache.ReadSharedReq_mshr_misses::total 54 # number of ReadSharedReq MSHR misses 874system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 875system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 876system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 877system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 878system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 879system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 880system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles 881system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles 882system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles 883system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles 884system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles 885system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles 886system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles 887system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles 888system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles 889system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles 890system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles 891system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 893system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 894system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses 895system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses 896system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses 897system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses 898system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 899system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses 900system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses 901system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 902system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses 903system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses 904system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency 905system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency 906system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency 907system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency 908system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency 909system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency 910system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency 911system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency 912system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency 913system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency 914system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency 915system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency 916system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 917system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter. 918system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. 919system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 920system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 921system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 922system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 923system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution 928system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 929system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) 930system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) 931system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 932system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes) 933system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) 934system.cpu.toL2Bus.snoops 0 # Total snoops (count) 935system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 943system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 945system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram 946system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) 947system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 948system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) 949system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 950system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks) 951system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 952system.membus.trans_dist::ReadResp 397 # Transaction distribution 953system.membus.trans_dist::ReadExReq 47 # Transaction distribution 954system.membus.trans_dist::ReadExResp 47 # Transaction distribution 955system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution 956system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 957system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 958system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 959system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 960system.membus.snoops 0 # Total snoops (count) 961system.membus.snoop_fanout::samples 444 # Request fanout histogram 962system.membus.snoop_fanout::mean 0 # Request fanout histogram 963system.membus.snoop_fanout::stdev 0 # Request fanout histogram 964system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 965system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram 966system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 967system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 968system.membus.snoop_fanout::min_value 0 # Request fanout histogram 969system.membus.snoop_fanout::max_value 0 # Request fanout histogram 970system.membus.snoop_fanout::total 444 # Request fanout histogram 971system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) 972system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 973system.membus.respLayer1.occupancy 2342750 # Layer occupancy (ticks) 974system.membus.respLayer1.utilization 11.8 # Layer utilization (%) 975 976---------- End Simulation Statistics ---------- 977