stats.txt revision 10488:7c27480a5031
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18857500 # Number of ticks simulated 5final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 71546 # Simulator instruction rate (inst/s) 8host_op_rate 71536 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 232873039 # Simulator tick rate (ticks/s) 10host_mem_usage 233800 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host 12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 71 # Per bank write bursts 45system.physmem.perBankRdBursts::1 42 # Per bank write bursts 46system.physmem.perBankRdBursts::2 55 # Per bank write bursts 47system.physmem.perBankRdBursts::3 58 # Per bank write bursts 48system.physmem.perBankRdBursts::4 53 # Per bank write bursts 49system.physmem.perBankRdBursts::5 61 # Per bank write bursts 50system.physmem.perBankRdBursts::6 52 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 9 # Per bank write bursts 53system.physmem.perBankRdBursts::9 28 # Per bank write bursts 54system.physmem.perBankRdBursts::10 1 # Per bank write bursts 55system.physmem.perBankRdBursts::11 0 # Per bank write bursts 56system.physmem.perBankRdBursts::12 0 # Per bank write bursts 57system.physmem.perBankRdBursts::13 0 # Per bank write bursts 58system.physmem.perBankRdBursts::14 4 # Per bank write bursts 59system.physmem.perBankRdBursts::15 0 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 18724000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 203system.physmem.totQLat 3635500 # Total ticks spent queuing 204system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.77 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 356 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 42171.17 # Average gap between requests 224system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.physmem.actEnergy::0 476280 # Energy for activate commands per rank (pJ) 231system.physmem.actEnergy::1 68040 # Energy for activate commands per rank (pJ) 232system.physmem.preEnergy::0 259875 # Energy for precharge commands per rank (pJ) 233system.physmem.preEnergy::1 37125 # Energy for precharge commands per rank (pJ) 234system.physmem.readEnergy::0 2644200 # Energy for read commands per rank (pJ) 235system.physmem.readEnergy::1 288600 # Energy for read commands per rank (pJ) 236system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 237system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 238system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) 239system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) 240system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) 241system.physmem.actBackEnergy::1 8055810 # Energy for active background per rank (pJ) 242system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) 243system.physmem.preBackEnergy::1 2433000 # Energy for precharge background per rank (pJ) 244system.physmem.totalEnergy::0 15222495 # Total energy per rank (pJ) 245system.physmem.totalEnergy::1 11899695 # Total energy per rank (pJ) 246system.physmem.averagePower::0 961.471341 # Core power per rank (mW) 247system.physmem.averagePower::1 751.599242 # Core power per rank (mW) 248system.membus.trans_dist::ReadReq 397 # Transaction distribution 249system.membus.trans_dist::ReadResp 397 # Transaction distribution 250system.membus.trans_dist::ReadExReq 47 # Transaction distribution 251system.membus.trans_dist::ReadExResp 47 # Transaction distribution 252system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 253system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) 254system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 255system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 256system.membus.snoops 0 # Total snoops (count) 257system.membus.snoop_fanout::samples 444 # Request fanout histogram 258system.membus.snoop_fanout::mean 0 # Request fanout histogram 259system.membus.snoop_fanout::stdev 0 # Request fanout histogram 260system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 261system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram 262system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 263system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 264system.membus.snoop_fanout::min_value 0 # Request fanout histogram 265system.membus.snoop_fanout::max_value 0 # Request fanout histogram 266system.membus.snoop_fanout::total 444 # Request fanout histogram 267system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) 268system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 269system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) 270system.membus.respLayer1.utilization 22.1 # Layer utilization (%) 271system.cpu_clk_domain.clock 500 # Clock period in ticks 272system.cpu.branchPred.lookups 2332 # Number of BP lookups 273system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted 274system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect 275system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups 276system.cpu.branchPred.BTBHits 661 # Number of BTB hits 277system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 278system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage 279system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. 280system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. 281system.cpu.dtb.read_hits 0 # DTB read hits 282system.cpu.dtb.read_misses 0 # DTB read misses 283system.cpu.dtb.read_accesses 0 # DTB read accesses 284system.cpu.dtb.write_hits 0 # DTB write hits 285system.cpu.dtb.write_misses 0 # DTB write misses 286system.cpu.dtb.write_accesses 0 # DTB write accesses 287system.cpu.dtb.hits 0 # DTB hits 288system.cpu.dtb.misses 0 # DTB misses 289system.cpu.dtb.accesses 0 # DTB accesses 290system.cpu.itb.read_hits 0 # DTB read hits 291system.cpu.itb.read_misses 0 # DTB read misses 292system.cpu.itb.read_accesses 0 # DTB read accesses 293system.cpu.itb.write_hits 0 # DTB write hits 294system.cpu.itb.write_misses 0 # DTB write misses 295system.cpu.itb.write_accesses 0 # DTB write accesses 296system.cpu.itb.hits 0 # DTB hits 297system.cpu.itb.misses 0 # DTB misses 298system.cpu.itb.accesses 0 # DTB accesses 299system.cpu.workload.num_syscalls 9 # Number of system calls 300system.cpu.numCycles 37716 # number of cpu cycles simulated 301system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 302system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 303system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss 304system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed 305system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered 306system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken 307system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked 308system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing 309system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 310system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 311system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 312system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched 313system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 314system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle 332system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle 333system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle 334system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked 335system.cpu.decode.RunCycles 1951 # Number of cycles decode is running 336system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking 337system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing 338system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch 339system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction 340system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode 341system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode 342system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing 343system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle 344system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking 345system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst 346system.cpu.rename.RunCycles 1916 # Number of cycles rename is running 347system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking 348system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename 349system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 350system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full 351system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 352system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed 353system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made 354system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups 355system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 356system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 357system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing 358system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 359system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 360system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer 361system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. 362system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 363system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 364system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 365system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) 366system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ 367system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued 368system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued 369system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling 370system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph 371system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed 372system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle 389system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available 392system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 419system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 422system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 423system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 424system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued 425system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued 426system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued 453system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued 454system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 457system.cpu.iq.FU_type_0::total 9108 # Type of FU issued 458system.cpu.iq.rate 0.241489 # Inst issue rate 459system.cpu.iq.fu_busy_cnt 251 # FU busy when requested 460system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) 461system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads 462system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes 463system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses 464system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 465system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes 466system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 467system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses 468system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 469system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores 470system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 471system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed 472system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 473system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 474system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed 475system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 476system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 477system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 478system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 479system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 480system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing 481system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking 482system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking 483system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ 484system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch 485system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions 486system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions 487system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions 488system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall 489system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall 490system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 491system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 492system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly 493system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute 494system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions 495system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed 496system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute 497system.cpu.iew.exec_swp 0 # number of swp insts executed 498system.cpu.iew.exec_nop 0 # number of nop insts executed 499system.cpu.iew.exec_refs 3329 # number of memory reference insts executed 500system.cpu.iew.exec_branches 1361 # Number of branches executed 501system.cpu.iew.exec_stores 1554 # Number of stores executed 502system.cpu.iew.exec_rate 0.230724 # Inst execution rate 503system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit 504system.cpu.iew.wb_count 8300 # cumulative count of insts written-back 505system.cpu.iew.wb_producers 4483 # num instructions producing a value 506system.cpu.iew.wb_consumers 7102 # num instructions consuming a value 507system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 508system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle 509system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back 510system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 511system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit 512system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 513system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted 514system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle 531system.cpu.commit.committedInsts 5792 # Number of instructions committed 532system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 533system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 534system.cpu.commit.refs 2007 # Number of memory references committed 535system.cpu.commit.loads 961 # Number of loads committed 536system.cpu.commit.membars 7 # Number of memory barriers committed 537system.cpu.commit.branches 1037 # Number of branches committed 538system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 539system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 540system.cpu.commit.function_calls 103 # Number of function calls committed. 541system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 542system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction 543system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction 544system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction 545system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction 546system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction 547system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction 548system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction 549system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction 550system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 571system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 572system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 573system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 574system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 576system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached 577system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 578system.cpu.rob.rob_reads 21860 # The number of ROB reads 579system.cpu.rob.rob_writes 21470 # The number of ROB writes 580system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself 581system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling 582system.cpu.committedInsts 5792 # Number of Instructions Simulated 583system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 584system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction 585system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads 586system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle 587system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads 588system.cpu.int_regfile_reads 13744 # number of integer regfile reads 589system.cpu.int_regfile_writes 7176 # number of integer regfile writes 590system.cpu.fp_regfile_reads 25 # number of floating regfile reads 591system.cpu.fp_regfile_writes 2 # number of floating regfile writes 592system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 596system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) 599system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 600system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 601system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) 602system.cpu.toL2Bus.snoops 0 # Total snoops (count) 603system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 612system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram 614system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 620system.cpu.icache.tags.replacements 0 # number of replacements 621system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 632system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 633system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses 634system.cpu.icache.tags.data_accesses 4007 # Number of data accesses 635system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits 636system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits 637system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits 638system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits 639system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits 640system.cpu.icache.overall_hits::total 1391 # number of overall hits 641system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 642system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 643system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 644system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 645system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 646system.cpu.icache.overall_misses::total 438 # number of overall misses 647system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles 648system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles 649system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles 650system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles 651system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles 652system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles 653system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses 656system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses 657system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses 658system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses 659system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses 661system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses 662system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses 663system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses 664system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency 666system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency 667system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 668system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency 671system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked 672system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 674system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 675system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked 676system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu.icache.fast_writes 0 # number of fast writes performed 678system.cpu.icache.cache_copies 0 # number of cache copies performed 679system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 680system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 681system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 682system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 683system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 684system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits 685system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 686system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 687system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 688system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 689system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 690system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses 691system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses 698system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses 699system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses 700system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 709system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 710system.cpu.l2cache.tags.replacements 0 # number of replacements 711system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use 712system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. 715system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 722system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 724system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 725system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses 726system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses 727system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 728system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 729system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 730system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 731system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 732system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits 733system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 734system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 735system.cpu.l2cache.overall_hits::total 7 # number of overall hits 736system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses 737system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 738system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses 739system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 740system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 741system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 742system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 744system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 745system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 746system.cpu.l2cache.overall_misses::total 445 # number of overall misses 747system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles 748system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles 749system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles 750system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles 751system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles 752system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles 753system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles 754system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles 755system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles 756system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles 757system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles 758system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) 759system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 760system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 761system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 762system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 763system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses 769system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses 770system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses 771system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses 772system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 773system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 774system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 775system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses 777system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 778system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses 780system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency 781system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency 782system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency 784system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency 785system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency 791system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu.l2cache.fast_writes 0 # number of fast writes performed 798system.cpu.l2cache.cache_copies 0 # number of cache copies performed 799system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 800system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 801system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses 802system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 803system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 804system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 805system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 806system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 807system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 808system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 809system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 810system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles 811system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles 812system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles 813system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles 819system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles 820system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles 821system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses 822system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 823system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses 824system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 825system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 826system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 828system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses 829system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 831system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses 832system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency 833system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency 834system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency 835system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency 836system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency 837system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 838system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 839system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 840system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 841system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 842system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 843system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 844system.cpu.dcache.tags.replacements 0 # number of replacements 845system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use 846system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. 847system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 848system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. 849system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 850system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor 851system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy 852system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy 853system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 854system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 855system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id 856system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 857system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 858system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 859system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits 860system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits 861system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits 862system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits 863system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits 864system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits 865system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits 866system.cpu.dcache.overall_hits::total 2261 # number of overall hits 867system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 868system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 869system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 870system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 871system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses 872system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses 873system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses 874system.cpu.dcache.overall_misses::total 452 # number of overall misses 875system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles 876system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles 877system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles 878system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles 879system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles 880system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles 881system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles 882system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles 883system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) 884system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) 885system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 886system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 887system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 888system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 889system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 890system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses 891system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses 892system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses 893system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses 894system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses 895system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses 896system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses 897system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses 898system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses 899system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency 900system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency 901system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency 902system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency 903system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 904system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency 905system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 906system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency 907system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked 908system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 910system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 911system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked 912system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 913system.cpu.dcache.fast_writes 0 # number of fast writes performed 914system.cpu.dcache.cache_copies 0 # number of cache copies performed 915system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 916system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 917system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits 918system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits 919system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 920system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 921system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 922system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 923system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 924system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 925system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 926system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 927system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 928system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 929system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 930system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses 931system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles 932system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles 933system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles 934system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles 935system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles 936system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles 937system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles 938system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles 939system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses 940system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses 941system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 942system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 943system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses 944system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses 945system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses 946system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses 947system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency 948system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency 949system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency 950system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency 951system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 952system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 953system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 954system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 955system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 956 957---------- End Simulation Statistics ---------- 958