config.ini revision 8802:ef66a9083bc4
1[root] 2type=Root 3children=system 4time_sync_enable=false 5time_sync_period=100000000000 6time_sync_spin_threshold=100000000 7 8[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12memories=system.physmem 13num_work_ids=16 14physmem=system.physmem 15work_begin_ckpt_count=0 16work_begin_cpu_id_exit=-1 17work_begin_exit_count=0 18work_cpus_ckpt_count=0 19work_end_ckpt_count=0 20work_end_exit_count=0 21work_item_id=-1 22system_port=system.membus.port[0] 23 24[system.cpu] 25type=DerivO3CPU 26children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 27BTBEntries=4096 28BTBTagSize=16 29LFSTSize=1024 30LQEntries=32 31LSQCheckLoads=true 32LSQDepCheckShift=4 33RASSize=16 34SQEntries=32 35SSITSize=1024 36UnifiedTLB=true 37activity=0 38backComSize=5 39cachePorts=200 40checker=Null 41choiceCtrBits=2 42choicePredictorSize=8192 43clock=500 44commitToDecodeDelay=1 45commitToFetchDelay=1 46commitToIEWDelay=1 47commitToRenameDelay=1 48commitWidth=8 49cpu_id=0 50decodeToFetchDelay=1 51decodeToRenameDelay=1 52decodeWidth=8 53defer_registration=false 54dispatchWidth=8 55do_checkpoint_insts=true 56do_statistics_insts=true 57dtb=system.cpu.dtb 58fetchToDecodeDelay=1 59fetchTrapLatency=1 60fetchWidth=8 61forwardComSize=5 62fuPool=system.cpu.fuPool 63function_trace=false 64function_trace_start=0 65globalCtrBits=2 66globalHistoryBits=13 67globalPredictorSize=8192 68iewToCommitDelay=1 69iewToDecodeDelay=1 70iewToFetchDelay=1 71iewToRenameDelay=1 72instShiftAmt=2 73issueToExecuteDelay=1 74issueWidth=8 75itb=system.cpu.itb 76localCtrBits=2 77localHistoryBits=11 78localHistoryTableSize=2048 79localPredictorSize=2048 80max_insts_all_threads=0 81max_insts_any_thread=0 82max_loads_all_threads=0 83max_loads_any_thread=0 84numIQEntries=64 85numPhysFloatRegs=256 86numPhysIntRegs=256 87numROBEntries=192 88numRobs=1 89numThreads=1 90phase=0 91predType=tournament 92progress_interval=0 93renameToDecodeDelay=1 94renameToFetchDelay=1 95renameToIEWDelay=2 96renameToROBDelay=1 97renameWidth=8 98smtCommitPolicy=RoundRobin 99smtFetchPolicy=SingleThread 100smtIQPolicy=Partitioned 101smtIQThreshold=100 102smtLSQPolicy=Partitioned 103smtLSQThreshold=100 104smtNumFetchingThreads=1 105smtROBPolicy=Partitioned 106smtROBThreshold=100 107squashWidth=8 108store_set_clear_period=250000 109system=system 110tracer=system.cpu.tracer 111trapLatency=13 112wbDepth=1 113wbWidth=8 114workload=system.cpu.workload 115dcache_port=system.cpu.dcache.cpu_side 116icache_port=system.cpu.icache.cpu_side 117 118[system.cpu.dcache] 119type=BaseCache 120addr_range=0:18446744073709551615 121assoc=2 122block_size=64 123forward_snoops=true 124hash_delay=1 125is_top_level=true 126latency=1000 127max_miss_count=0 128mshrs=10 129num_cpus=1 130prefetch_data_accesses_only=false 131prefetch_degree=1 132prefetch_latency=10000 133prefetch_on_access=false 134prefetch_past_page=false 135prefetch_policy=none 136prefetch_serial_squash=false 137prefetch_use_cpu_id=true 138prefetcher_size=100 139prioritizeRequests=false 140repl=Null 141size=262144 142subblock_size=0 143tgts_per_mshr=20 144trace_addr=0 145two_queue=false 146write_buffers=8 147cpu_side=system.cpu.dcache_port 148mem_side=system.cpu.toL2Bus.port[1] 149 150[system.cpu.dtb] 151type=PowerTLB 152size=64 153 154[system.cpu.fuPool] 155type=FUPool 156children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 157FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 158 159[system.cpu.fuPool.FUList0] 160type=FUDesc 161children=opList 162count=6 163opList=system.cpu.fuPool.FUList0.opList 164 165[system.cpu.fuPool.FUList0.opList] 166type=OpDesc 167issueLat=1 168opClass=IntAlu 169opLat=1 170 171[system.cpu.fuPool.FUList1] 172type=FUDesc 173children=opList0 opList1 174count=2 175opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 176 177[system.cpu.fuPool.FUList1.opList0] 178type=OpDesc 179issueLat=1 180opClass=IntMult 181opLat=3 182 183[system.cpu.fuPool.FUList1.opList1] 184type=OpDesc 185issueLat=19 186opClass=IntDiv 187opLat=20 188 189[system.cpu.fuPool.FUList2] 190type=FUDesc 191children=opList0 opList1 opList2 192count=4 193opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 194 195[system.cpu.fuPool.FUList2.opList0] 196type=OpDesc 197issueLat=1 198opClass=FloatAdd 199opLat=2 200 201[system.cpu.fuPool.FUList2.opList1] 202type=OpDesc 203issueLat=1 204opClass=FloatCmp 205opLat=2 206 207[system.cpu.fuPool.FUList2.opList2] 208type=OpDesc 209issueLat=1 210opClass=FloatCvt 211opLat=2 212 213[system.cpu.fuPool.FUList3] 214type=FUDesc 215children=opList0 opList1 opList2 216count=2 217opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 218 219[system.cpu.fuPool.FUList3.opList0] 220type=OpDesc 221issueLat=1 222opClass=FloatMult 223opLat=4 224 225[system.cpu.fuPool.FUList3.opList1] 226type=OpDesc 227issueLat=12 228opClass=FloatDiv 229opLat=12 230 231[system.cpu.fuPool.FUList3.opList2] 232type=OpDesc 233issueLat=24 234opClass=FloatSqrt 235opLat=24 236 237[system.cpu.fuPool.FUList4] 238type=FUDesc 239children=opList 240count=0 241opList=system.cpu.fuPool.FUList4.opList 242 243[system.cpu.fuPool.FUList4.opList] 244type=OpDesc 245issueLat=1 246opClass=MemRead 247opLat=1 248 249[system.cpu.fuPool.FUList5] 250type=FUDesc 251children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 252count=4 253opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 254 255[system.cpu.fuPool.FUList5.opList00] 256type=OpDesc 257issueLat=1 258opClass=SimdAdd 259opLat=1 260 261[system.cpu.fuPool.FUList5.opList01] 262type=OpDesc 263issueLat=1 264opClass=SimdAddAcc 265opLat=1 266 267[system.cpu.fuPool.FUList5.opList02] 268type=OpDesc 269issueLat=1 270opClass=SimdAlu 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList03] 274type=OpDesc 275issueLat=1 276opClass=SimdCmp 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList04] 280type=OpDesc 281issueLat=1 282opClass=SimdCvt 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList05] 286type=OpDesc 287issueLat=1 288opClass=SimdMisc 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList06] 292type=OpDesc 293issueLat=1 294opClass=SimdMult 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList07] 298type=OpDesc 299issueLat=1 300opClass=SimdMultAcc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList08] 304type=OpDesc 305issueLat=1 306opClass=SimdShift 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList09] 310type=OpDesc 311issueLat=1 312opClass=SimdShiftAcc 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList10] 316type=OpDesc 317issueLat=1 318opClass=SimdSqrt 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList11] 322type=OpDesc 323issueLat=1 324opClass=SimdFloatAdd 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList12] 328type=OpDesc 329issueLat=1 330opClass=SimdFloatAlu 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList13] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatCmp 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList14] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatCvt 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList15] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatDiv 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList16] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatMisc 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList17] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatMult 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList18] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMultAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList19] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatSqrt 373opLat=1 374 375[system.cpu.fuPool.FUList6] 376type=FUDesc 377children=opList 378count=0 379opList=system.cpu.fuPool.FUList6.opList 380 381[system.cpu.fuPool.FUList6.opList] 382type=OpDesc 383issueLat=1 384opClass=MemWrite 385opLat=1 386 387[system.cpu.fuPool.FUList7] 388type=FUDesc 389children=opList0 opList1 390count=4 391opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 392 393[system.cpu.fuPool.FUList7.opList0] 394type=OpDesc 395issueLat=1 396opClass=MemRead 397opLat=1 398 399[system.cpu.fuPool.FUList7.opList1] 400type=OpDesc 401issueLat=1 402opClass=MemWrite 403opLat=1 404 405[system.cpu.fuPool.FUList8] 406type=FUDesc 407children=opList 408count=1 409opList=system.cpu.fuPool.FUList8.opList 410 411[system.cpu.fuPool.FUList8.opList] 412type=OpDesc 413issueLat=3 414opClass=IprAccess 415opLat=3 416 417[system.cpu.icache] 418type=BaseCache 419addr_range=0:18446744073709551615 420assoc=2 421block_size=64 422forward_snoops=true 423hash_delay=1 424is_top_level=true 425latency=1000 426max_miss_count=0 427mshrs=10 428num_cpus=1 429prefetch_data_accesses_only=false 430prefetch_degree=1 431prefetch_latency=10000 432prefetch_on_access=false 433prefetch_past_page=false 434prefetch_policy=none 435prefetch_serial_squash=false 436prefetch_use_cpu_id=true 437prefetcher_size=100 438prioritizeRequests=false 439repl=Null 440size=131072 441subblock_size=0 442tgts_per_mshr=20 443trace_addr=0 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.port[0] 448 449[system.cpu.itb] 450type=PowerTLB 451size=64 452 453[system.cpu.l2cache] 454type=BaseCache 455addr_range=0:18446744073709551615 456assoc=2 457block_size=64 458forward_snoops=true 459hash_delay=1 460is_top_level=false 461latency=1000 462max_miss_count=0 463mshrs=10 464num_cpus=1 465prefetch_data_accesses_only=false 466prefetch_degree=1 467prefetch_latency=10000 468prefetch_on_access=false 469prefetch_past_page=false 470prefetch_policy=none 471prefetch_serial_squash=false 472prefetch_use_cpu_id=true 473prefetcher_size=100 474prioritizeRequests=false 475repl=Null 476size=2097152 477subblock_size=0 478tgts_per_mshr=5 479trace_addr=0 480two_queue=false 481write_buffers=8 482cpu_side=system.cpu.toL2Bus.port[2] 483mem_side=system.membus.port[2] 484 485[system.cpu.toL2Bus] 486type=Bus 487block_size=64 488bus_id=0 489clock=1000 490header_cycles=1 491use_default_range=false 492width=64 493port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 494 495[system.cpu.tracer] 496type=ExeTracer 497 498[system.cpu.workload] 499type=LiveProcess 500cmd=hello 501cwd= 502egid=100 503env= 504errout=cerr 505euid=100 506executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello 507gid=100 508input=cin 509max_stack_size=67108864 510output=cout 511pid=100 512ppid=99 513simpoint=0 514system=system 515uid=100 516 517[system.membus] 518type=Bus 519block_size=64 520bus_id=0 521clock=1000 522header_cycles=1 523use_default_range=false 524width=64 525port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 526 527[system.physmem] 528type=PhysicalMemory 529file= 530latency=30000 531latency_var=0 532null=false 533range=0:134217727 534zero=false 535port=system.membus.port[1] 536 537