config.ini revision 11440
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60UnifiedTLB=true 61activity=0 62backComSize=5 63branchPred=system.cpu.branchPred 64cachePorts=200 65checker=Null 66clk_domain=system.cpu_clk_domain 67commitToDecodeDelay=1 68commitToFetchDelay=1 69commitToIEWDelay=1 70commitToRenameDelay=1 71commitWidth=8 72cpu_id=0 73decodeToFetchDelay=1 74decodeToRenameDelay=1 75decodeWidth=8 76dispatchWidth=8 77do_checkpoint_insts=true 78do_quiesce=true 79do_statistics_insts=true 80dtb=system.cpu.dtb 81eventq_index=0 82fetchBufferSize=64 83fetchQueueSize=32 84fetchToDecodeDelay=1 85fetchTrapLatency=1 86fetchWidth=8 87forwardComSize=5 88fuPool=system.cpu.fuPool 89function_trace=false 90function_trace_start=0 91iewToCommitDelay=1 92iewToDecodeDelay=1 93iewToFetchDelay=1 94iewToRenameDelay=1 95interrupts=system.cpu.interrupts 96isa=system.cpu.isa 97issueToExecuteDelay=1 98issueWidth=8 99itb=system.cpu.itb 100max_insts_all_threads=0 101max_insts_any_thread=0 102max_loads_all_threads=0 103max_loads_any_thread=0 104needsTSO=false 105numIQEntries=64 106numPhysCCRegs=0 107numPhysFloatRegs=256 108numPhysIntRegs=256 109numROBEntries=192 110numRobs=1 111numThreads=1 112profile=0 113progress_interval=0 114renameToDecodeDelay=1 115renameToFetchDelay=1 116renameToIEWDelay=2 117renameToROBDelay=1 118renameWidth=8 119simpoint_start_insts= 120smtCommitPolicy=RoundRobin 121smtFetchPolicy=SingleThread 122smtIQPolicy=Partitioned 123smtIQThreshold=100 124smtLSQPolicy=Partitioned 125smtLSQThreshold=100 126smtNumFetchingThreads=1 127smtROBPolicy=Partitioned 128smtROBThreshold=100 129socket_id=0 130squashWidth=8 131store_set_clear_period=250000 132switched_out=false 133system=system 134tracer=system.cpu.tracer 135trapLatency=13 136wbWidth=8 137workload=system.cpu.workload 138dcache_port=system.cpu.dcache.cpu_side 139icache_port=system.cpu.icache.cpu_side 140 141[system.cpu.branchPred] 142type=TournamentBP 143BTBEntries=4096 144BTBTagSize=16 145RASSize=16 146choiceCtrBits=2 147choicePredictorSize=8192 148eventq_index=0 149globalCtrBits=2 150globalPredictorSize=8192 151indirectHashGHR=true 152indirectHashTargets=true 153indirectPathLength=3 154indirectSets=256 155indirectTagSize=16 156indirectWays=2 157instShiftAmt=2 158localCtrBits=2 159localHistoryTableSize=2048 160localPredictorSize=2048 161numThreads=1 162useIndirect=true 163 164[system.cpu.dcache] 165type=Cache 166children=tags 167addr_ranges=0:18446744073709551615 168assoc=2 169clk_domain=system.cpu_clk_domain 170clusivity=mostly_incl 171demand_mshr_reserve=1 172eventq_index=0 173hit_latency=2 174is_read_only=false 175max_miss_count=0 176mshrs=4 177prefetch_on_access=false 178prefetcher=Null 179response_latency=2 180sequential_access=false 181size=262144 182system=system 183tags=system.cpu.dcache.tags 184tgts_per_mshr=20 185write_buffers=8 186writeback_clean=false 187cpu_side=system.cpu.dcache_port 188mem_side=system.cpu.toL2Bus.slave[1] 189 190[system.cpu.dcache.tags] 191type=LRU 192assoc=2 193block_size=64 194clk_domain=system.cpu_clk_domain 195eventq_index=0 196hit_latency=2 197sequential_access=false 198size=262144 199 200[system.cpu.dtb] 201type=PowerTLB 202eventq_index=0 203size=64 204 205[system.cpu.fuPool] 206type=FUPool 207children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 208FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 209eventq_index=0 210 211[system.cpu.fuPool.FUList0] 212type=FUDesc 213children=opList 214count=6 215eventq_index=0 216opList=system.cpu.fuPool.FUList0.opList 217 218[system.cpu.fuPool.FUList0.opList] 219type=OpDesc 220eventq_index=0 221opClass=IntAlu 222opLat=1 223pipelined=true 224 225[system.cpu.fuPool.FUList1] 226type=FUDesc 227children=opList0 opList1 228count=2 229eventq_index=0 230opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 231 232[system.cpu.fuPool.FUList1.opList0] 233type=OpDesc 234eventq_index=0 235opClass=IntMult 236opLat=3 237pipelined=true 238 239[system.cpu.fuPool.FUList1.opList1] 240type=OpDesc 241eventq_index=0 242opClass=IntDiv 243opLat=20 244pipelined=false 245 246[system.cpu.fuPool.FUList2] 247type=FUDesc 248children=opList0 opList1 opList2 249count=4 250eventq_index=0 251opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 252 253[system.cpu.fuPool.FUList2.opList0] 254type=OpDesc 255eventq_index=0 256opClass=FloatAdd 257opLat=2 258pipelined=true 259 260[system.cpu.fuPool.FUList2.opList1] 261type=OpDesc 262eventq_index=0 263opClass=FloatCmp 264opLat=2 265pipelined=true 266 267[system.cpu.fuPool.FUList2.opList2] 268type=OpDesc 269eventq_index=0 270opClass=FloatCvt 271opLat=2 272pipelined=true 273 274[system.cpu.fuPool.FUList3] 275type=FUDesc 276children=opList0 opList1 opList2 277count=2 278eventq_index=0 279opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 280 281[system.cpu.fuPool.FUList3.opList0] 282type=OpDesc 283eventq_index=0 284opClass=FloatMult 285opLat=4 286pipelined=true 287 288[system.cpu.fuPool.FUList3.opList1] 289type=OpDesc 290eventq_index=0 291opClass=FloatDiv 292opLat=12 293pipelined=false 294 295[system.cpu.fuPool.FUList3.opList2] 296type=OpDesc 297eventq_index=0 298opClass=FloatSqrt 299opLat=24 300pipelined=false 301 302[system.cpu.fuPool.FUList4] 303type=FUDesc 304children=opList 305count=0 306eventq_index=0 307opList=system.cpu.fuPool.FUList4.opList 308 309[system.cpu.fuPool.FUList4.opList] 310type=OpDesc 311eventq_index=0 312opClass=MemRead 313opLat=1 314pipelined=true 315 316[system.cpu.fuPool.FUList5] 317type=FUDesc 318children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 319count=4 320eventq_index=0 321opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 322 323[system.cpu.fuPool.FUList5.opList00] 324type=OpDesc 325eventq_index=0 326opClass=SimdAdd 327opLat=1 328pipelined=true 329 330[system.cpu.fuPool.FUList5.opList01] 331type=OpDesc 332eventq_index=0 333opClass=SimdAddAcc 334opLat=1 335pipelined=true 336 337[system.cpu.fuPool.FUList5.opList02] 338type=OpDesc 339eventq_index=0 340opClass=SimdAlu 341opLat=1 342pipelined=true 343 344[system.cpu.fuPool.FUList5.opList03] 345type=OpDesc 346eventq_index=0 347opClass=SimdCmp 348opLat=1 349pipelined=true 350 351[system.cpu.fuPool.FUList5.opList04] 352type=OpDesc 353eventq_index=0 354opClass=SimdCvt 355opLat=1 356pipelined=true 357 358[system.cpu.fuPool.FUList5.opList05] 359type=OpDesc 360eventq_index=0 361opClass=SimdMisc 362opLat=1 363pipelined=true 364 365[system.cpu.fuPool.FUList5.opList06] 366type=OpDesc 367eventq_index=0 368opClass=SimdMult 369opLat=1 370pipelined=true 371 372[system.cpu.fuPool.FUList5.opList07] 373type=OpDesc 374eventq_index=0 375opClass=SimdMultAcc 376opLat=1 377pipelined=true 378 379[system.cpu.fuPool.FUList5.opList08] 380type=OpDesc 381eventq_index=0 382opClass=SimdShift 383opLat=1 384pipelined=true 385 386[system.cpu.fuPool.FUList5.opList09] 387type=OpDesc 388eventq_index=0 389opClass=SimdShiftAcc 390opLat=1 391pipelined=true 392 393[system.cpu.fuPool.FUList5.opList10] 394type=OpDesc 395eventq_index=0 396opClass=SimdSqrt 397opLat=1 398pipelined=true 399 400[system.cpu.fuPool.FUList5.opList11] 401type=OpDesc 402eventq_index=0 403opClass=SimdFloatAdd 404opLat=1 405pipelined=true 406 407[system.cpu.fuPool.FUList5.opList12] 408type=OpDesc 409eventq_index=0 410opClass=SimdFloatAlu 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList5.opList13] 415type=OpDesc 416eventq_index=0 417opClass=SimdFloatCmp 418opLat=1 419pipelined=true 420 421[system.cpu.fuPool.FUList5.opList14] 422type=OpDesc 423eventq_index=0 424opClass=SimdFloatCvt 425opLat=1 426pipelined=true 427 428[system.cpu.fuPool.FUList5.opList15] 429type=OpDesc 430eventq_index=0 431opClass=SimdFloatDiv 432opLat=1 433pipelined=true 434 435[system.cpu.fuPool.FUList5.opList16] 436type=OpDesc 437eventq_index=0 438opClass=SimdFloatMisc 439opLat=1 440pipelined=true 441 442[system.cpu.fuPool.FUList5.opList17] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatMult 446opLat=1 447pipelined=true 448 449[system.cpu.fuPool.FUList5.opList18] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatMultAcc 453opLat=1 454pipelined=true 455 456[system.cpu.fuPool.FUList5.opList19] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatSqrt 460opLat=1 461pipelined=true 462 463[system.cpu.fuPool.FUList6] 464type=FUDesc 465children=opList 466count=0 467eventq_index=0 468opList=system.cpu.fuPool.FUList6.opList 469 470[system.cpu.fuPool.FUList6.opList] 471type=OpDesc 472eventq_index=0 473opClass=MemWrite 474opLat=1 475pipelined=true 476 477[system.cpu.fuPool.FUList7] 478type=FUDesc 479children=opList0 opList1 480count=4 481eventq_index=0 482opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 483 484[system.cpu.fuPool.FUList7.opList0] 485type=OpDesc 486eventq_index=0 487opClass=MemRead 488opLat=1 489pipelined=true 490 491[system.cpu.fuPool.FUList7.opList1] 492type=OpDesc 493eventq_index=0 494opClass=MemWrite 495opLat=1 496pipelined=true 497 498[system.cpu.fuPool.FUList8] 499type=FUDesc 500children=opList 501count=1 502eventq_index=0 503opList=system.cpu.fuPool.FUList8.opList 504 505[system.cpu.fuPool.FUList8.opList] 506type=OpDesc 507eventq_index=0 508opClass=IprAccess 509opLat=3 510pipelined=false 511 512[system.cpu.icache] 513type=Cache 514children=tags 515addr_ranges=0:18446744073709551615 516assoc=2 517clk_domain=system.cpu_clk_domain 518clusivity=mostly_incl 519demand_mshr_reserve=1 520eventq_index=0 521hit_latency=2 522is_read_only=true 523max_miss_count=0 524mshrs=4 525prefetch_on_access=false 526prefetcher=Null 527response_latency=2 528sequential_access=false 529size=131072 530system=system 531tags=system.cpu.icache.tags 532tgts_per_mshr=20 533write_buffers=8 534writeback_clean=true 535cpu_side=system.cpu.icache_port 536mem_side=system.cpu.toL2Bus.slave[0] 537 538[system.cpu.icache.tags] 539type=LRU 540assoc=2 541block_size=64 542clk_domain=system.cpu_clk_domain 543eventq_index=0 544hit_latency=2 545sequential_access=false 546size=131072 547 548[system.cpu.interrupts] 549type=PowerInterrupts 550eventq_index=0 551 552[system.cpu.isa] 553type=PowerISA 554eventq_index=0 555 556[system.cpu.itb] 557type=PowerTLB 558eventq_index=0 559size=64 560 561[system.cpu.l2cache] 562type=Cache 563children=tags 564addr_ranges=0:18446744073709551615 565assoc=8 566clk_domain=system.cpu_clk_domain 567clusivity=mostly_incl 568demand_mshr_reserve=1 569eventq_index=0 570hit_latency=20 571is_read_only=false 572max_miss_count=0 573mshrs=20 574prefetch_on_access=false 575prefetcher=Null 576response_latency=20 577sequential_access=false 578size=2097152 579system=system 580tags=system.cpu.l2cache.tags 581tgts_per_mshr=12 582write_buffers=8 583writeback_clean=false 584cpu_side=system.cpu.toL2Bus.master[0] 585mem_side=system.membus.slave[1] 586 587[system.cpu.l2cache.tags] 588type=LRU 589assoc=8 590block_size=64 591clk_domain=system.cpu_clk_domain 592eventq_index=0 593hit_latency=20 594sequential_access=false 595size=2097152 596 597[system.cpu.toL2Bus] 598type=CoherentXBar 599children=snoop_filter 600clk_domain=system.cpu_clk_domain 601eventq_index=0 602forward_latency=0 603frontend_latency=1 604point_of_coherency=false 605response_latency=1 606snoop_filter=system.cpu.toL2Bus.snoop_filter 607snoop_response_latency=1 608system=system 609use_default_range=false 610width=32 611master=system.cpu.l2cache.cpu_side 612slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 613 614[system.cpu.toL2Bus.snoop_filter] 615type=SnoopFilter 616eventq_index=0 617lookup_latency=0 618max_capacity=8388608 619system=system 620 621[system.cpu.tracer] 622type=ExeTracer 623eventq_index=0 624 625[system.cpu.workload] 626type=LiveProcess 627cmd=hello 628cwd= 629drivers= 630egid=100 631env= 632errout=cerr 633euid=100 634eventq_index=0 635executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello 636gid=100 637input=cin 638kvmInSE=false 639max_stack_size=67108864 640output=cout 641pid=100 642ppid=99 643simpoint=0 644system=system 645uid=100 646useArchPT=false 647 648[system.cpu_clk_domain] 649type=SrcClockDomain 650clock=500 651domain_id=-1 652eventq_index=0 653init_perf_level=0 654voltage_domain=system.voltage_domain 655 656[system.dvfs_handler] 657type=DVFSHandler 658domains= 659enable=false 660eventq_index=0 661sys_clk_domain=system.clk_domain 662transition_latency=100000000 663 664[system.membus] 665type=CoherentXBar 666clk_domain=system.clk_domain 667eventq_index=0 668forward_latency=4 669frontend_latency=3 670point_of_coherency=true 671response_latency=2 672snoop_filter=Null 673snoop_response_latency=4 674system=system 675use_default_range=false 676width=16 677master=system.physmem.port 678slave=system.system_port system.cpu.l2cache.mem_side 679 680[system.physmem] 681type=DRAMCtrl 682IDD0=0.075000 683IDD02=0.000000 684IDD2N=0.050000 685IDD2N2=0.000000 686IDD2P0=0.000000 687IDD2P02=0.000000 688IDD2P1=0.000000 689IDD2P12=0.000000 690IDD3N=0.057000 691IDD3N2=0.000000 692IDD3P0=0.000000 693IDD3P02=0.000000 694IDD3P1=0.000000 695IDD3P12=0.000000 696IDD4R=0.187000 697IDD4R2=0.000000 698IDD4W=0.165000 699IDD4W2=0.000000 700IDD5=0.220000 701IDD52=0.000000 702IDD6=0.000000 703IDD62=0.000000 704VDD=1.500000 705VDD2=0.000000 706activation_limit=4 707addr_mapping=RoRaBaCoCh 708bank_groups_per_rank=0 709banks_per_rank=8 710burst_length=8 711channels=1 712clk_domain=system.clk_domain 713conf_table_reported=true 714device_bus_width=8 715device_rowbuffer_size=1024 716device_size=536870912 717devices_per_rank=8 718dll=true 719eventq_index=0 720in_addr_map=true 721max_accesses_per_row=16 722mem_sched_policy=frfcfs 723min_writes_per_switch=16 724null=false 725page_policy=open_adaptive 726range=0:134217727 727ranks_per_channel=2 728read_buffer_size=32 729static_backend_latency=10000 730static_frontend_latency=10000 731tBURST=5000 732tCCD_L=0 733tCK=1250 734tCL=13750 735tCS=2500 736tRAS=35000 737tRCD=13750 738tREFI=7800000 739tRFC=260000 740tRP=13750 741tRRD=6000 742tRRD_L=0 743tRTP=7500 744tRTW=2500 745tWR=15000 746tWTR=7500 747tXAW=30000 748tXP=0 749tXPDLL=0 750tXS=0 751tXSDLL=0 752write_buffer_size=64 753write_high_thresh_perc=85 754write_low_thresh_perc=50 755port=system.membus.master[0] 756 757[system.voltage_domain] 758type=VoltageDomain 759eventq_index=0 760voltage=1.000000 761 762