config.ini revision 11312:3d7a85d71bd1
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 30readfile= 31symbolfile= 32work_begin_ckpt_count=0 33work_begin_cpu_id_exit=-1 34work_begin_exit_count=0 35work_cpus_ckpt_count=0 36work_end_ckpt_count=0 37work_end_exit_count=0 38work_item_id=-1 39system_port=system.membus.slave[0] 40 41[system.clk_domain] 42type=SrcClockDomain 43clock=1000 44domain_id=-1 45eventq_index=0 46init_perf_level=0 47voltage_domain=system.voltage_domain 48 49[system.cpu] 50type=DerivO3CPU 51children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 52LFSTSize=1024 53LQEntries=32 54LSQCheckLoads=true 55LSQDepCheckShift=4 56SQEntries=32 57SSITSize=1024 58UnifiedTLB=true 59activity=0 60backComSize=5 61branchPred=system.cpu.branchPred 62cachePorts=200 63checker=Null 64clk_domain=system.cpu_clk_domain 65commitToDecodeDelay=1 66commitToFetchDelay=1 67commitToIEWDelay=1 68commitToRenameDelay=1 69commitWidth=8 70cpu_id=0 71decodeToFetchDelay=1 72decodeToRenameDelay=1 73decodeWidth=8 74dispatchWidth=8 75do_checkpoint_insts=true 76do_quiesce=true 77do_statistics_insts=true 78dtb=system.cpu.dtb 79eventq_index=0 80fetchBufferSize=64 81fetchQueueSize=32 82fetchToDecodeDelay=1 83fetchTrapLatency=1 84fetchWidth=8 85forwardComSize=5 86fuPool=system.cpu.fuPool 87function_trace=false 88function_trace_start=0 89iewToCommitDelay=1 90iewToDecodeDelay=1 91iewToFetchDelay=1 92iewToRenameDelay=1 93interrupts=system.cpu.interrupts 94isa=system.cpu.isa 95issueToExecuteDelay=1 96issueWidth=8 97itb=system.cpu.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=64 104numPhysCCRegs=0 105numPhysFloatRegs=256 106numPhysIntRegs=256 107numROBEntries=192 108numRobs=1 109numThreads=1 110profile=0 111progress_interval=0 112renameToDecodeDelay=1 113renameToFetchDelay=1 114renameToIEWDelay=2 115renameToROBDelay=1 116renameWidth=8 117simpoint_start_insts= 118smtCommitPolicy=RoundRobin 119smtFetchPolicy=SingleThread 120smtIQPolicy=Partitioned 121smtIQThreshold=100 122smtLSQPolicy=Partitioned 123smtLSQThreshold=100 124smtNumFetchingThreads=1 125smtROBPolicy=Partitioned 126smtROBThreshold=100 127socket_id=0 128squashWidth=8 129store_set_clear_period=250000 130switched_out=false 131system=system 132tracer=system.cpu.tracer 133trapLatency=13 134wbWidth=8 135workload=system.cpu.workload 136dcache_port=system.cpu.dcache.cpu_side 137icache_port=system.cpu.icache.cpu_side 138 139[system.cpu.branchPred] 140type=TournamentBP 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 146eventq_index=0 147globalCtrBits=2 148globalPredictorSize=8192 149instShiftAmt=2 150localCtrBits=2 151localHistoryTableSize=2048 152localPredictorSize=2048 153numThreads=1 154 155[system.cpu.dcache] 156type=Cache 157children=tags 158addr_ranges=0:18446744073709551615 159assoc=2 160clk_domain=system.cpu_clk_domain 161clusivity=mostly_incl 162demand_mshr_reserve=1 163eventq_index=0 164forward_snoops=true 165hit_latency=2 166is_read_only=false 167max_miss_count=0 168mshrs=4 169prefetch_on_access=false 170prefetcher=Null 171response_latency=2 172sequential_access=false 173size=262144 174system=system 175tags=system.cpu.dcache.tags 176tgts_per_mshr=20 177write_buffers=8 178writeback_clean=false 179cpu_side=system.cpu.dcache_port 180mem_side=system.cpu.toL2Bus.slave[1] 181 182[system.cpu.dcache.tags] 183type=LRU 184assoc=2 185block_size=64 186clk_domain=system.cpu_clk_domain 187eventq_index=0 188hit_latency=2 189sequential_access=false 190size=262144 191 192[system.cpu.dtb] 193type=PowerTLB 194eventq_index=0 195size=64 196 197[system.cpu.fuPool] 198type=FUPool 199children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 200FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 201eventq_index=0 202 203[system.cpu.fuPool.FUList0] 204type=FUDesc 205children=opList 206count=6 207eventq_index=0 208opList=system.cpu.fuPool.FUList0.opList 209 210[system.cpu.fuPool.FUList0.opList] 211type=OpDesc 212eventq_index=0 213opClass=IntAlu 214opLat=1 215pipelined=true 216 217[system.cpu.fuPool.FUList1] 218type=FUDesc 219children=opList0 opList1 220count=2 221eventq_index=0 222opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 223 224[system.cpu.fuPool.FUList1.opList0] 225type=OpDesc 226eventq_index=0 227opClass=IntMult 228opLat=3 229pipelined=true 230 231[system.cpu.fuPool.FUList1.opList1] 232type=OpDesc 233eventq_index=0 234opClass=IntDiv 235opLat=20 236pipelined=false 237 238[system.cpu.fuPool.FUList2] 239type=FUDesc 240children=opList0 opList1 opList2 241count=4 242eventq_index=0 243opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 244 245[system.cpu.fuPool.FUList2.opList0] 246type=OpDesc 247eventq_index=0 248opClass=FloatAdd 249opLat=2 250pipelined=true 251 252[system.cpu.fuPool.FUList2.opList1] 253type=OpDesc 254eventq_index=0 255opClass=FloatCmp 256opLat=2 257pipelined=true 258 259[system.cpu.fuPool.FUList2.opList2] 260type=OpDesc 261eventq_index=0 262opClass=FloatCvt 263opLat=2 264pipelined=true 265 266[system.cpu.fuPool.FUList3] 267type=FUDesc 268children=opList0 opList1 opList2 269count=2 270eventq_index=0 271opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 272 273[system.cpu.fuPool.FUList3.opList0] 274type=OpDesc 275eventq_index=0 276opClass=FloatMult 277opLat=4 278pipelined=true 279 280[system.cpu.fuPool.FUList3.opList1] 281type=OpDesc 282eventq_index=0 283opClass=FloatDiv 284opLat=12 285pipelined=false 286 287[system.cpu.fuPool.FUList3.opList2] 288type=OpDesc 289eventq_index=0 290opClass=FloatSqrt 291opLat=24 292pipelined=false 293 294[system.cpu.fuPool.FUList4] 295type=FUDesc 296children=opList 297count=0 298eventq_index=0 299opList=system.cpu.fuPool.FUList4.opList 300 301[system.cpu.fuPool.FUList4.opList] 302type=OpDesc 303eventq_index=0 304opClass=MemRead 305opLat=1 306pipelined=true 307 308[system.cpu.fuPool.FUList5] 309type=FUDesc 310children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 311count=4 312eventq_index=0 313opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 314 315[system.cpu.fuPool.FUList5.opList00] 316type=OpDesc 317eventq_index=0 318opClass=SimdAdd 319opLat=1 320pipelined=true 321 322[system.cpu.fuPool.FUList5.opList01] 323type=OpDesc 324eventq_index=0 325opClass=SimdAddAcc 326opLat=1 327pipelined=true 328 329[system.cpu.fuPool.FUList5.opList02] 330type=OpDesc 331eventq_index=0 332opClass=SimdAlu 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5.opList03] 337type=OpDesc 338eventq_index=0 339opClass=SimdCmp 340opLat=1 341pipelined=true 342 343[system.cpu.fuPool.FUList5.opList04] 344type=OpDesc 345eventq_index=0 346opClass=SimdCvt 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList05] 351type=OpDesc 352eventq_index=0 353opClass=SimdMisc 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList06] 358type=OpDesc 359eventq_index=0 360opClass=SimdMult 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList07] 365type=OpDesc 366eventq_index=0 367opClass=SimdMultAcc 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList08] 372type=OpDesc 373eventq_index=0 374opClass=SimdShift 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList09] 379type=OpDesc 380eventq_index=0 381opClass=SimdShiftAcc 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList10] 386type=OpDesc 387eventq_index=0 388opClass=SimdSqrt 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList11] 393type=OpDesc 394eventq_index=0 395opClass=SimdFloatAdd 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList12] 400type=OpDesc 401eventq_index=0 402opClass=SimdFloatAlu 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList13] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatCmp 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList14] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatCvt 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList15] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatDiv 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList16] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatMisc 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList17] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatMult 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList18] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMultAcc 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList19] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatSqrt 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList6] 456type=FUDesc 457children=opList 458count=0 459eventq_index=0 460opList=system.cpu.fuPool.FUList6.opList 461 462[system.cpu.fuPool.FUList6.opList] 463type=OpDesc 464eventq_index=0 465opClass=MemWrite 466opLat=1 467pipelined=true 468 469[system.cpu.fuPool.FUList7] 470type=FUDesc 471children=opList0 opList1 472count=4 473eventq_index=0 474opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 475 476[system.cpu.fuPool.FUList7.opList0] 477type=OpDesc 478eventq_index=0 479opClass=MemRead 480opLat=1 481pipelined=true 482 483[system.cpu.fuPool.FUList7.opList1] 484type=OpDesc 485eventq_index=0 486opClass=MemWrite 487opLat=1 488pipelined=true 489 490[system.cpu.fuPool.FUList8] 491type=FUDesc 492children=opList 493count=1 494eventq_index=0 495opList=system.cpu.fuPool.FUList8.opList 496 497[system.cpu.fuPool.FUList8.opList] 498type=OpDesc 499eventq_index=0 500opClass=IprAccess 501opLat=3 502pipelined=false 503 504[system.cpu.icache] 505type=Cache 506children=tags 507addr_ranges=0:18446744073709551615 508assoc=2 509clk_domain=system.cpu_clk_domain 510clusivity=mostly_incl 511demand_mshr_reserve=1 512eventq_index=0 513forward_snoops=true 514hit_latency=2 515is_read_only=true 516max_miss_count=0 517mshrs=4 518prefetch_on_access=false 519prefetcher=Null 520response_latency=2 521sequential_access=false 522size=131072 523system=system 524tags=system.cpu.icache.tags 525tgts_per_mshr=20 526write_buffers=8 527writeback_clean=true 528cpu_side=system.cpu.icache_port 529mem_side=system.cpu.toL2Bus.slave[0] 530 531[system.cpu.icache.tags] 532type=LRU 533assoc=2 534block_size=64 535clk_domain=system.cpu_clk_domain 536eventq_index=0 537hit_latency=2 538sequential_access=false 539size=131072 540 541[system.cpu.interrupts] 542type=PowerInterrupts 543eventq_index=0 544 545[system.cpu.isa] 546type=PowerISA 547eventq_index=0 548 549[system.cpu.itb] 550type=PowerTLB 551eventq_index=0 552size=64 553 554[system.cpu.l2cache] 555type=Cache 556children=tags 557addr_ranges=0:18446744073709551615 558assoc=8 559clk_domain=system.cpu_clk_domain 560clusivity=mostly_incl 561demand_mshr_reserve=1 562eventq_index=0 563forward_snoops=true 564hit_latency=20 565is_read_only=false 566max_miss_count=0 567mshrs=20 568prefetch_on_access=false 569prefetcher=Null 570response_latency=20 571sequential_access=false 572size=2097152 573system=system 574tags=system.cpu.l2cache.tags 575tgts_per_mshr=12 576write_buffers=8 577writeback_clean=false 578cpu_side=system.cpu.toL2Bus.master[0] 579mem_side=system.membus.slave[1] 580 581[system.cpu.l2cache.tags] 582type=LRU 583assoc=8 584block_size=64 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587hit_latency=20 588sequential_access=false 589size=2097152 590 591[system.cpu.toL2Bus] 592type=CoherentXBar 593children=snoop_filter 594clk_domain=system.cpu_clk_domain 595eventq_index=0 596forward_latency=0 597frontend_latency=1 598response_latency=1 599snoop_filter=system.cpu.toL2Bus.snoop_filter 600snoop_response_latency=1 601system=system 602use_default_range=false 603width=32 604master=system.cpu.l2cache.cpu_side 605slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 606 607[system.cpu.toL2Bus.snoop_filter] 608type=SnoopFilter 609eventq_index=0 610lookup_latency=0 611max_capacity=8388608 612system=system 613 614[system.cpu.tracer] 615type=ExeTracer 616eventq_index=0 617 618[system.cpu.workload] 619type=LiveProcess 620cmd=hello 621cwd= 622drivers= 623egid=100 624env= 625errout=cerr 626euid=100 627eventq_index=0 628executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello 629gid=100 630input=cin 631kvmInSE=false 632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=0 637system=system 638uid=100 639useArchPT=false 640 641[system.cpu_clk_domain] 642type=SrcClockDomain 643clock=500 644domain_id=-1 645eventq_index=0 646init_perf_level=0 647voltage_domain=system.voltage_domain 648 649[system.dvfs_handler] 650type=DVFSHandler 651domains= 652enable=false 653eventq_index=0 654sys_clk_domain=system.clk_domain 655transition_latency=100000000 656 657[system.membus] 658type=CoherentXBar 659clk_domain=system.clk_domain 660eventq_index=0 661forward_latency=4 662frontend_latency=3 663response_latency=2 664snoop_filter=Null 665snoop_response_latency=4 666system=system 667use_default_range=false 668width=16 669master=system.physmem.port 670slave=system.system_port system.cpu.l2cache.mem_side 671 672[system.physmem] 673type=DRAMCtrl 674IDD0=0.075000 675IDD02=0.000000 676IDD2N=0.050000 677IDD2N2=0.000000 678IDD2P0=0.000000 679IDD2P02=0.000000 680IDD2P1=0.000000 681IDD2P12=0.000000 682IDD3N=0.057000 683IDD3N2=0.000000 684IDD3P0=0.000000 685IDD3P02=0.000000 686IDD3P1=0.000000 687IDD3P12=0.000000 688IDD4R=0.187000 689IDD4R2=0.000000 690IDD4W=0.165000 691IDD4W2=0.000000 692IDD5=0.220000 693IDD52=0.000000 694IDD6=0.000000 695IDD62=0.000000 696VDD=1.500000 697VDD2=0.000000 698activation_limit=4 699addr_mapping=RoRaBaCoCh 700bank_groups_per_rank=0 701banks_per_rank=8 702burst_length=8 703channels=1 704clk_domain=system.clk_domain 705conf_table_reported=true 706device_bus_width=8 707device_rowbuffer_size=1024 708device_size=536870912 709devices_per_rank=8 710dll=true 711eventq_index=0 712in_addr_map=true 713max_accesses_per_row=16 714mem_sched_policy=frfcfs 715min_writes_per_switch=16 716null=false 717page_policy=open_adaptive 718range=0:134217727 719ranks_per_channel=2 720read_buffer_size=32 721static_backend_latency=10000 722static_frontend_latency=10000 723tBURST=5000 724tCCD_L=0 725tCK=1250 726tCL=13750 727tCS=2500 728tRAS=35000 729tRCD=13750 730tREFI=7800000 731tRFC=260000 732tRP=13750 733tRRD=6000 734tRRD_L=0 735tRTP=7500 736tRTW=2500 737tWR=15000 738tWTR=7500 739tXAW=30000 740tXP=0 741tXPDLL=0 742tXS=0 743tXSDLL=0 744write_buffer_size=64 745write_high_thresh_perc=85 746write_low_thresh_perc=50 747port=system.membus.master[0] 748 749[system.voltage_domain] 750type=VoltageDomain 751eventq_index=0 752voltage=1.000000 753 754