config.ini revision 11066:969113566d50
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56UnifiedTLB=true 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=0 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=TournamentBP 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152 153[system.cpu.dcache] 154type=Cache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159demand_mshr_reserve=1 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_read_only=false 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=262144 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=20 174write_buffers=8 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=2 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=262144 187 188[system.cpu.dtb] 189type=PowerTLB 190eventq_index=0 191size=64 192 193[system.cpu.fuPool] 194type=FUPool 195children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 196FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 197eventq_index=0 198 199[system.cpu.fuPool.FUList0] 200type=FUDesc 201children=opList 202count=6 203eventq_index=0 204opList=system.cpu.fuPool.FUList0.opList 205 206[system.cpu.fuPool.FUList0.opList] 207type=OpDesc 208eventq_index=0 209opClass=IntAlu 210opLat=1 211pipelined=true 212 213[system.cpu.fuPool.FUList1] 214type=FUDesc 215children=opList0 opList1 216count=2 217eventq_index=0 218opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 219 220[system.cpu.fuPool.FUList1.opList0] 221type=OpDesc 222eventq_index=0 223opClass=IntMult 224opLat=3 225pipelined=true 226 227[system.cpu.fuPool.FUList1.opList1] 228type=OpDesc 229eventq_index=0 230opClass=IntDiv 231opLat=20 232pipelined=false 233 234[system.cpu.fuPool.FUList2] 235type=FUDesc 236children=opList0 opList1 opList2 237count=4 238eventq_index=0 239opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 240 241[system.cpu.fuPool.FUList2.opList0] 242type=OpDesc 243eventq_index=0 244opClass=FloatAdd 245opLat=2 246pipelined=true 247 248[system.cpu.fuPool.FUList2.opList1] 249type=OpDesc 250eventq_index=0 251opClass=FloatCmp 252opLat=2 253pipelined=true 254 255[system.cpu.fuPool.FUList2.opList2] 256type=OpDesc 257eventq_index=0 258opClass=FloatCvt 259opLat=2 260pipelined=true 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266eventq_index=0 267opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 268 269[system.cpu.fuPool.FUList3.opList0] 270type=OpDesc 271eventq_index=0 272opClass=FloatMult 273opLat=4 274pipelined=true 275 276[system.cpu.fuPool.FUList3.opList1] 277type=OpDesc 278eventq_index=0 279opClass=FloatDiv 280opLat=12 281pipelined=false 282 283[system.cpu.fuPool.FUList3.opList2] 284type=OpDesc 285eventq_index=0 286opClass=FloatSqrt 287opLat=24 288pipelined=false 289 290[system.cpu.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294eventq_index=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299eventq_index=0 300opClass=MemRead 301opLat=1 302pipelined=true 303 304[system.cpu.fuPool.FUList5] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 307count=4 308eventq_index=0 309opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 310 311[system.cpu.fuPool.FUList5.opList00] 312type=OpDesc 313eventq_index=0 314opClass=SimdAdd 315opLat=1 316pipelined=true 317 318[system.cpu.fuPool.FUList5.opList01] 319type=OpDesc 320eventq_index=0 321opClass=SimdAddAcc 322opLat=1 323pipelined=true 324 325[system.cpu.fuPool.FUList5.opList02] 326type=OpDesc 327eventq_index=0 328opClass=SimdAlu 329opLat=1 330pipelined=true 331 332[system.cpu.fuPool.FUList5.opList03] 333type=OpDesc 334eventq_index=0 335opClass=SimdCmp 336opLat=1 337pipelined=true 338 339[system.cpu.fuPool.FUList5.opList04] 340type=OpDesc 341eventq_index=0 342opClass=SimdCvt 343opLat=1 344pipelined=true 345 346[system.cpu.fuPool.FUList5.opList05] 347type=OpDesc 348eventq_index=0 349opClass=SimdMisc 350opLat=1 351pipelined=true 352 353[system.cpu.fuPool.FUList5.opList06] 354type=OpDesc 355eventq_index=0 356opClass=SimdMult 357opLat=1 358pipelined=true 359 360[system.cpu.fuPool.FUList5.opList07] 361type=OpDesc 362eventq_index=0 363opClass=SimdMultAcc 364opLat=1 365pipelined=true 366 367[system.cpu.fuPool.FUList5.opList08] 368type=OpDesc 369eventq_index=0 370opClass=SimdShift 371opLat=1 372pipelined=true 373 374[system.cpu.fuPool.FUList5.opList09] 375type=OpDesc 376eventq_index=0 377opClass=SimdShiftAcc 378opLat=1 379pipelined=true 380 381[system.cpu.fuPool.FUList5.opList10] 382type=OpDesc 383eventq_index=0 384opClass=SimdSqrt 385opLat=1 386pipelined=true 387 388[system.cpu.fuPool.FUList5.opList11] 389type=OpDesc 390eventq_index=0 391opClass=SimdFloatAdd 392opLat=1 393pipelined=true 394 395[system.cpu.fuPool.FUList5.opList12] 396type=OpDesc 397eventq_index=0 398opClass=SimdFloatAlu 399opLat=1 400pipelined=true 401 402[system.cpu.fuPool.FUList5.opList13] 403type=OpDesc 404eventq_index=0 405opClass=SimdFloatCmp 406opLat=1 407pipelined=true 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411eventq_index=0 412opClass=SimdFloatCvt 413opLat=1 414pipelined=true 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418eventq_index=0 419opClass=SimdFloatDiv 420opLat=1 421pipelined=true 422 423[system.cpu.fuPool.FUList5.opList16] 424type=OpDesc 425eventq_index=0 426opClass=SimdFloatMisc 427opLat=1 428pipelined=true 429 430[system.cpu.fuPool.FUList5.opList17] 431type=OpDesc 432eventq_index=0 433opClass=SimdFloatMult 434opLat=1 435pipelined=true 436 437[system.cpu.fuPool.FUList5.opList18] 438type=OpDesc 439eventq_index=0 440opClass=SimdFloatMultAcc 441opLat=1 442pipelined=true 443 444[system.cpu.fuPool.FUList5.opList19] 445type=OpDesc 446eventq_index=0 447opClass=SimdFloatSqrt 448opLat=1 449pipelined=true 450 451[system.cpu.fuPool.FUList6] 452type=FUDesc 453children=opList 454count=0 455eventq_index=0 456opList=system.cpu.fuPool.FUList6.opList 457 458[system.cpu.fuPool.FUList6.opList] 459type=OpDesc 460eventq_index=0 461opClass=MemWrite 462opLat=1 463pipelined=true 464 465[system.cpu.fuPool.FUList7] 466type=FUDesc 467children=opList0 opList1 468count=4 469eventq_index=0 470opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 471 472[system.cpu.fuPool.FUList7.opList0] 473type=OpDesc 474eventq_index=0 475opClass=MemRead 476opLat=1 477pipelined=true 478 479[system.cpu.fuPool.FUList7.opList1] 480type=OpDesc 481eventq_index=0 482opClass=MemWrite 483opLat=1 484pipelined=true 485 486[system.cpu.fuPool.FUList8] 487type=FUDesc 488children=opList 489count=1 490eventq_index=0 491opList=system.cpu.fuPool.FUList8.opList 492 493[system.cpu.fuPool.FUList8.opList] 494type=OpDesc 495eventq_index=0 496opClass=IprAccess 497opLat=3 498pipelined=false 499 500[system.cpu.icache] 501type=Cache 502children=tags 503addr_ranges=0:18446744073709551615 504assoc=2 505clk_domain=system.cpu_clk_domain 506demand_mshr_reserve=1 507eventq_index=0 508forward_snoops=true 509hit_latency=2 510is_read_only=true 511max_miss_count=0 512mshrs=4 513prefetch_on_access=false 514prefetcher=Null 515response_latency=2 516sequential_access=false 517size=131072 518system=system 519tags=system.cpu.icache.tags 520tgts_per_mshr=20 521write_buffers=8 522cpu_side=system.cpu.icache_port 523mem_side=system.cpu.toL2Bus.slave[0] 524 525[system.cpu.icache.tags] 526type=LRU 527assoc=2 528block_size=64 529clk_domain=system.cpu_clk_domain 530eventq_index=0 531hit_latency=2 532sequential_access=false 533size=131072 534 535[system.cpu.interrupts] 536type=PowerInterrupts 537eventq_index=0 538 539[system.cpu.isa] 540type=PowerISA 541eventq_index=0 542 543[system.cpu.itb] 544type=PowerTLB 545eventq_index=0 546size=64 547 548[system.cpu.l2cache] 549type=Cache 550children=tags 551addr_ranges=0:18446744073709551615 552assoc=8 553clk_domain=system.cpu_clk_domain 554demand_mshr_reserve=1 555eventq_index=0 556forward_snoops=true 557hit_latency=20 558is_read_only=false 559max_miss_count=0 560mshrs=20 561prefetch_on_access=false 562prefetcher=Null 563response_latency=20 564sequential_access=false 565size=2097152 566system=system 567tags=system.cpu.l2cache.tags 568tgts_per_mshr=12 569write_buffers=8 570cpu_side=system.cpu.toL2Bus.master[0] 571mem_side=system.membus.slave[1] 572 573[system.cpu.l2cache.tags] 574type=LRU 575assoc=8 576block_size=64 577clk_domain=system.cpu_clk_domain 578eventq_index=0 579hit_latency=20 580sequential_access=false 581size=2097152 582 583[system.cpu.toL2Bus] 584type=CoherentXBar 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587forward_latency=0 588frontend_latency=1 589response_latency=1 590snoop_filter=Null 591snoop_response_latency=1 592system=system 593use_default_range=false 594width=32 595master=system.cpu.l2cache.cpu_side 596slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 597 598[system.cpu.tracer] 599type=ExeTracer 600eventq_index=0 601 602[system.cpu.workload] 603type=LiveProcess 604cmd=hello 605cwd= 606drivers= 607egid=100 608env= 609errout=cerr 610euid=100 611eventq_index=0 612executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello 613gid=100 614input=cin 615kvmInSE=false 616max_stack_size=67108864 617output=cout 618pid=100 619ppid=99 620simpoint=0 621system=system 622uid=100 623useArchPT=false 624 625[system.cpu_clk_domain] 626type=SrcClockDomain 627clock=500 628domain_id=-1 629eventq_index=0 630init_perf_level=0 631voltage_domain=system.voltage_domain 632 633[system.dvfs_handler] 634type=DVFSHandler 635domains= 636enable=false 637eventq_index=0 638sys_clk_domain=system.clk_domain 639transition_latency=100000000 640 641[system.membus] 642type=CoherentXBar 643clk_domain=system.clk_domain 644eventq_index=0 645forward_latency=4 646frontend_latency=3 647response_latency=2 648snoop_filter=Null 649snoop_response_latency=4 650system=system 651use_default_range=false 652width=16 653master=system.physmem.port 654slave=system.system_port system.cpu.l2cache.mem_side 655 656[system.physmem] 657type=DRAMCtrl 658IDD0=0.075000 659IDD02=0.000000 660IDD2N=0.050000 661IDD2N2=0.000000 662IDD2P0=0.000000 663IDD2P02=0.000000 664IDD2P1=0.000000 665IDD2P12=0.000000 666IDD3N=0.057000 667IDD3N2=0.000000 668IDD3P0=0.000000 669IDD3P02=0.000000 670IDD3P1=0.000000 671IDD3P12=0.000000 672IDD4R=0.187000 673IDD4R2=0.000000 674IDD4W=0.165000 675IDD4W2=0.000000 676IDD5=0.220000 677IDD52=0.000000 678IDD6=0.000000 679IDD62=0.000000 680VDD=1.500000 681VDD2=0.000000 682activation_limit=4 683addr_mapping=RoRaBaCoCh 684bank_groups_per_rank=0 685banks_per_rank=8 686burst_length=8 687channels=1 688clk_domain=system.clk_domain 689conf_table_reported=true 690device_bus_width=8 691device_rowbuffer_size=1024 692device_size=536870912 693devices_per_rank=8 694dll=true 695eventq_index=0 696in_addr_map=true 697max_accesses_per_row=16 698mem_sched_policy=frfcfs 699min_writes_per_switch=16 700null=false 701page_policy=open_adaptive 702range=0:134217727 703ranks_per_channel=2 704read_buffer_size=32 705static_backend_latency=10000 706static_frontend_latency=10000 707tBURST=5000 708tCCD_L=0 709tCK=1250 710tCL=13750 711tCS=2500 712tRAS=35000 713tRCD=13750 714tREFI=7800000 715tRFC=260000 716tRP=13750 717tRRD=6000 718tRRD_L=0 719tRTP=7500 720tRTW=2500 721tWR=15000 722tWTR=7500 723tXAW=30000 724tXP=0 725tXPDLL=0 726tXS=0 727tXSDLL=0 728write_buffer_size=64 729write_high_thresh_perc=85 730write_low_thresh_perc=50 731port=system.membus.master[0] 732 733[system.voltage_domain] 734type=VoltageDomain 735eventq_index=0 736voltage=1.000000 737 738