config.ini revision 10798
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56UnifiedTLB=true 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=0 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=TournamentBP 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159demand_mshr_reserve=1 160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=262144 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=20 174two_queue=false 175write_buffers=8 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=262144 188 189[system.cpu.dtb] 190type=PowerTLB 191eventq_index=0 192size=64 193 194[system.cpu.fuPool] 195type=FUPool 196children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 197FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 198eventq_index=0 199 200[system.cpu.fuPool.FUList0] 201type=FUDesc 202children=opList 203count=6 204eventq_index=0 205opList=system.cpu.fuPool.FUList0.opList 206 207[system.cpu.fuPool.FUList0.opList] 208type=OpDesc 209eventq_index=0 210issueLat=1 211opClass=IntAlu 212opLat=1 213 214[system.cpu.fuPool.FUList1] 215type=FUDesc 216children=opList0 opList1 217count=2 218eventq_index=0 219opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 220 221[system.cpu.fuPool.FUList1.opList0] 222type=OpDesc 223eventq_index=0 224issueLat=1 225opClass=IntMult 226opLat=3 227 228[system.cpu.fuPool.FUList1.opList1] 229type=OpDesc 230eventq_index=0 231issueLat=19 232opClass=IntDiv 233opLat=20 234 235[system.cpu.fuPool.FUList2] 236type=FUDesc 237children=opList0 opList1 opList2 238count=4 239eventq_index=0 240opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 241 242[system.cpu.fuPool.FUList2.opList0] 243type=OpDesc 244eventq_index=0 245issueLat=1 246opClass=FloatAdd 247opLat=2 248 249[system.cpu.fuPool.FUList2.opList1] 250type=OpDesc 251eventq_index=0 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList2] 257type=OpDesc 258eventq_index=0 259issueLat=1 260opClass=FloatCvt 261opLat=2 262 263[system.cpu.fuPool.FUList3] 264type=FUDesc 265children=opList0 opList1 opList2 266count=2 267eventq_index=0 268opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 269 270[system.cpu.fuPool.FUList3.opList0] 271type=OpDesc 272eventq_index=0 273issueLat=1 274opClass=FloatMult 275opLat=4 276 277[system.cpu.fuPool.FUList3.opList1] 278type=OpDesc 279eventq_index=0 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu.fuPool.FUList3.opList2] 285type=OpDesc 286eventq_index=0 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295eventq_index=0 296opList=system.cpu.fuPool.FUList4.opList 297 298[system.cpu.fuPool.FUList4.opList] 299type=OpDesc 300eventq_index=0 301issueLat=1 302opClass=MemRead 303opLat=1 304 305[system.cpu.fuPool.FUList5] 306type=FUDesc 307children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 308count=4 309eventq_index=0 310opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 311 312[system.cpu.fuPool.FUList5.opList00] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=SimdAdd 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList01] 320type=OpDesc 321eventq_index=0 322issueLat=1 323opClass=SimdAddAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList02] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdAlu 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList03] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdCmp 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList04] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdCvt 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList05] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdMisc 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList06] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdMult 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList07] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdMultAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList08] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdShift 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList09] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdShiftAcc 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList10] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdSqrt 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList11] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdFloatAdd 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList12] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList13] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList14] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatCvt 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList15] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatDiv 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList16] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatMisc 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList17] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatMult 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList18] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatMultAcc 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList19] 446type=OpDesc 447eventq_index=0 448issueLat=1 449opClass=SimdFloatSqrt 450opLat=1 451 452[system.cpu.fuPool.FUList6] 453type=FUDesc 454children=opList 455count=0 456eventq_index=0 457opList=system.cpu.fuPool.FUList6.opList 458 459[system.cpu.fuPool.FUList6.opList] 460type=OpDesc 461eventq_index=0 462issueLat=1 463opClass=MemWrite 464opLat=1 465 466[system.cpu.fuPool.FUList7] 467type=FUDesc 468children=opList0 opList1 469count=4 470eventq_index=0 471opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 472 473[system.cpu.fuPool.FUList7.opList0] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemRead 478opLat=1 479 480[system.cpu.fuPool.FUList7.opList1] 481type=OpDesc 482eventq_index=0 483issueLat=1 484opClass=MemWrite 485opLat=1 486 487[system.cpu.fuPool.FUList8] 488type=FUDesc 489children=opList 490count=1 491eventq_index=0 492opList=system.cpu.fuPool.FUList8.opList 493 494[system.cpu.fuPool.FUList8.opList] 495type=OpDesc 496eventq_index=0 497issueLat=3 498opClass=IprAccess 499opLat=3 500 501[system.cpu.icache] 502type=BaseCache 503children=tags 504addr_ranges=0:18446744073709551615 505assoc=2 506clk_domain=system.cpu_clk_domain 507demand_mshr_reserve=1 508eventq_index=0 509forward_snoops=true 510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null 516response_latency=2 517sequential_access=false 518size=131072 519system=system 520tags=system.cpu.icache.tags 521tgts_per_mshr=20 522two_queue=false 523write_buffers=8 524cpu_side=system.cpu.icache_port 525mem_side=system.cpu.toL2Bus.slave[0] 526 527[system.cpu.icache.tags] 528type=LRU 529assoc=2 530block_size=64 531clk_domain=system.cpu_clk_domain 532eventq_index=0 533hit_latency=2 534sequential_access=false 535size=131072 536 537[system.cpu.interrupts] 538type=PowerInterrupts 539eventq_index=0 540 541[system.cpu.isa] 542type=PowerISA 543eventq_index=0 544 545[system.cpu.itb] 546type=PowerTLB 547eventq_index=0 548size=64 549 550[system.cpu.l2cache] 551type=BaseCache 552children=tags 553addr_ranges=0:18446744073709551615 554assoc=8 555clk_domain=system.cpu_clk_domain 556demand_mshr_reserve=1 557eventq_index=0 558forward_snoops=true 559hit_latency=20 560is_top_level=false 561max_miss_count=0 562mshrs=20 563prefetch_on_access=false 564prefetcher=Null 565response_latency=20 566sequential_access=false 567size=2097152 568system=system 569tags=system.cpu.l2cache.tags 570tgts_per_mshr=12 571two_queue=false 572write_buffers=8 573cpu_side=system.cpu.toL2Bus.master[0] 574mem_side=system.membus.slave[1] 575 576[system.cpu.l2cache.tags] 577type=LRU 578assoc=8 579block_size=64 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582hit_latency=20 583sequential_access=false 584size=2097152 585 586[system.cpu.toL2Bus] 587type=CoherentXBar 588clk_domain=system.cpu_clk_domain 589eventq_index=0 590forward_latency=0 591frontend_latency=1 592response_latency=1 593snoop_filter=Null 594snoop_response_latency=1 595system=system 596use_default_range=false 597width=32 598master=system.cpu.l2cache.cpu_side 599slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 600 601[system.cpu.tracer] 602type=ExeTracer 603eventq_index=0 604 605[system.cpu.workload] 606type=LiveProcess 607cmd=hello 608cwd= 609drivers= 610egid=100 611env= 612errout=cerr 613euid=100 614eventq_index=0 615executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello 616gid=100 617input=cin 618kvmInSE=false 619max_stack_size=67108864 620output=cout 621pid=100 622ppid=99 623simpoint=0 624system=system 625uid=100 626useArchPT=false 627 628[system.cpu_clk_domain] 629type=SrcClockDomain 630clock=500 631domain_id=-1 632eventq_index=0 633init_perf_level=0 634voltage_domain=system.voltage_domain 635 636[system.dvfs_handler] 637type=DVFSHandler 638domains= 639enable=false 640eventq_index=0 641sys_clk_domain=system.clk_domain 642transition_latency=100000000 643 644[system.membus] 645type=CoherentXBar 646clk_domain=system.clk_domain 647eventq_index=0 648forward_latency=4 649frontend_latency=3 650response_latency=2 651snoop_filter=Null 652snoop_response_latency=4 653system=system 654use_default_range=false 655width=16 656master=system.physmem.port 657slave=system.system_port system.cpu.l2cache.mem_side 658 659[system.physmem] 660type=DRAMCtrl 661IDD0=0.075000 662IDD02=0.000000 663IDD2N=0.050000 664IDD2N2=0.000000 665IDD2P0=0.000000 666IDD2P02=0.000000 667IDD2P1=0.000000 668IDD2P12=0.000000 669IDD3N=0.057000 670IDD3N2=0.000000 671IDD3P0=0.000000 672IDD3P02=0.000000 673IDD3P1=0.000000 674IDD3P12=0.000000 675IDD4R=0.187000 676IDD4R2=0.000000 677IDD4W=0.165000 678IDD4W2=0.000000 679IDD5=0.220000 680IDD52=0.000000 681IDD6=0.000000 682IDD62=0.000000 683VDD=1.500000 684VDD2=0.000000 685activation_limit=4 686addr_mapping=RoRaBaCoCh 687bank_groups_per_rank=0 688banks_per_rank=8 689burst_length=8 690channels=1 691clk_domain=system.clk_domain 692conf_table_reported=true 693device_bus_width=8 694device_rowbuffer_size=1024 695device_size=536870912 696devices_per_rank=8 697dll=true 698eventq_index=0 699in_addr_map=true 700max_accesses_per_row=16 701mem_sched_policy=frfcfs 702min_writes_per_switch=16 703null=false 704page_policy=open_adaptive 705range=0:134217727 706ranks_per_channel=2 707read_buffer_size=32 708static_backend_latency=10000 709static_frontend_latency=10000 710tBURST=5000 711tCCD_L=0 712tCK=1250 713tCL=13750 714tCS=2500 715tRAS=35000 716tRCD=13750 717tREFI=7800000 718tRFC=260000 719tRP=13750 720tRRD=6000 721tRRD_L=0 722tRTP=7500 723tRTW=2500 724tWR=15000 725tWTR=7500 726tXAW=30000 727tXP=0 728tXPDLL=0 729tXS=0 730tXSDLL=0 731write_buffer_size=64 732write_high_thresh_perc=85 733write_low_thresh_perc=50 734port=system.membus.master[0] 735 736[system.voltage_domain] 737type=VoltageDomain 738eventq_index=0 739voltage=1.000000 740 741