config.ini revision 10315:9e02c14446bb
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55UnifiedTLB=true 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91issueToExecuteDelay=1 92issueWidth=8 93itb=system.cpu.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98needsTSO=false 99numIQEntries=64 100numPhysCCRegs=0 101numPhysFloatRegs=256 102numPhysIntRegs=256 103numROBEntries=192 104numRobs=1 105numThreads=1 106profile=0 107progress_interval=0 108renameToDecodeDelay=1 109renameToFetchDelay=1 110renameToIEWDelay=2 111renameToROBDelay=1 112renameWidth=8 113simpoint_start_insts= 114smtCommitPolicy=RoundRobin 115smtFetchPolicy=SingleThread 116smtIQPolicy=Partitioned 117smtIQThreshold=100 118smtLSQPolicy=Partitioned 119smtLSQThreshold=100 120smtNumFetchingThreads=1 121smtROBPolicy=Partitioned 122smtROBThreshold=100 123socket_id=0 124squashWidth=8 125store_set_clear_period=250000 126switched_out=false 127system=system 128tracer=system.cpu.tracer 129trapLatency=13 130wbDepth=1 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain 159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=262144 170system=system 171tags=system.cpu.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=2 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=262144 187 188[system.cpu.dtb] 189type=PowerTLB 190eventq_index=0 191size=64 192 193[system.cpu.fuPool] 194type=FUPool 195children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 196FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 197eventq_index=0 198 199[system.cpu.fuPool.FUList0] 200type=FUDesc 201children=opList 202count=6 203eventq_index=0 204opList=system.cpu.fuPool.FUList0.opList 205 206[system.cpu.fuPool.FUList0.opList] 207type=OpDesc 208eventq_index=0 209issueLat=1 210opClass=IntAlu 211opLat=1 212 213[system.cpu.fuPool.FUList1] 214type=FUDesc 215children=opList0 opList1 216count=2 217eventq_index=0 218opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 219 220[system.cpu.fuPool.FUList1.opList0] 221type=OpDesc 222eventq_index=0 223issueLat=1 224opClass=IntMult 225opLat=3 226 227[system.cpu.fuPool.FUList1.opList1] 228type=OpDesc 229eventq_index=0 230issueLat=19 231opClass=IntDiv 232opLat=20 233 234[system.cpu.fuPool.FUList2] 235type=FUDesc 236children=opList0 opList1 opList2 237count=4 238eventq_index=0 239opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 240 241[system.cpu.fuPool.FUList2.opList0] 242type=OpDesc 243eventq_index=0 244issueLat=1 245opClass=FloatAdd 246opLat=2 247 248[system.cpu.fuPool.FUList2.opList1] 249type=OpDesc 250eventq_index=0 251issueLat=1 252opClass=FloatCmp 253opLat=2 254 255[system.cpu.fuPool.FUList2.opList2] 256type=OpDesc 257eventq_index=0 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266eventq_index=0 267opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 268 269[system.cpu.fuPool.FUList3.opList0] 270type=OpDesc 271eventq_index=0 272issueLat=1 273opClass=FloatMult 274opLat=4 275 276[system.cpu.fuPool.FUList3.opList1] 277type=OpDesc 278eventq_index=0 279issueLat=12 280opClass=FloatDiv 281opLat=12 282 283[system.cpu.fuPool.FUList3.opList2] 284type=OpDesc 285eventq_index=0 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294eventq_index=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemRead 302opLat=1 303 304[system.cpu.fuPool.FUList5] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 307count=4 308eventq_index=0 309opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 310 311[system.cpu.fuPool.FUList5.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=1 401 402[system.cpu.fuPool.FUList5.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=1 422 423[system.cpu.fuPool.FUList5.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=1 429 430[system.cpu.fuPool.FUList5.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=1 436 437[system.cpu.fuPool.FUList5.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu.fuPool.FUList5.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=1 450 451[system.cpu.fuPool.FUList6] 452type=FUDesc 453children=opList 454count=0 455eventq_index=0 456opList=system.cpu.fuPool.FUList6.opList 457 458[system.cpu.fuPool.FUList6.opList] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=MemWrite 463opLat=1 464 465[system.cpu.fuPool.FUList7] 466type=FUDesc 467children=opList0 opList1 468count=4 469eventq_index=0 470opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 471 472[system.cpu.fuPool.FUList7.opList0] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=MemRead 477opLat=1 478 479[system.cpu.fuPool.FUList7.opList1] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=MemWrite 484opLat=1 485 486[system.cpu.fuPool.FUList8] 487type=FUDesc 488children=opList 489count=1 490eventq_index=0 491opList=system.cpu.fuPool.FUList8.opList 492 493[system.cpu.fuPool.FUList8.opList] 494type=OpDesc 495eventq_index=0 496issueLat=3 497opClass=IprAccess 498opLat=3 499 500[system.cpu.icache] 501type=BaseCache 502children=tags 503addr_ranges=0:18446744073709551615 504assoc=2 505clk_domain=system.cpu_clk_domain 506eventq_index=0 507forward_snoops=true 508hit_latency=2 509is_top_level=true 510max_miss_count=0 511mshrs=4 512prefetch_on_access=false 513prefetcher=Null 514response_latency=2 515sequential_access=false 516size=131072 517system=system 518tags=system.cpu.icache.tags 519tgts_per_mshr=20 520two_queue=false 521write_buffers=8 522cpu_side=system.cpu.icache_port 523mem_side=system.cpu.toL2Bus.slave[0] 524 525[system.cpu.icache.tags] 526type=LRU 527assoc=2 528block_size=64 529clk_domain=system.cpu_clk_domain 530eventq_index=0 531hit_latency=2 532sequential_access=false 533size=131072 534 535[system.cpu.interrupts] 536type=PowerInterrupts 537eventq_index=0 538 539[system.cpu.isa] 540type=PowerISA 541eventq_index=0 542 543[system.cpu.itb] 544type=PowerTLB 545eventq_index=0 546size=64 547 548[system.cpu.l2cache] 549type=BaseCache 550children=tags 551addr_ranges=0:18446744073709551615 552assoc=8 553clk_domain=system.cpu_clk_domain 554eventq_index=0 555forward_snoops=true 556hit_latency=20 557is_top_level=false 558max_miss_count=0 559mshrs=20 560prefetch_on_access=false 561prefetcher=Null 562response_latency=20 563sequential_access=false 564size=2097152 565system=system 566tags=system.cpu.l2cache.tags 567tgts_per_mshr=12 568two_queue=false 569write_buffers=8 570cpu_side=system.cpu.toL2Bus.master[0] 571mem_side=system.membus.slave[1] 572 573[system.cpu.l2cache.tags] 574type=LRU 575assoc=8 576block_size=64 577clk_domain=system.cpu_clk_domain 578eventq_index=0 579hit_latency=20 580sequential_access=false 581size=2097152 582 583[system.cpu.toL2Bus] 584type=CoherentBus 585clk_domain=system.cpu_clk_domain 586eventq_index=0 587header_cycles=1 588system=system 589use_default_range=false 590width=32 591master=system.cpu.l2cache.cpu_side 592slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 593 594[system.cpu.tracer] 595type=ExeTracer 596eventq_index=0 597 598[system.cpu.workload] 599type=LiveProcess 600cmd=hello 601cwd= 602egid=100 603env= 604errout=cerr 605euid=100 606eventq_index=0 607executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello 608gid=100 609input=cin 610max_stack_size=67108864 611output=cout 612pid=100 613ppid=99 614simpoint=0 615system=system 616uid=100 617 618[system.cpu_clk_domain] 619type=SrcClockDomain 620clock=500 621domain_id=-1 622eventq_index=0 623init_perf_level=0 624voltage_domain=system.voltage_domain 625 626[system.dvfs_handler] 627type=DVFSHandler 628domains= 629enable=false 630eventq_index=0 631sys_clk_domain=system.clk_domain 632transition_latency=100000000 633 634[system.membus] 635type=CoherentBus 636clk_domain=system.clk_domain 637eventq_index=0 638header_cycles=1 639system=system 640use_default_range=false 641width=8 642master=system.physmem.port 643slave=system.system_port system.cpu.l2cache.mem_side 644 645[system.physmem] 646type=DRAMCtrl 647activation_limit=4 648addr_mapping=RoRaBaChCo 649banks_per_rank=8 650burst_length=8 651channels=1 652clk_domain=system.clk_domain 653conf_table_reported=true 654device_bus_width=8 655device_rowbuffer_size=1024 656devices_per_rank=8 657eventq_index=0 658in_addr_map=true 659max_accesses_per_row=16 660mem_sched_policy=frfcfs 661min_writes_per_switch=16 662null=false 663page_policy=open_adaptive 664range=0:134217727 665ranks_per_channel=2 666read_buffer_size=32 667static_backend_latency=10000 668static_frontend_latency=10000 669tBURST=5000 670tCK=1250 671tCL=13750 672tRAS=35000 673tRCD=13750 674tREFI=7800000 675tRFC=260000 676tRP=13750 677tRRD=6000 678tRTP=7500 679tRTW=2500 680tWR=15000 681tWTR=7500 682tXAW=30000 683write_buffer_size=64 684write_high_thresh_perc=85 685write_low_thresh_perc=50 686port=system.membus.master[0] 687 688[system.voltage_domain] 689type=VoltageDomain 690eventq_index=0 691voltage=1.000000 692 693