config.ini revision 10036:80e84beef3bb
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51UnifiedTLB=true 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dtb=system.cpu.dtb 72eventq_index=0 73fetchBufferSize=64 74fetchToDecodeDelay=1 75fetchTrapLatency=1 76fetchWidth=8 77forwardComSize=5 78fuPool=system.cpu.fuPool 79function_trace=false 80function_trace_start=0 81iewToCommitDelay=1 82iewToDecodeDelay=1 83iewToFetchDelay=1 84iewToRenameDelay=1 85interrupts=system.cpu.interrupts 86isa=system.cpu.isa 87issueToExecuteDelay=1 88issueWidth=8 89itb=system.cpu.itb 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysCCRegs=0 97numPhysFloatRegs=256 98numPhysIntRegs=256 99numROBEntries=192 100numRobs=1 101numThreads=1 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109simpoint_start_insts= 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119squashWidth=8 120store_set_clear_period=250000 121switched_out=false 122system=system 123tracer=system.cpu.tracer 124trapLatency=13 125wbDepth=1 126wbWidth=8 127workload=system.cpu.workload 128dcache_port=system.cpu.dcache.cpu_side 129icache_port=system.cpu.icache.cpu_side 130 131[system.cpu.branchPred] 132type=BranchPredictor 133BTBEntries=4096 134BTBTagSize=16 135RASSize=16 136choiceCtrBits=2 137choicePredictorSize=8192 138eventq_index=0 139globalCtrBits=2 140globalPredictorSize=8192 141instShiftAmt=2 142localCtrBits=2 143localHistoryTableSize=2048 144localPredictorSize=2048 145numThreads=1 146predType=tournament 147 148[system.cpu.dcache] 149type=BaseCache 150children=tags 151addr_ranges=0:18446744073709551615 152assoc=2 153clk_domain=system.cpu_clk_domain 154eventq_index=0 155forward_snoops=true 156hit_latency=2 157is_top_level=true 158max_miss_count=0 159mshrs=4 160prefetch_on_access=false 161prefetcher=Null 162response_latency=2 163sequential_access=false 164size=262144 165system=system 166tags=system.cpu.dcache.tags 167tgts_per_mshr=20 168two_queue=false 169write_buffers=8 170cpu_side=system.cpu.dcache_port 171mem_side=system.cpu.toL2Bus.slave[1] 172 173[system.cpu.dcache.tags] 174type=LRU 175assoc=2 176block_size=64 177clk_domain=system.cpu_clk_domain 178eventq_index=0 179hit_latency=2 180sequential_access=false 181size=262144 182 183[system.cpu.dtb] 184type=PowerTLB 185eventq_index=0 186size=64 187 188[system.cpu.fuPool] 189type=FUPool 190children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 191FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 192eventq_index=0 193 194[system.cpu.fuPool.FUList0] 195type=FUDesc 196children=opList 197count=6 198eventq_index=0 199opList=system.cpu.fuPool.FUList0.opList 200 201[system.cpu.fuPool.FUList0.opList] 202type=OpDesc 203eventq_index=0 204issueLat=1 205opClass=IntAlu 206opLat=1 207 208[system.cpu.fuPool.FUList1] 209type=FUDesc 210children=opList0 opList1 211count=2 212eventq_index=0 213opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 214 215[system.cpu.fuPool.FUList1.opList0] 216type=OpDesc 217eventq_index=0 218issueLat=1 219opClass=IntMult 220opLat=3 221 222[system.cpu.fuPool.FUList1.opList1] 223type=OpDesc 224eventq_index=0 225issueLat=19 226opClass=IntDiv 227opLat=20 228 229[system.cpu.fuPool.FUList2] 230type=FUDesc 231children=opList0 opList1 opList2 232count=4 233eventq_index=0 234opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 235 236[system.cpu.fuPool.FUList2.opList0] 237type=OpDesc 238eventq_index=0 239issueLat=1 240opClass=FloatAdd 241opLat=2 242 243[system.cpu.fuPool.FUList2.opList1] 244type=OpDesc 245eventq_index=0 246issueLat=1 247opClass=FloatCmp 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList2] 251type=OpDesc 252eventq_index=0 253issueLat=1 254opClass=FloatCvt 255opLat=2 256 257[system.cpu.fuPool.FUList3] 258type=FUDesc 259children=opList0 opList1 opList2 260count=2 261eventq_index=0 262opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 263 264[system.cpu.fuPool.FUList3.opList0] 265type=OpDesc 266eventq_index=0 267issueLat=1 268opClass=FloatMult 269opLat=4 270 271[system.cpu.fuPool.FUList3.opList1] 272type=OpDesc 273eventq_index=0 274issueLat=12 275opClass=FloatDiv 276opLat=12 277 278[system.cpu.fuPool.FUList3.opList2] 279type=OpDesc 280eventq_index=0 281issueLat=24 282opClass=FloatSqrt 283opLat=24 284 285[system.cpu.fuPool.FUList4] 286type=FUDesc 287children=opList 288count=0 289eventq_index=0 290opList=system.cpu.fuPool.FUList4.opList 291 292[system.cpu.fuPool.FUList4.opList] 293type=OpDesc 294eventq_index=0 295issueLat=1 296opClass=MemRead 297opLat=1 298 299[system.cpu.fuPool.FUList5] 300type=FUDesc 301children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 302count=4 303eventq_index=0 304opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 305 306[system.cpu.fuPool.FUList5.opList00] 307type=OpDesc 308eventq_index=0 309issueLat=1 310opClass=SimdAdd 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList01] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=SimdAddAcc 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList02] 321type=OpDesc 322eventq_index=0 323issueLat=1 324opClass=SimdAlu 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList03] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdCmp 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList04] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdCvt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList05] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdMisc 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList06] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdMult 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList07] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdMultAcc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList08] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdShift 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList09] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdShiftAcc 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList10] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdSqrt 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList11] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdFloatAdd 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList12] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdFloatAlu 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList13] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdFloatCmp 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList14] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatCvt 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList15] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatDiv 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList16] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatMisc 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList17] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatMult 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList18] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatMultAcc 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList19] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 450eventq_index=0 451opList=system.cpu.fuPool.FUList6.opList 452 453[system.cpu.fuPool.FUList6.opList] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=MemWrite 458opLat=1 459 460[system.cpu.fuPool.FUList7] 461type=FUDesc 462children=opList0 opList1 463count=4 464eventq_index=0 465opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 466 467[system.cpu.fuPool.FUList7.opList0] 468type=OpDesc 469eventq_index=0 470issueLat=1 471opClass=MemRead 472opLat=1 473 474[system.cpu.fuPool.FUList7.opList1] 475type=OpDesc 476eventq_index=0 477issueLat=1 478opClass=MemWrite 479opLat=1 480 481[system.cpu.fuPool.FUList8] 482type=FUDesc 483children=opList 484count=1 485eventq_index=0 486opList=system.cpu.fuPool.FUList8.opList 487 488[system.cpu.fuPool.FUList8.opList] 489type=OpDesc 490eventq_index=0 491issueLat=3 492opClass=IprAccess 493opLat=3 494 495[system.cpu.icache] 496type=BaseCache 497children=tags 498addr_ranges=0:18446744073709551615 499assoc=2 500clk_domain=system.cpu_clk_domain 501eventq_index=0 502forward_snoops=true 503hit_latency=2 504is_top_level=true 505max_miss_count=0 506mshrs=4 507prefetch_on_access=false 508prefetcher=Null 509response_latency=2 510sequential_access=false 511size=131072 512system=system 513tags=system.cpu.icache.tags 514tgts_per_mshr=20 515two_queue=false 516write_buffers=8 517cpu_side=system.cpu.icache_port 518mem_side=system.cpu.toL2Bus.slave[0] 519 520[system.cpu.icache.tags] 521type=LRU 522assoc=2 523block_size=64 524clk_domain=system.cpu_clk_domain 525eventq_index=0 526hit_latency=2 527sequential_access=false 528size=131072 529 530[system.cpu.interrupts] 531type=PowerInterrupts 532eventq_index=0 533 534[system.cpu.isa] 535type=PowerISA 536eventq_index=0 537 538[system.cpu.itb] 539type=PowerTLB 540eventq_index=0 541size=64 542 543[system.cpu.l2cache] 544type=BaseCache 545children=tags 546addr_ranges=0:18446744073709551615 547assoc=8 548clk_domain=system.cpu_clk_domain 549eventq_index=0 550forward_snoops=true 551hit_latency=20 552is_top_level=false 553max_miss_count=0 554mshrs=20 555prefetch_on_access=false 556prefetcher=Null 557response_latency=20 558sequential_access=false 559size=2097152 560system=system 561tags=system.cpu.l2cache.tags 562tgts_per_mshr=12 563two_queue=false 564write_buffers=8 565cpu_side=system.cpu.toL2Bus.master[0] 566mem_side=system.membus.slave[1] 567 568[system.cpu.l2cache.tags] 569type=LRU 570assoc=8 571block_size=64 572clk_domain=system.cpu_clk_domain 573eventq_index=0 574hit_latency=20 575sequential_access=false 576size=2097152 577 578[system.cpu.toL2Bus] 579type=CoherentBus 580clk_domain=system.cpu_clk_domain 581eventq_index=0 582header_cycles=1 583system=system 584use_default_range=false 585width=32 586master=system.cpu.l2cache.cpu_side 587slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 588 589[system.cpu.tracer] 590type=ExeTracer 591eventq_index=0 592 593[system.cpu.workload] 594type=LiveProcess 595cmd=hello 596cwd= 597egid=100 598env= 599errout=cerr 600euid=100 601eventq_index=0 602executable=/dist/test-progs/hello/bin/power/linux/hello 603gid=100 604input=cin 605max_stack_size=67108864 606output=cout 607pid=100 608ppid=99 609simpoint=0 610system=system 611uid=100 612 613[system.cpu_clk_domain] 614type=SrcClockDomain 615clock=500 616eventq_index=0 617voltage_domain=system.voltage_domain 618 619[system.membus] 620type=CoherentBus 621clk_domain=system.clk_domain 622eventq_index=0 623header_cycles=1 624system=system 625use_default_range=false 626width=8 627master=system.physmem.port 628slave=system.system_port system.cpu.l2cache.mem_side 629 630[system.physmem] 631type=SimpleDRAM 632activation_limit=4 633addr_mapping=RaBaChCo 634banks_per_rank=8 635burst_length=8 636channels=1 637clk_domain=system.clk_domain 638conf_table_reported=true 639device_bus_width=8 640device_rowbuffer_size=1024 641devices_per_rank=8 642eventq_index=0 643in_addr_map=true 644mem_sched_policy=frfcfs 645null=false 646page_policy=open 647range=0:134217727 648ranks_per_channel=2 649read_buffer_size=32 650static_backend_latency=10000 651static_frontend_latency=10000 652tBURST=5000 653tCL=13750 654tRAS=35000 655tRCD=13750 656tREFI=7800000 657tRFC=300000 658tRP=13750 659tRRD=6250 660tWTR=7500 661tXAW=40000 662write_buffer_size=32 663write_high_thresh_perc=70 664write_low_thresh_perc=0 665port=system.membus.master[0] 666 667[system.voltage_domain] 668type=VoltageDomain 669eventq_index=0 670voltage=1.000000 671 672