stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 31633000 # Number of ticks simulated 5final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 482351 # Simulator instruction rate (inst/s) 8host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2613274672 # Simulator tick rate (ticks/s) 10host_mem_usage 225064 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5814 # Number of instructions simulated 13sim_ops 5814 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28096 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 439 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 888186388 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 388 # Transaction distribution 32system.membus.trans_dist::ReadResp 388 # Transaction distribution 33system.membus.trans_dist::ReadExReq 51 # Transaction distribution 34system.membus.trans_dist::ReadExResp 51 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 28096 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 43system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 12.5 # Layer utilization (%) 45system.cpu.dtb.read_hits 0 # DTB read hits 46system.cpu.dtb.read_misses 0 # DTB read misses 47system.cpu.dtb.read_accesses 0 # DTB read accesses 48system.cpu.dtb.write_hits 0 # DTB write hits 49system.cpu.dtb.write_misses 0 # DTB write misses 50system.cpu.dtb.write_accesses 0 # DTB write accesses 51system.cpu.dtb.hits 0 # DTB hits 52system.cpu.dtb.misses 0 # DTB misses 53system.cpu.dtb.accesses 0 # DTB accesses 54system.cpu.itb.read_hits 0 # DTB read hits 55system.cpu.itb.read_misses 0 # DTB read misses 56system.cpu.itb.read_accesses 0 # DTB read accesses 57system.cpu.itb.write_hits 0 # DTB write hits 58system.cpu.itb.write_misses 0 # DTB write misses 59system.cpu.itb.write_accesses 0 # DTB write accesses 60system.cpu.itb.hits 0 # DTB hits 61system.cpu.itb.misses 0 # DTB misses 62system.cpu.itb.accesses 0 # DTB accesses 63system.cpu.workload.num_syscalls 8 # Number of system calls 64system.cpu.numCycles 63266 # number of cpu cycles simulated 65system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu.committedInsts 5814 # Number of instructions committed 68system.cpu.committedOps 5814 # Number of ops (including micro ops) committed 69system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses 70system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 71system.cpu.num_func_calls 194 # number of times a function call or return occured 72system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls 73system.cpu.num_int_insts 5113 # number of integer instructions 74system.cpu.num_fp_insts 2 # number of float instructions 75system.cpu.num_int_register_reads 7284 # number of times the integer registers were read 76system.cpu.num_int_register_writes 3397 # number of times the integer registers were written 77system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 78system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 79system.cpu.num_mem_refs 2089 # number of memory refs 80system.cpu.num_load_insts 1163 # Number of load instructions 81system.cpu.num_store_insts 926 # Number of store instructions 82system.cpu.num_idle_cycles 0 # Number of idle cycles 83system.cpu.num_busy_cycles 63266 # Number of busy cycles 84system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 85system.cpu.idle_fraction 0 # Percentage of idle cycles 86system.cpu.icache.tags.replacements 13 # number of replacements 87system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use 88system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. 89system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. 90system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. 91system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 92system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor 93system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy 94system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy 95system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits 96system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits 97system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits 98system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits 99system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits 100system.cpu.icache.overall_hits::total 5513 # number of overall hits 101system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 102system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 103system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 104system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 105system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 106system.cpu.icache.overall_misses::total 303 # number of overall misses 107system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles 108system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles 109system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles 110system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles 111system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles 112system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles 113system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) 114system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) 115system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses 116system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses 117system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses 118system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses 119system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses 120system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses 121system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses 122system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses 123system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses 124system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses 125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency 126system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency 127system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 128system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency 129system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency 130system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency 131system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 132system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 133system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 134system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 135system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 136system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 137system.cpu.icache.fast_writes 0 # number of fast writes performed 138system.cpu.icache.cache_copies 0 # number of cache copies performed 139system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 140system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 141system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 142system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 143system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 144system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 145system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 146system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 147system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 148system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 149system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 150system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 151system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses 152system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses 153system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses 154system.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses 155system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses 156system.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses 157system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 158system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 159system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 160system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 161system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 162system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 163system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 164system.cpu.l2cache.tags.replacements 0 # number of replacements 165system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use 166system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 167system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks. 168system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks. 169system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 170system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor 171system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor 172system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy 173system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy 174system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy 175system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 176system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 177system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 178system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 179system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 180system.cpu.l2cache.overall_hits::total 2 # number of overall hits 181system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 182system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 183system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 184system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 185system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 186system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 187system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 188system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 189system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 190system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 191system.cpu.l2cache.overall_misses::total 439 # number of overall misses 192system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 193system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 194system.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 195system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 196system.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 197system.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 198system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 199system.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 200system.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 201system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 202system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 203system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 204system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 205system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 206system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 207system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 208system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 209system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 210system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 211system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 212system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 213system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 214system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 215system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 216system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses 217system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 218system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 219system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 220system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 221system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses 222system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 223system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 224system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses 225system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 226system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 227system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 228system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 229system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 230system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 231system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 232system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 233system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 234system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 235system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 236system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 237system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 238system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 239system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 240system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 241system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 242system.cpu.l2cache.fast_writes 0 # number of fast writes performed 243system.cpu.l2cache.cache_copies 0 # number of cache copies performed 244system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 245system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 246system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 247system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 248system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 249system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 250system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 251system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 252system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 253system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 254system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 255system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 256system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 257system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 258system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 259system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 260system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 261system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 262system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 263system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 264system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 265system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 266system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 267system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 268system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses 269system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 270system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 271system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 272system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 273system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses 274system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 275system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 276system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses 277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 278system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 279system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 280system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 281system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 282system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 283system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 284system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 285system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 286system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 287system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 288system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 289system.cpu.dcache.tags.replacements 0 # number of replacements 290system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use 291system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. 292system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. 293system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. 294system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 295system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor 296system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy 297system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy 298system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits 299system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits 300system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 301system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 302system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits 303system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits 304system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits 305system.cpu.dcache.overall_hits::total 1950 # number of overall hits 306system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 307system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 308system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 309system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 310system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 311system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 312system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 313system.cpu.dcache.overall_misses::total 138 # number of overall misses 314system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 315system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 316system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles 317system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles 318system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles 319system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles 320system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles 321system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles 322system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) 323system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) 324system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 325system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 326system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses 327system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses 328system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses 329system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses 330system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses 331system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses 332system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 333system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses 334system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses 335system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses 336system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses 337system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses 338system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 339system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 340system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 341system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 342system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 343system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 344system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 345system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 346system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 351system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 352system.cpu.dcache.fast_writes 0 # number of fast writes performed 353system.cpu.dcache.cache_copies 0 # number of cache copies performed 354system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 355system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 356system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 357system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 358system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 359system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 360system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 361system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 362system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 363system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 364system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 365system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 366system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 367system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 368system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 369system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 370system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses 371system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses 372system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 373system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 374system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses 375system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses 376system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses 377system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses 378system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 379system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 380system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 381system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 382system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 383system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 384system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 385system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 386system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 387system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) 388system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution 389system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution 390system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 391system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 392system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) 393system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) 394system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) 395system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) 396system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) 397system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) 398system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) 399system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 400system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 401system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 402system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) 403system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 404system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 405system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 406 407---------- End Simulation Statistics ---------- 408