stats.txt revision 9096:8971a998190a
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33413000 # Number of ticks simulated 5final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 168189 # Simulator instruction rate (inst/s) 8host_op_rate 168105 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 963489284 # Simulator tick rate (ticks/s) 10host_mem_usage 219036 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28096 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 439 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses 38system.cpu.dtb.accesses 0 # DTB accesses 39system.cpu.itb.read_hits 0 # DTB read hits 40system.cpu.itb.read_misses 0 # DTB read misses 41system.cpu.itb.read_accesses 0 # DTB read accesses 42system.cpu.itb.write_hits 0 # DTB write hits 43system.cpu.itb.write_misses 0 # DTB write misses 44system.cpu.itb.write_accesses 0 # DTB write accesses 45system.cpu.itb.hits 0 # DTB hits 46system.cpu.itb.misses 0 # DTB misses 47system.cpu.itb.accesses 0 # DTB accesses 48system.cpu.workload.num_syscalls 8 # Number of system calls 49system.cpu.numCycles 66826 # number of cpu cycles simulated 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 5827 # Number of instructions committed 53system.cpu.committedOps 5827 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 56system.cpu.num_func_calls 194 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 58system.cpu.num_int_insts 5126 # number of integer instructions 59system.cpu.num_fp_insts 2 # number of float instructions 60system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 61system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 64system.cpu.num_mem_refs 2090 # number of memory refs 65system.cpu.num_load_insts 1164 # Number of load instructions 66system.cpu.num_store_insts 926 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles 68system.cpu.num_busy_cycles 66826 # Number of busy cycles 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.icache.replacements 13 # number of replacements 72system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use 73system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 74system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 75system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 76system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 77system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor 78system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy 79system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy 80system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits 81system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits 82system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits 83system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits 84system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits 85system.cpu.icache.overall_hits::total 5526 # number of overall hits 86system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 87system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses 88system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses 89system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses 90system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses 91system.cpu.icache.overall_misses::total 303 # number of overall misses 92system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles 93system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles 94system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles 95system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles 96system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles 97system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles 98system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses) 99system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses) 100system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses 101system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses 102system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses 103system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses 104system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses 105system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses 106system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses 107system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses 108system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses 109system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses 110system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 111system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency 112system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 113system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency 114system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 115system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency 116system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 119system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 120system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.cpu.icache.fast_writes 0 # number of fast writes performed 123system.cpu.icache.cache_copies 0 # number of cache copies performed 124system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 125system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 126system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 127system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 128system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 129system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses 130system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles 131system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles 132system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles 133system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles 134system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles 135system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles 136system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses 137system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses 138system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses 139system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses 140system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses 141system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses 142system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 143system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 144system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 145system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 146system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 147system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 148system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 149system.cpu.dcache.replacements 0 # number of replacements 150system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use 151system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 152system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 153system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 154system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 155system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor 156system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy 157system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy 158system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits 159system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits 160system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 161system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 162system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits 163system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits 164system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits 165system.cpu.dcache.overall_hits::total 1951 # number of overall hits 166system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 167system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 168system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses 169system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses 170system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses 171system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses 172system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses 173system.cpu.dcache.overall_misses::total 138 # number of overall misses 174system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles 175system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles 176system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles 177system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles 178system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles 179system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles 180system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles 181system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles 182system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) 183system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) 184system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 185system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 186system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses 187system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses 188system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses 189system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses 190system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses 191system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses 192system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses 193system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses 194system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses 195system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses 196system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses 197system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses 198system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 199system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency 200system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 201system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency 202system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 203system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency 204system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 205system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency 206system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 207system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 209system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 210system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 211system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 212system.cpu.dcache.fast_writes 0 # number of fast writes performed 213system.cpu.dcache.cache_copies 0 # number of cache copies performed 214system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 215system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 216system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 217system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 218system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 219system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses 220system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 221system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses 222system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 223system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 224system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles 225system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles 226system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles 227system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles 228system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles 229system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles 230system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses 231system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses 232system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 233system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 234system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses 235system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses 236system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses 237system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses 238system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 239system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 240system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 241system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 242system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 243system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 245system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 246system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 247system.cpu.l2cache.replacements 0 # number of replacements 248system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use 249system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 250system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 251system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 252system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 253system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor 254system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor 255system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy 256system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy 257system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy 258system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 259system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 260system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 261system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 262system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 263system.cpu.l2cache.overall_hits::total 2 # number of overall hits 264system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 265system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 266system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses 267system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 268system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 269system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses 270system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses 271system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses 272system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses 273system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses 274system.cpu.l2cache.overall_misses::total 439 # number of overall misses 275system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles 276system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 277system.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles 278system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles 279system.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles 280system.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles 281system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles 282system.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles 283system.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles 284system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles 285system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles 286system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) 287system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 288system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) 289system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 290system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 291system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses 292system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses 293system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 294system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses 295system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses 296system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 297system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses 298system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 299system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses 300system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 301system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 302system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses 303system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 304system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses 305system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses 306system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 307system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses 308system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 309system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 310system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 311system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 312system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 313system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 314system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 315system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 316system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 317system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 318system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 319system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 322system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 323system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 325system.cpu.l2cache.fast_writes 0 # number of fast writes performed 326system.cpu.l2cache.cache_copies 0 # number of cache copies performed 327system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 328system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 329system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 330system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 331system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 332system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses 333system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 334system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses 335system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses 336system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses 337system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses 338system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles 339system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 340system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles 341system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles 342system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles 343system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles 344system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles 345system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles 346system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles 347system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles 348system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles 349system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses 350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses 352system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 353system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 354system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses 355system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 356system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses 357system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses 358system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 359system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses 360system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 361system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 362system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 363system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 364system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 365system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 366system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 367system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 368system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 369system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 370system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 371system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 372 373---------- End Simulation Statistics ---------- 374