stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 32088000 # Number of ticks simulated 5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 263412 # Simulator instruction rate (inst/s) 8host_tick_rate 1449372115 # Simulator tick rate (ticks/s) 9host_mem_usage 207940 # Number of bytes of host memory used 10host_seconds 0.02 # Real time elapsed on the host 11sim_insts 5827 # Number of instructions simulated 12system.physmem.bytes_read 28096 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 439 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.read_hits 0 # DTB read hits 22system.cpu.dtb.read_misses 0 # DTB read misses 23system.cpu.dtb.read_accesses 0 # DTB read accesses 24system.cpu.dtb.write_hits 0 # DTB write hits 25system.cpu.dtb.write_misses 0 # DTB write misses 26system.cpu.dtb.write_accesses 0 # DTB write accesses 27system.cpu.dtb.hits 0 # DTB hits 28system.cpu.dtb.misses 0 # DTB misses 29system.cpu.dtb.accesses 0 # DTB accesses 30system.cpu.itb.read_hits 0 # DTB read hits 31system.cpu.itb.read_misses 0 # DTB read misses 32system.cpu.itb.read_accesses 0 # DTB read accesses 33system.cpu.itb.write_hits 0 # DTB write hits 34system.cpu.itb.write_misses 0 # DTB write misses 35system.cpu.itb.write_accesses 0 # DTB write accesses 36system.cpu.itb.hits 0 # DTB hits 37system.cpu.itb.misses 0 # DTB misses 38system.cpu.itb.accesses 0 # DTB accesses 39system.cpu.workload.num_syscalls 8 # Number of system calls 40system.cpu.numCycles 64176 # number of cpu cycles simulated 41system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 42system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43system.cpu.num_insts 5827 # Number of instructions executed 44system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 45system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 46system.cpu.num_func_calls 194 # number of times a function call or return occured 47system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 48system.cpu.num_int_insts 5126 # number of integer instructions 49system.cpu.num_fp_insts 2 # number of float instructions 50system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 51system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 52system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 53system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 54system.cpu.num_mem_refs 2090 # number of memory refs 55system.cpu.num_load_insts 1164 # Number of load instructions 56system.cpu.num_store_insts 926 # Number of store instructions 57system.cpu.num_idle_cycles 0 # Number of idle cycles 58system.cpu.num_busy_cycles 64176 # Number of busy cycles 59system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 60system.cpu.idle_fraction 0 # Percentage of idle cycles 61system.cpu.icache.replacements 13 # number of replacements 62system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use 63system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 64system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 65system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 66system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 67system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context 68system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy 69system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits 70system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits 71system.cpu.icache.overall_hits 5526 # number of overall hits 72system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses 73system.cpu.icache.demand_misses 303 # number of demand (read+write) misses 74system.cpu.icache.overall_misses 303 # number of overall misses 75system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles 76system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles 77system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles 78system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) 79system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses 80system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses 81system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses 82system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses 83system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses 84system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency 85system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency 86system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency 87system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 88system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 90system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 91system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 92system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 93system.cpu.icache.fast_writes 0 # number of fast writes performed 94system.cpu.icache.cache_copies 0 # number of cache copies performed 95system.cpu.icache.writebacks 0 # number of writebacks 96system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 97system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 98system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses 99system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses 100system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses 101system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 102system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles 103system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles 105system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 106system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses 107system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses 108system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses 109system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency 110system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 111system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency 112system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 113system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 114system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 115system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 116system.cpu.dcache.replacements 0 # number of replacements 117system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use 118system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 119system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 120system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 121system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 122system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context 123system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy 124system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits 125system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits 126system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits 127system.cpu.dcache.overall_hits 1951 # number of overall hits 128system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses 129system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses 130system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses 131system.cpu.dcache.overall_misses 138 # number of overall misses 132system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles 133system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles 134system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles 135system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles 136system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) 137system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) 138system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses 139system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses 140system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses 141system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses 142system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses 143system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses 144system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 145system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency 146system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency 147system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency 148system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 149system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 150system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 151system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 152system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 153system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 154system.cpu.dcache.fast_writes 0 # number of fast writes performed 155system.cpu.dcache.cache_copies 0 # number of cache copies performed 156system.cpu.dcache.writebacks 0 # number of writebacks 157system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 158system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 159system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses 160system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses 161system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses 162system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses 163system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 164system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles 165system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles 166system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles 167system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles 168system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 169system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses 170system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses 171system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses 172system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses 173system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 174system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency 175system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 176system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 177system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 178system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 179system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 180system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 181system.cpu.l2cache.replacements 0 # number of replacements 182system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use 183system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 184system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 185system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 186system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 187system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context 188system.cpu.l2cache.occ_percent::0 0.005739 # Average percentage of cache occupancy 189system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits 190system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits 191system.cpu.l2cache.overall_hits 2 # number of overall hits 192system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses 193system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses 194system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses 195system.cpu.l2cache.overall_misses 439 # number of overall misses 196system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles 197system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles 198system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles 199system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles 200system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) 201system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) 202system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses 203system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses 204system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses 205system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 206system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses 207system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses 208system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 209system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency 210system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency 211system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency 212system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 216system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 217system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 218system.cpu.l2cache.fast_writes 0 # number of fast writes performed 219system.cpu.l2cache.cache_copies 0 # number of cache copies performed 220system.cpu.l2cache.writebacks 0 # number of writebacks 221system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 222system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 223system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses 224system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses 225system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses 226system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses 227system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 228system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles 229system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles 230system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles 231system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles 232system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 233system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses 234system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 235system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses 236system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses 237system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 238system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 239system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 240system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 241system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 242system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 243system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 244system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 245 246---------- End Simulation Statistics ---------- 247