stats.txt revision 11268:8b4b55d79ddd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000100 # Number of seconds simulated 4sim_ticks 100307 # Number of ticks simulated 5final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 21348 # Simulator instruction rate (inst/s) 8host_op_rate 21346 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 380685 # Simulator tick rate (ticks/s) 10host_mem_usage 386772 # Number of bytes of host memory used 11host_seconds 0.26 # Real time elapsed on the host 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 937920584 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 937920584 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 935368419 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 935368419 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1873289003 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 1873289003 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1470 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1466 # Number of write requests accepted 32system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 58560 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 35520 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 59456 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 516 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 243 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 113 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 44 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 160 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 9 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 83 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 239 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 97 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 117 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 176 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 11 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 100258 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 915 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 54 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 61 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 62 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 346 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 337.017341 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 221.831279 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 312.425842 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 75 21.68% 21.68% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 111 32.08% 53.76% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 54 15.61% 69.36% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 22 6.36% 75.72% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 14 4.05% 79.77% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 16 4.62% 84.39% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 11 3.18% 87.57% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 8 2.31% 89.88% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 35 10.12% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 346 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 15.982456 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 15.826931 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 2.722205 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes 211system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads 212system.mem_ctrls.wrPerTurnAround::mean 16.298246 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::gmean 16.275827 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::stdev 0.905635 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::16 51 89.47% 89.47% # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::18 2 3.51% 92.98% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads 220system.mem_ctrls.totQLat 12902 # Total ticks spent queuing 221system.mem_ctrls.totMemAccLat 30287 # Total ticks spent from burst creation until serviced by the DRAM 222system.mem_ctrls.totBusLat 4575 # Total ticks spent in databus transfers 223system.mem_ctrls.avgQLat 14.10 # Average queueing delay per DRAM burst 224system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 225system.mem_ctrls.avgMemAccLat 33.10 # Average memory access latency per DRAM burst 226system.mem_ctrls.avgRdBW 583.81 # Average DRAM read bandwidth in MiByte/s 227system.mem_ctrls.avgWrBW 592.74 # Average achieved write bandwidth in MiByte/s 228system.mem_ctrls.avgRdBWSys 937.92 # Average system read bandwidth in MiByte/s 229system.mem_ctrls.avgWrBWSys 935.37 # Average system write bandwidth in MiByte/s 230system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 231system.mem_ctrls.busUtil 9.19 # Data bus utilization in percentage 232system.mem_ctrls.busUtilRead 4.56 # Data bus utilization in percentage for reads 233system.mem_ctrls.busUtilWrite 4.63 # Data bus utilization in percentage for writes 234system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 235system.mem_ctrls.avgWrQLen 25.61 # Average write queue length when enqueuing 236system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads 237system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes 238system.mem_ctrls.readRowHitRate 68.52 # Row buffer hit rate for reads 239system.mem_ctrls.writeRowHitRate 91.05 # Row buffer hit rate for writes 240system.mem_ctrls.avgGap 34.15 # Average gap between requests 241system.mem_ctrls.pageHitRate 80.00 # Row buffer hit rate, read and write combined 242system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ) 243system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ) 244system.mem_ctrls_0.readEnergy 1497600 # Energy for read commands per rank (pJ) 245system.mem_ctrls_0.writeEnergy 1254528 # Energy for write commands per rank (pJ) 246system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 247system.mem_ctrls_0.actBackEnergy 47014056 # Energy for active background per rank (pJ) 248system.mem_ctrls_0.preBackEnergy 14974800 # Energy for precharge background per rank (pJ) 249system.mem_ctrls_0.totalEnergy 71631624 # Total energy per rank (pJ) 250system.mem_ctrls_0.averagePower 764.543654 # Core power per rank (mW) 251system.mem_ctrls_0.memoryStateTime::IDLE 25717 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT 71078 # Time in different power states 255system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.mem_ctrls_1.actEnergy 1950480 # Energy for activate commands per rank (pJ) 257system.mem_ctrls_1.preEnergy 1083600 # Energy for precharge commands per rank (pJ) 258system.mem_ctrls_1.readEnergy 9197760 # Energy for read commands per rank (pJ) 259system.mem_ctrls_1.writeEnergy 7713792 # Energy for write commands per rank (pJ) 260system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 261system.mem_ctrls_1.actBackEnergy 63796680 # Energy for active background per rank (pJ) 262system.mem_ctrls_1.preBackEnergy 253200 # Energy for precharge background per rank (pJ) 263system.mem_ctrls_1.totalEnergy 90098232 # Total energy per rank (pJ) 264system.mem_ctrls_1.averagePower 961.642744 # Core power per rank (mW) 265system.mem_ctrls_1.memoryStateTime::IDLE 100 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT 90486 # Time in different power states 269system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 270system.cpu.clk_domain.clock 1 # Clock period in ticks 271system.cpu.dtb.read_hits 0 # DTB read hits 272system.cpu.dtb.read_misses 0 # DTB read misses 273system.cpu.dtb.read_accesses 0 # DTB read accesses 274system.cpu.dtb.write_hits 0 # DTB write hits 275system.cpu.dtb.write_misses 0 # DTB write misses 276system.cpu.dtb.write_accesses 0 # DTB write accesses 277system.cpu.dtb.hits 0 # DTB hits 278system.cpu.dtb.misses 0 # DTB misses 279system.cpu.dtb.accesses 0 # DTB accesses 280system.cpu.itb.read_hits 0 # DTB read hits 281system.cpu.itb.read_misses 0 # DTB read misses 282system.cpu.itb.read_accesses 0 # DTB read accesses 283system.cpu.itb.write_hits 0 # DTB write hits 284system.cpu.itb.write_misses 0 # DTB write misses 285system.cpu.itb.write_accesses 0 # DTB write accesses 286system.cpu.itb.hits 0 # DTB hits 287system.cpu.itb.misses 0 # DTB misses 288system.cpu.itb.accesses 0 # DTB accesses 289system.cpu.workload.num_syscalls 7 # Number of system calls 290system.cpu.numCycles 100307 # number of cpu cycles simulated 291system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 292system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 293system.cpu.committedInsts 5624 # Number of instructions committed 294system.cpu.committedOps 5624 # Number of ops (including micro ops) committed 295system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses 296system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 297system.cpu.num_func_calls 190 # number of times a function call or return occured 298system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls 299system.cpu.num_int_insts 4944 # number of integer instructions 300system.cpu.num_fp_insts 2 # number of float instructions 301system.cpu.num_int_register_reads 7054 # number of times the integer registers were read 302system.cpu.num_int_register_writes 3281 # number of times the integer registers were written 303system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 304system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 305system.cpu.num_mem_refs 2034 # number of memory refs 306system.cpu.num_load_insts 1132 # Number of load instructions 307system.cpu.num_store_insts 902 # Number of store instructions 308system.cpu.num_idle_cycles 0 # Number of idle cycles 309system.cpu.num_busy_cycles 100307 # Number of busy cycles 310system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 311system.cpu.idle_fraction 0 # Percentage of idle cycles 312system.cpu.Branches 883 # Number of branches fetched 313system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction 314system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction 315system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction 316system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction 317system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction 318system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction 319system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction 320system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction 321system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction 322system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction 323system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction 324system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction 325system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction 326system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction 327system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction 328system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction 329system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction 330system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction 331system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction 332system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction 333system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction 334system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction 335system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction 336system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction 337system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction 338system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction 339system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction 340system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction 341system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction 342system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction 343system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction 344system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction 345system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 346system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 347system.cpu.op_class::total 5625 # Class of executed instruction 348system.ruby.clk_domain.clock 1 # Clock period in ticks 349system.ruby.delayHist::bucket_size 1 # delay histogram for all message 350system.ruby.delayHist::max_bucket 9 # delay histogram for all message 351system.ruby.delayHist::samples 2936 # delay histogram for all message 352system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 353system.ruby.delayHist::total 2936 # delay histogram for all message 354system.ruby.outstanding_req_hist::bucket_size 1 355system.ruby.outstanding_req_hist::max_bucket 9 356system.ruby.outstanding_req_hist::samples 7659 357system.ruby.outstanding_req_hist::mean 1 358system.ruby.outstanding_req_hist::gmean 1 359system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 360system.ruby.outstanding_req_hist::total 7659 361system.ruby.latency_hist::bucket_size 64 362system.ruby.latency_hist::max_bucket 639 363system.ruby.latency_hist::samples 7658 364system.ruby.latency_hist::mean 12.098329 365system.ruby.latency_hist::gmean 2.138684 366system.ruby.latency_hist::stdev 27.490264 367system.ruby.latency_hist | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 368system.ruby.latency_hist::total 7658 369system.ruby.hit_latency_hist::bucket_size 1 370system.ruby.hit_latency_hist::max_bucket 9 371system.ruby.hit_latency_hist::samples 6188 372system.ruby.hit_latency_hist::mean 1 373system.ruby.hit_latency_hist::gmean 1 374system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 375system.ruby.hit_latency_hist::total 6188 376system.ruby.miss_latency_hist::bucket_size 64 377system.ruby.miss_latency_hist::max_bucket 639 378system.ruby.miss_latency_hist::samples 1470 379system.ruby.miss_latency_hist::mean 58.817007 380system.ruby.miss_latency_hist::gmean 52.469450 381system.ruby.miss_latency_hist::stdev 35.158300 382system.ruby.miss_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 383system.ruby.miss_latency_hist::total 1470 384system.ruby.Directory.incomplete_times 1469 385system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits 386system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses 387system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses 388system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 389system.ruby.network.routers0.percent_links_utilized 7.317535 390system.ruby.network.routers0.msg_count.Control::2 1470 391system.ruby.network.routers0.msg_count.Data::2 1466 392system.ruby.network.routers0.msg_count.Response_Data::4 1470 393system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 394system.ruby.network.routers0.msg_bytes.Control::2 11760 395system.ruby.network.routers0.msg_bytes.Data::2 105552 396system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 397system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 398system.ruby.network.routers1.percent_links_utilized 7.317535 399system.ruby.network.routers1.msg_count.Control::2 1470 400system.ruby.network.routers1.msg_count.Data::2 1466 401system.ruby.network.routers1.msg_count.Response_Data::4 1470 402system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 403system.ruby.network.routers1.msg_bytes.Control::2 11760 404system.ruby.network.routers1.msg_bytes.Data::2 105552 405system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 406system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 407system.ruby.network.routers2.percent_links_utilized 7.317535 408system.ruby.network.routers2.msg_count.Control::2 1470 409system.ruby.network.routers2.msg_count.Data::2 1466 410system.ruby.network.routers2.msg_count.Response_Data::4 1470 411system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 412system.ruby.network.routers2.msg_bytes.Control::2 11760 413system.ruby.network.routers2.msg_bytes.Data::2 105552 414system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 415system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 416system.ruby.network.msg_count.Control 4410 417system.ruby.network.msg_count.Data 4398 418system.ruby.network.msg_count.Response_Data 4410 419system.ruby.network.msg_count.Writeback_Control 4398 420system.ruby.network.msg_byte.Control 35280 421system.ruby.network.msg_byte.Data 316656 422system.ruby.network.msg_byte.Response_Data 317520 423system.ruby.network.msg_byte.Writeback_Control 35184 424system.ruby.network.routers0.throttle0.link_utilization 7.325511 425system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 426system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 427system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 428system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 429system.ruby.network.routers0.throttle1.link_utilization 7.309560 430system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 431system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 432system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 433system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 434system.ruby.network.routers1.throttle0.link_utilization 7.309560 435system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 436system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 437system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 438system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 439system.ruby.network.routers1.throttle1.link_utilization 7.325511 440system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 441system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 442system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 443system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 444system.ruby.network.routers2.throttle0.link_utilization 7.325511 445system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 446system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 447system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 448system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 449system.ruby.network.routers2.throttle1.link_utilization 7.309560 450system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 451system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 452system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 453system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552 454system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 455system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 456system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1 457system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 458system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1 459system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 460system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 461system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 462system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 463system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 464system.ruby.LD.latency_hist::bucket_size 32 465system.ruby.LD.latency_hist::max_bucket 319 466system.ruby.LD.latency_hist::samples 1132 467system.ruby.LD.latency_hist::mean 33.356007 468system.ruby.LD.latency_hist::gmean 9.984943 469system.ruby.LD.latency_hist::stdev 37.413851 470system.ruby.LD.latency_hist | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00% 471system.ruby.LD.latency_hist::total 1132 472system.ruby.LD.hit_latency_hist::bucket_size 1 473system.ruby.LD.hit_latency_hist::max_bucket 9 474system.ruby.LD.hit_latency_hist::samples 465 475system.ruby.LD.hit_latency_hist::mean 1 476system.ruby.LD.hit_latency_hist::gmean 1 477system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 478system.ruby.LD.hit_latency_hist::total 465 479system.ruby.LD.miss_latency_hist::bucket_size 32 480system.ruby.LD.miss_latency_hist::max_bucket 319 481system.ruby.LD.miss_latency_hist::samples 667 482system.ruby.LD.miss_latency_hist::mean 55.913043 483system.ruby.LD.miss_latency_hist::gmean 49.663893 484system.ruby.LD.miss_latency_hist::stdev 33.713440 485system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% 486system.ruby.LD.miss_latency_hist::total 667 487system.ruby.ST.latency_hist::bucket_size 32 488system.ruby.ST.latency_hist::max_bucket 319 489system.ruby.ST.latency_hist::samples 901 490system.ruby.ST.latency_hist::mean 12.753607 491system.ruby.ST.latency_hist::gmean 2.500911 492system.ruby.ST.latency_hist::stdev 24.939066 493system.ruby.ST.latency_hist | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% 494system.ruby.ST.latency_hist::total 901 495system.ruby.ST.hit_latency_hist::bucket_size 1 496system.ruby.ST.hit_latency_hist::max_bucket 9 497system.ruby.ST.hit_latency_hist::samples 684 498system.ruby.ST.hit_latency_hist::mean 1 499system.ruby.ST.hit_latency_hist::gmean 1 500system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 501system.ruby.ST.hit_latency_hist::total 684 502system.ruby.ST.miss_latency_hist::bucket_size 32 503system.ruby.ST.miss_latency_hist::max_bucket 319 504system.ruby.ST.miss_latency_hist::samples 217 505system.ruby.ST.miss_latency_hist::mean 49.801843 506system.ruby.ST.miss_latency_hist::gmean 44.971096 507system.ruby.ST.miss_latency_hist::stdev 27.840525 508system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% 509system.ruby.ST.miss_latency_hist::total 217 510system.ruby.IFETCH.latency_hist::bucket_size 64 511system.ruby.IFETCH.latency_hist::max_bucket 639 512system.ruby.IFETCH.latency_hist::samples 5625 513system.ruby.IFETCH.latency_hist::mean 7.715378 514system.ruby.IFETCH.latency_hist::gmean 1.529642 515system.ruby.IFETCH.latency_hist::stdev 23.186705 516system.ruby.IFETCH.latency_hist | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 517system.ruby.IFETCH.latency_hist::total 5625 518system.ruby.IFETCH.hit_latency_hist::bucket_size 1 519system.ruby.IFETCH.hit_latency_hist::max_bucket 9 520system.ruby.IFETCH.hit_latency_hist::samples 5039 521system.ruby.IFETCH.hit_latency_hist::mean 1 522system.ruby.IFETCH.hit_latency_hist::gmean 1 523system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 524system.ruby.IFETCH.hit_latency_hist::total 5039 525system.ruby.IFETCH.miss_latency_hist::bucket_size 64 526system.ruby.IFETCH.miss_latency_hist::max_bucket 639 527system.ruby.IFETCH.miss_latency_hist::samples 586 528system.ruby.IFETCH.miss_latency_hist::mean 65.460751 529system.ruby.IFETCH.miss_latency_hist::gmean 59.138692 530system.ruby.IFETCH.miss_latency_hist::stdev 37.945521 531system.ruby.IFETCH.miss_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 532system.ruby.IFETCH.miss_latency_hist::total 586 533system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 534system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 535system.ruby.Directory.miss_mach_latency_hist::samples 1470 536system.ruby.Directory.miss_mach_latency_hist::mean 58.817007 537system.ruby.Directory.miss_mach_latency_hist::gmean 52.469450 538system.ruby.Directory.miss_mach_latency_hist::stdev 35.158300 539system.ruby.Directory.miss_mach_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 540system.ruby.Directory.miss_mach_latency_hist::total 1470 541system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 542system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 543system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 544system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 545system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 546system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 547system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 548system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 549system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 550system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 551system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 552system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 553system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 554system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 555system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 556system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 557system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 558system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 559system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 560system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 561system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 562system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 563system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 564system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 565system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 566system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 567system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 568system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 569system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 570system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 55.913043 571system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.663893 572system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.713440 573system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% 574system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 575system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 576system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 577system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 578system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 49.801843 579system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.971096 580system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.840525 581system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% 582system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 583system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 584system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 585system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 586system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.460751 587system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 59.138692 588system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.945521 589system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 590system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 591system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% 592system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% 593system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% 594system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% 595system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% 596system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% 597system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% 598system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% 599system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% 600system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% 601system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% 602system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00% 603system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00% 604system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00% 605system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00% 606system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00% 607system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00% 608system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00% 609system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00% 610system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00% 611system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% 612system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% 613system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% 614system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% 615 616---------- End Simulation Statistics ---------- 617