stats.txt revision 11268
13006SN/A
23006SN/A---------- Begin Simulation Statistics ----------
34398SN/Asim_seconds                                  0.000003                       # Number of seconds simulated
410488Snilay@cs.wisc.edusim_ticks                                     2812000                       # Number of ticks simulated
510488Snilay@cs.wisc.edufinal_tick                                    2812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68540SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
711268Satgutier@umich.eduhost_inst_rate                                 121410                       # Simulator instruction rate (inst/s)
811268Satgutier@umich.eduhost_op_rate                                   121348                       # Simulator op (including micro ops) rate (op/s)
911268Satgutier@umich.eduhost_tick_rate                               60644587                       # Simulator tick rate (ticks/s)
1011268Satgutier@umich.eduhost_mem_usage                                 218112                       # Number of bytes of host memory used
1111268Satgutier@umich.eduhost_seconds                                     0.05                       # Real time elapsed on the host
1210488Snilay@cs.wisc.edusim_insts                                        5624                       # Number of instructions simulated
1310488Snilay@cs.wisc.edusim_ops                                          5624                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1610488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst             22500                       # Number of bytes read from this memory
1710488Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data              4289                       # Number of bytes read from this memory
1810488Snilay@cs.wisc.edusystem.physmem.bytes_read::total                26789                       # Number of bytes read from this memory
1910488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst        22500                       # Number of instructions bytes read from this memory
2010488Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total           22500                       # Number of instructions bytes read from this memory
2110488Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu.data           3601                       # Number of bytes written to this memory
2210488Snilay@cs.wisc.edusystem.physmem.bytes_written::total              3601                       # Number of bytes written to this memory
2310488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst               5625                       # Number of read requests responded to by this memory
2410488Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data               1132                       # Number of read requests responded to by this memory
2510488Snilay@cs.wisc.edusystem.physmem.num_reads::total                  6757                       # Number of read requests responded to by this memory
2610488Snilay@cs.wisc.edusystem.physmem.num_writes::cpu.data               901                       # Number of write requests responded to by this memory
2710488Snilay@cs.wisc.edusystem.physmem.num_writes::total                  901                       # Number of write requests responded to by this memory
2810488Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst           8001422475                       # Total read bandwidth from this memory (bytes/s)
2910488Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data           1525248933                       # Total read bandwidth from this memory (bytes/s)
3010488Snilay@cs.wisc.edusystem.physmem.bw_read::total              9526671408                       # Total read bandwidth from this memory (bytes/s)
3110488Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst      8001422475                       # Instruction read bandwidth from this memory (bytes/s)
3210488Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total         8001422475                       # Instruction read bandwidth from this memory (bytes/s)
3310488Snilay@cs.wisc.edusystem.physmem.bw_write::cpu.data          1280583215                       # Write bandwidth from this memory (bytes/s)
3410488Snilay@cs.wisc.edusystem.physmem.bw_write::total             1280583215                       # Write bandwidth from this memory (bytes/s)
3510488Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst          8001422475                       # Total bandwidth to/from this memory (bytes/s)
3610488Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data          2805832148                       # Total bandwidth to/from this memory (bytes/s)
3710488Snilay@cs.wisc.edusystem.physmem.bw_total::total            10807254623                       # Total bandwidth to/from this memory (bytes/s)
3810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
398540SN/Asystem.cpu.dtb.read_hits                            0                       # DTB read hits
408540SN/Asystem.cpu.dtb.read_misses                          0                       # DTB read misses
418540SN/Asystem.cpu.dtb.read_accesses                        0                       # DTB read accesses
428540SN/Asystem.cpu.dtb.write_hits                           0                       # DTB write hits
438540SN/Asystem.cpu.dtb.write_misses                         0                       # DTB write misses
448540SN/Asystem.cpu.dtb.write_accesses                       0                       # DTB write accesses
455510SN/Asystem.cpu.dtb.hits                                 0                       # DTB hits
465510SN/Asystem.cpu.dtb.misses                               0                       # DTB misses
478540SN/Asystem.cpu.dtb.accesses                             0                       # DTB accesses
488540SN/Asystem.cpu.itb.read_hits                            0                       # DTB read hits
498540SN/Asystem.cpu.itb.read_misses                          0                       # DTB read misses
508540SN/Asystem.cpu.itb.read_accesses                        0                       # DTB read accesses
518540SN/Asystem.cpu.itb.write_hits                           0                       # DTB write hits
528540SN/Asystem.cpu.itb.write_misses                         0                       # DTB write misses
538540SN/Asystem.cpu.itb.write_accesses                       0                       # DTB write accesses
545510SN/Asystem.cpu.itb.hits                                 0                       # DTB hits
555510SN/Asystem.cpu.itb.misses                               0                       # DTB misses
568540SN/Asystem.cpu.itb.accesses                             0                       # DTB accesses
5710488Snilay@cs.wisc.edusystem.cpu.workload.num_syscalls                    7                       # Number of system calls
5810488Snilay@cs.wisc.edusystem.cpu.numCycles                             5625                       # number of cpu cycles simulated
598540SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
607935SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
6110488Snilay@cs.wisc.edusystem.cpu.committedInsts                        5624                       # Number of instructions committed
6210488Snilay@cs.wisc.edusystem.cpu.committedOps                          5624                       # Number of ops (including micro ops) committed
6310488Snilay@cs.wisc.edusystem.cpu.num_int_alu_accesses                  4944                       # Number of integer alu accesses
648540SN/Asystem.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
6510488Snilay@cs.wisc.edusystem.cpu.num_func_calls                         190                       # number of times a function call or return occured
6610488Snilay@cs.wisc.edusystem.cpu.num_conditional_control_insts          649                       # number of instructions that are conditional controls
6710488Snilay@cs.wisc.edusystem.cpu.num_int_insts                         4944                       # number of integer instructions
687935SN/Asystem.cpu.num_fp_insts                             2                       # number of float instructions
6910488Snilay@cs.wisc.edusystem.cpu.num_int_register_reads                7054                       # number of times the integer registers were read
7010488Snilay@cs.wisc.edusystem.cpu.num_int_register_writes               3281                       # number of times the integer registers were written
717935SN/Asystem.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
727935SN/Asystem.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
7310488Snilay@cs.wisc.edusystem.cpu.num_mem_refs                          2034                       # number of memory refs
7410488Snilay@cs.wisc.edusystem.cpu.num_load_insts                        1132                       # Number of load instructions
7510488Snilay@cs.wisc.edusystem.cpu.num_store_insts                        902                       # Number of store instructions
767935SN/Asystem.cpu.num_idle_cycles                          0                       # Number of idle cycles
7710488Snilay@cs.wisc.edusystem.cpu.num_busy_cycles                       5625                       # Number of busy cycles
788540SN/Asystem.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
798540SN/Asystem.cpu.idle_fraction                            0                       # Percentage of idle cycles
8010488Snilay@cs.wisc.edusystem.cpu.Branches                               883                       # Number of branches fetched
8110488Snilay@cs.wisc.edusystem.cpu.op_class::No_OpClass                   637     11.32%     11.32% # Class of executed instruction
8210488Snilay@cs.wisc.edusystem.cpu.op_class::IntAlu                      2950     52.44%     63.77% # Class of executed instruction
8310488Snilay@cs.wisc.edusystem.cpu.op_class::IntMult                        2      0.04%     63.80% # Class of executed instruction
8410488Snilay@cs.wisc.edusystem.cpu.op_class::IntDiv                         0      0.00%     63.80% # Class of executed instruction
8510488Snilay@cs.wisc.edusystem.cpu.op_class::FloatAdd                       2      0.04%     63.84% # Class of executed instruction
8610488Snilay@cs.wisc.edusystem.cpu.op_class::FloatCmp                       0      0.00%     63.84% # Class of executed instruction
8710488Snilay@cs.wisc.edusystem.cpu.op_class::FloatCvt                       0      0.00%     63.84% # Class of executed instruction
8810488Snilay@cs.wisc.edusystem.cpu.op_class::FloatMult                      0      0.00%     63.84% # Class of executed instruction
8910488Snilay@cs.wisc.edusystem.cpu.op_class::FloatDiv                       0      0.00%     63.84% # Class of executed instruction
9010488Snilay@cs.wisc.edusystem.cpu.op_class::FloatSqrt                      0      0.00%     63.84% # Class of executed instruction
9110488Snilay@cs.wisc.edusystem.cpu.op_class::SimdAdd                        0      0.00%     63.84% # Class of executed instruction
9210488Snilay@cs.wisc.edusystem.cpu.op_class::SimdAddAcc                     0      0.00%     63.84% # Class of executed instruction
9310488Snilay@cs.wisc.edusystem.cpu.op_class::SimdAlu                        0      0.00%     63.84% # Class of executed instruction
9410488Snilay@cs.wisc.edusystem.cpu.op_class::SimdCmp                        0      0.00%     63.84% # Class of executed instruction
9510488Snilay@cs.wisc.edusystem.cpu.op_class::SimdCvt                        0      0.00%     63.84% # Class of executed instruction
9610488Snilay@cs.wisc.edusystem.cpu.op_class::SimdMisc                       0      0.00%     63.84% # Class of executed instruction
9710488Snilay@cs.wisc.edusystem.cpu.op_class::SimdMult                       0      0.00%     63.84% # Class of executed instruction
9810488Snilay@cs.wisc.edusystem.cpu.op_class::SimdMultAcc                    0      0.00%     63.84% # Class of executed instruction
9910488Snilay@cs.wisc.edusystem.cpu.op_class::SimdShift                      0      0.00%     63.84% # Class of executed instruction
10010488Snilay@cs.wisc.edusystem.cpu.op_class::SimdShiftAcc                   0      0.00%     63.84% # Class of executed instruction
10110488Snilay@cs.wisc.edusystem.cpu.op_class::SimdSqrt                       0      0.00%     63.84% # Class of executed instruction
10210488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatAdd                   0      0.00%     63.84% # Class of executed instruction
10310488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatAlu                   0      0.00%     63.84% # Class of executed instruction
10410488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatCmp                   0      0.00%     63.84% # Class of executed instruction
10510488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatCvt                   0      0.00%     63.84% # Class of executed instruction
10610488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatDiv                   0      0.00%     63.84% # Class of executed instruction
10710488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatMisc                  0      0.00%     63.84% # Class of executed instruction
10810488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatMult                  0      0.00%     63.84% # Class of executed instruction
10910488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.84% # Class of executed instruction
11010488Snilay@cs.wisc.edusystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.84% # Class of executed instruction
11110488Snilay@cs.wisc.edusystem.cpu.op_class::MemRead                     1132     20.12%     83.96% # Class of executed instruction
11210488Snilay@cs.wisc.edusystem.cpu.op_class::MemWrite                     902     16.04%    100.00% # Class of executed instruction
11310220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
11410220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
11510488Snilay@cs.wisc.edusystem.cpu.op_class::total                       5625                       # Class of executed instruction
11611268Satgutier@umich.edusystem.membus.trans_dist::ReadReq                6757                       # Transaction distribution
11711268Satgutier@umich.edusystem.membus.trans_dist::ReadResp               6757                       # Transaction distribution
11811268Satgutier@umich.edusystem.membus.trans_dist::WriteReq                901                       # Transaction distribution
11911268Satgutier@umich.edusystem.membus.trans_dist::WriteResp               901                       # Transaction distribution
12011268Satgutier@umich.edusystem.membus.pkt_count_system.cpu.icache_port::system.physmem.port        11250                       # Packet count per connected master and slave (bytes)
12111268Satgutier@umich.edusystem.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         4066                       # Packet count per connected master and slave (bytes)
12211268Satgutier@umich.edusystem.membus.pkt_count::total                  15316                       # Packet count per connected master and slave (bytes)
12311268Satgutier@umich.edusystem.membus.pkt_size_system.cpu.icache_port::system.physmem.port        22500                       # Cumulative packet size per connected master and slave (bytes)
12411268Satgutier@umich.edusystem.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         7890                       # Cumulative packet size per connected master and slave (bytes)
12511268Satgutier@umich.edusystem.membus.pkt_size::total                   30390                       # Cumulative packet size per connected master and slave (bytes)
12611268Satgutier@umich.edusystem.membus.snoops                                0                       # Total snoops (count)
12711268Satgutier@umich.edusystem.membus.snoop_fanout::samples              7658                       # Request fanout histogram
12811268Satgutier@umich.edusystem.membus.snoop_fanout::mean             0.734526                       # Request fanout histogram
12911268Satgutier@umich.edusystem.membus.snoop_fanout::stdev            0.441614                       # Request fanout histogram
13011268Satgutier@umich.edusystem.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
13111268Satgutier@umich.edusystem.membus.snoop_fanout::0                    2033     26.55%     26.55% # Request fanout histogram
13211268Satgutier@umich.edusystem.membus.snoop_fanout::1                    5625     73.45%    100.00% # Request fanout histogram
13311268Satgutier@umich.edusystem.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
13411268Satgutier@umich.edusystem.membus.snoop_fanout::min_value               0                       # Request fanout histogram
13511268Satgutier@umich.edusystem.membus.snoop_fanout::max_value               1                       # Request fanout histogram
13611268Satgutier@umich.edusystem.membus.snoop_fanout::total                7658                       # Request fanout histogram
1373006SN/A
1383006SN/A---------- End Simulation Statistics   ----------
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