stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17026500 # Number of ticks simulated 5final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 44899 # Simulator instruction rate (inst/s) 8host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 148205995 # Simulator tick rate (ticks/s) 10host_mem_usage 226388 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 478 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 478 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30592 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 16967000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 478 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes 88system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 152system.physmem.totQLat 2863000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests 154system.physmem.totBusLat 2390000 # Total cycles spent in databus access 155system.physmem.totBankLat 9363750 # Total cycles spent in bank access 156system.physmem.avgQLat 5989.54 # Average queueing delay per request 157system.physmem.avgBankLat 19589.44 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request 159system.physmem.avgMemAccLat 30578.97 # Average memory access latency 160system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 14.04 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.86 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 351 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 172system.physmem.avgGap 35495.82 # Average gap between requests 173system.cpu.branchPred.lookups 2222 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 508 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 182system.cpu.dtb.read_hits 0 # DTB read hits 183system.cpu.dtb.read_misses 0 # DTB read misses 184system.cpu.dtb.read_accesses 0 # DTB read accesses 185system.cpu.dtb.write_hits 0 # DTB write hits 186system.cpu.dtb.write_misses 0 # DTB write misses 187system.cpu.dtb.write_accesses 0 # DTB write accesses 188system.cpu.dtb.hits 0 # DTB hits 189system.cpu.dtb.misses 0 # DTB misses 190system.cpu.dtb.accesses 0 # DTB accesses 191system.cpu.itb.read_hits 0 # DTB read hits 192system.cpu.itb.read_misses 0 # DTB read misses 193system.cpu.itb.read_accesses 0 # DTB read accesses 194system.cpu.itb.write_hits 0 # DTB write hits 195system.cpu.itb.write_misses 0 # DTB write misses 196system.cpu.itb.write_accesses 0 # DTB write accesses 197system.cpu.itb.hits 0 # DTB hits 198system.cpu.itb.misses 0 # DTB misses 199system.cpu.itb.accesses 0 # DTB accesses 200system.cpu.workload.num_syscalls 8 # Number of system calls 201system.cpu.numCycles 34054 # number of cpu cycles simulated 202system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 203system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 204system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss 205system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed 206system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered 207system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken 208system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked 209system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing 210system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked 211system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 212system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched 213system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed 214system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle 232system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle 233system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle 234system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked 235system.cpu.decode.RunCycles 3094 # Number of cycles decode is running 236system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking 237system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing 238system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch 239system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction 240system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode 241system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 242system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing 243system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle 244system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking 245system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst 246system.cpu.rename.RunCycles 2958 # Number of cycles rename is running 247system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking 248system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename 249system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 250system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 251system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full 252system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed 253system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made 254system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups 255system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 256system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 257system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing 258system.cpu.rename.serializingInsts 18 # count of serializing insts renamed 259system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed 260system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer 261system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. 262system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. 263system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 264system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 265system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) 266system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ 267system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued 268system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued 269system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling 270system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph 271system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed 272system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle 289system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 290system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available 291system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available 292system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available 294system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available 295system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available 319system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available 320system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available 321system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 322system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 323system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 324system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued 325system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued 326system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued 328system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued 329system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued 330system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued 353system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued 354system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued 355system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 356system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 357system.cpu.iq.FU_type_0::total 8325 # Type of FU issued 358system.cpu.iq.rate 0.244465 # Inst issue rate 359system.cpu.iq.fu_busy_cnt 159 # FU busy when requested 360system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) 361system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads 362system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes 363system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses 364system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 365system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 366system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 367system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses 368system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 369system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores 370system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 371system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed 372system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 373system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations 374system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed 375system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 376system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 377system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 378system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked 379system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 380system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing 381system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking 382system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 383system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ 384system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch 385system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions 386system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions 387system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions 388system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 389system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 390system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 391system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly 392system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly 393system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute 394system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions 395system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed 396system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute 397system.cpu.iew.exec_swp 0 # number of swp insts executed 398system.cpu.iew.exec_nop 1547 # number of nop insts executed 399system.cpu.iew.exec_refs 3203 # number of memory reference insts executed 400system.cpu.iew.exec_branches 1355 # Number of branches executed 401system.cpu.iew.exec_stores 1078 # Number of stores executed 402system.cpu.iew.exec_rate 0.233042 # Inst execution rate 403system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit 404system.cpu.iew.wb_count 7471 # cumulative count of insts written-back 405system.cpu.iew.wb_producers 2950 # num instructions producing a value 406system.cpu.iew.wb_consumers 4259 # num instructions consuming a value 407system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 408system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle 409system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back 410system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 411system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit 412system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 413system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 414system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle 431system.cpu.commit.committedInsts 5813 # Number of instructions committed 432system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 433system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 434system.cpu.commit.refs 2088 # Number of memory references committed 435system.cpu.commit.loads 1163 # Number of loads committed 436system.cpu.commit.membars 0 # Number of memory barriers committed 437system.cpu.commit.branches 915 # Number of branches committed 438system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 439system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 440system.cpu.commit.function_calls 87 # Number of function calls committed. 441system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached 442system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 443system.cpu.rob.rob_reads 23973 # The number of ROB reads 444system.cpu.rob.rob_writes 22610 # The number of ROB writes 445system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself 446system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling 447system.cpu.committedInsts 5156 # Number of Instructions Simulated 448system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 449system.cpu.committedInsts_total 5156 # Number of Instructions Simulated 450system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction 451system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads 452system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle 453system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads 454system.cpu.int_regfile_reads 10756 # number of integer regfile reads 455system.cpu.int_regfile_writes 5239 # number of integer regfile writes 456system.cpu.fp_regfile_reads 3 # number of floating regfile reads 457system.cpu.fp_regfile_writes 1 # number of floating regfile writes 458system.cpu.misc_regfile_reads 150 # number of misc regfile reads 459system.cpu.icache.replacements 17 # number of replacements 460system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use 461system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. 462system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. 463system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. 464system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 465system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor 466system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy 467system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy 468system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits 469system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits 470system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits 471system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits 472system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits 473system.cpu.icache.overall_hits::total 1566 # number of overall hits 474system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses 475system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses 476system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses 477system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses 478system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses 479system.cpu.icache.overall_misses::total 447 # number of overall misses 480system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles 481system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles 482system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles 483system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles 484system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles 485system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles 486system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) 487system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) 488system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses 489system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses 490system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses 491system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses 492system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses 493system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses 494system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses 495system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses 496system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses 497system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses 498system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency 499system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency 500system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency 501system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency 502system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency 503system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency 504system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked 505system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 506system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 507system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 508system.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked 509system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 510system.cpu.icache.fast_writes 0 # number of fast writes performed 511system.cpu.icache.cache_copies 0 # number of cache copies performed 512system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 513system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 514system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 515system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 516system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 517system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 518system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 519system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 520system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 521system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses 522system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 523system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses 524system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17822000 # number of ReadReq MSHR miss cycles 525system.cpu.icache.ReadReq_mshr_miss_latency::total 17822000 # number of ReadReq MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17822000 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.demand_mshr_miss_latency::total 17822000 # number of demand (read+write) MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17822000 # number of overall MSHR miss cycles 529system.cpu.icache.overall_mshr_miss_latency::total 17822000 # number of overall MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for ReadReq accesses 531system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168405 # mshr miss rate for ReadReq accesses 532system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for demand accesses 533system.cpu.icache.demand_mshr_miss_rate::total 0.168405 # mshr miss rate for demand accesses 534system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168405 # mshr miss rate for overall accesses 535system.cpu.icache.overall_mshr_miss_rate::total 0.168405 # mshr miss rate for overall accesses 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52572.271386 # average ReadReq mshr miss latency 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52572.271386 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency 542system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 543system.cpu.l2cache.replacements 0 # number of replacements 544system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use 545system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 546system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. 547system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. 548system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 549system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor 550system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor 551system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy 552system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy 553system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy 554system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 555system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 556system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 559system.cpu.l2cache.overall_hits::total 3 # number of overall hits 560system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses 561system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 562system.cpu.l2cache.ReadReq_misses::total 427 # number of ReadReq misses 563system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 564system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 565system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 567system.cpu.l2cache.demand_misses::total 478 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 570system.cpu.l2cache.overall_misses::total 478 # number of overall misses 571system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17452500 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5919000 # number of ReadReq miss cycles 573system.cpu.l2cache.ReadReq_miss_latency::total 23371500 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2657000 # number of ReadExReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::total 2657000 # number of ReadExReq miss cycles 576system.cpu.l2cache.demand_miss_latency::cpu.inst 17452500 # number of demand (read+write) miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.data 8576000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::total 26028500 # number of demand (read+write) miss cycles 579system.cpu.l2cache.overall_miss_latency::cpu.inst 17452500 # number of overall miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.data 8576000 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::total 26028500 # number of overall miss cycles 582system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 586system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 587system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses 588system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 589system.cpu.l2cache.demand_accesses::total 481 # number of demand (read+write) accesses 590system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses 591system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 592system.cpu.l2cache.overall_accesses::total 481 # number of overall (read+write) accesses 593system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991150 # miss rate for ReadReq accesses 594system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 595system.cpu.l2cache.ReadReq_miss_rate::total 0.993023 # miss rate for ReadReq accesses 596system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 597system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 598system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991150 # miss rate for demand accesses 599system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 600system.cpu.l2cache.demand_miss_rate::total 0.993763 # miss rate for demand accesses 601system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses 602system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 603system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses 604system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51941.964286 # average ReadReq miss latency 605system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65043.956044 # average ReadReq miss latency 606system.cpu.l2cache.ReadReq_avg_miss_latency::total 54734.192037 # average ReadReq miss latency 607system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency 608system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency 609system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency 610system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency 611system.cpu.l2cache.demand_avg_miss_latency::total 54452.928870 # average overall miss latency 612system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency 613system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::total 54452.928870 # average overall miss latency 615system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 620system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 621system.cpu.l2cache.fast_writes 0 # number of fast writes performed 622system.cpu.l2cache.cache_copies 0 # number of cache copies performed 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 625system.cpu.l2cache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses 626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 627system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 628system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 629system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 630system.cpu.l2cache.demand_mshr_misses::total 478 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 632system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 633system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses 634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles 635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles 636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles 638system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles 639system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles 640system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles 643system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles 645system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for demand accesses 651system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 652system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses 653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses 654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 655system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses 656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency 659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency 663system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency 665system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency 666system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency 667system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 668system.cpu.dcache.replacements 0 # number of replacements 669system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use 670system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. 671system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 672system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. 673system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 674system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor 675system.cpu.dcache.occ_percent::cpu.data 0.022374 # Average percentage of cache occupancy 676system.cpu.dcache.occ_percent::total 0.022374 # Average percentage of cache occupancy 677system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits 678system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits 679system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits 680system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits 681system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits 682system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits 683system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits 684system.cpu.dcache.overall_hits::total 2424 # number of overall hits 685system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 686system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 687system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses 688system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses 689system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses 692system.cpu.dcache.overall_misses::total 501 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 9019500 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 9019500 # number of ReadReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles 697system.cpu.dcache.demand_miss_latency::cpu.data 24118499 # number of demand (read+write) miss cycles 698system.cpu.dcache.demand_miss_latency::total 24118499 # number of demand (read+write) miss cycles 699system.cpu.dcache.overall_miss_latency::cpu.data 24118499 # number of overall miss cycles 700system.cpu.dcache.overall_miss_latency::total 24118499 # number of overall miss cycles 701system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) 702system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) 703system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 704system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 705system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses 706system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses 707system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses 708system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses 709system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses 710system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses 711system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses 712system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses 713system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses 714system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses 715system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses 716system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses 717system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency 718system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency 719system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency 720system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency 721system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency 722system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency 723system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency 724system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency 725system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked 726system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 728system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 729system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked 730system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.dcache.fast_writes 0 # number of fast writes performed 732system.cpu.dcache.cache_copies 0 # number of cache copies performed 733system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 734system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 735system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits 736system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits 737system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits 738system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits 739system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits 740system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits 741system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 742system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 743system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 744system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 745system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 746system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 747system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 748system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 749system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles 750system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles 751system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles 752system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles 753system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles 754system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles 755system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles 756system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles 757system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses 758system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses 759system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 760system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses 762system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses 763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses 764system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses 765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency 769system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency 770system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency 771system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency 772system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency 773system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 774 775---------- End Simulation Statistics ---------- 776