stats.txt revision 10488:7c27480a5031
17404SAli.Saidi@ARM.com 29015Sandreas.hansson@arm.com---------- Begin Simulation Statistics ---------- 37404SAli.Saidi@ARM.comsim_seconds 0.000021 # Number of seconds simulated 47404SAli.Saidi@ARM.comsim_ticks 21163500 # Number of ticks simulated 57404SAli.Saidi@ARM.comfinal_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67404SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 77404SAli.Saidi@ARM.comhost_inst_rate 24711 # Simulator instruction rate (inst/s) 87404SAli.Saidi@ARM.comhost_op_rate 24708 # Simulator op (including micro ops) rate (op/s) 97404SAli.Saidi@ARM.comhost_tick_rate 104867636 # Simulator tick rate (ticks/s) 107404SAli.Saidi@ARM.comhost_mem_usage 278232 # Number of bytes of host memory used 117404SAli.Saidi@ARM.comhost_seconds 0.20 # Real time elapsed on the host 127404SAli.Saidi@ARM.comsim_insts 4986 # Number of instructions simulated 137404SAli.Saidi@ARM.comsim_ops 4986 # Number of ops (including micro ops) simulated 147404SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 157404SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 167404SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory 177404SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 187404SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 30144 # Number of bytes read from this memory 197404SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory 207404SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory 217404SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory 227404SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 237404SAli.Saidi@ARM.comsystem.physmem.num_reads::total 471 # Number of read requests responded to by this memory 247404SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) 257404SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) 267404SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) 277404SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) 287404SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) 297404SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) 307404SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) 317404SAli.Saidi@ARM.comsystem.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) 327404SAli.Saidi@ARM.comsystem.physmem.readReqs 471 # Number of read requests accepted 337404SAli.Saidi@ARM.comsystem.physmem.writeReqs 0 # Number of write requests accepted 347404SAli.Saidi@ARM.comsystem.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue 357404SAli.Saidi@ARM.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 367404SAli.Saidi@ARM.comsystem.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM 377404SAli.Saidi@ARM.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 387404SAli.Saidi@ARM.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 397404SAli.Saidi@ARM.comsystem.physmem.bytesReadSys 30144 # Total read bytes from the system interface side 407404SAli.Saidi@ARM.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 417404SAli.Saidi@ARM.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 427404SAli.Saidi@ARM.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 437578Sdam.sunwoo@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 447578Sdam.sunwoo@arm.comsystem.physmem.perBankRdBursts::0 29 # Per bank write bursts 457404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::1 0 # Per bank write bursts 467404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::2 1 # Per bank write bursts 479016Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 0 # Per bank write bursts 487404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::4 7 # Per bank write bursts 497404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::5 3 # Per bank write bursts 507404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::6 13 # Per bank write bursts 517404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::7 53 # Per bank write bursts 527878Sgblack@eecs.umich.edusystem.physmem.perBankRdBursts::8 59 # Per bank write bursts 537404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::9 76 # Per bank write bursts 547404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::10 43 # Per bank write bursts 557404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::11 20 # Per bank write bursts 567404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::12 51 # Per bank write bursts 577404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::13 29 # Per bank write bursts 587404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::14 80 # Per bank write bursts 597404SAli.Saidi@ARM.comsystem.physmem.perBankRdBursts::15 7 # Per bank write bursts 607404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 617404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 627694SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 637404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 647404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 657404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 667404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 677404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 687404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 697404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 707404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 717404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 727436Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 737404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 747404SAli.Saidi@ARM.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 757436Sdam.sunwoo@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 767436Sdam.sunwoo@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 777436Sdam.sunwoo@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 787436Sdam.sunwoo@arm.comsystem.physmem.totGap 21083000 # Total gap between requests 797404SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 807404SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 817404SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 827404SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 837404SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 847404SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 857404SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 471 # Read request sizes (log2) 867404SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 877404SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 887404SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 897404SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 907404SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 917404SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 927404SAli.Saidi@ARM.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 937404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see 947404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 957946SGiacomo.Gabrielli@arm.comsystem.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see 967404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 977694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 987694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 997694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1007694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1017694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1027946SGiacomo.Gabrielli@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1037694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1047694SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1057404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1067404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1077404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1087404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1097404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1107404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1117946SGiacomo.Gabrielli@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1127404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1137404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1147404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1157404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1167404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1177608SGene.Wu@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1187404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1197404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1207404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1217404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1227404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1237608SGene.Wu@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1247404SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1257404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1267404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1277404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1287404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1297946SGiacomo.Gabrielli@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1307404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1317404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1327404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1337404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1347404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1357946SGiacomo.Gabrielli@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1367404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1377404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1387404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1397404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1407404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1417946SGiacomo.Gabrielli@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1427404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1437404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1447436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1457436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1467436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1477436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1487436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1497404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1507404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1517946SGiacomo.Gabrielli@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1527404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1537404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1547436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1557436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1567436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1577436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1587436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 1597436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 1607436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 1617436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 1627436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 1637436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 1647436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 1657436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 1667436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 1677436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 1687436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 1697436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 1707436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 1717436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 1727436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 1737436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 1747404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 1757404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 1767404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 1777404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 1787404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 1797436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 1807404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 1817404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 1827436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 1837436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 1847436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 1857436Sdam.sunwoo@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 1867404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 1877404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 1887404SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 1897946SGiacomo.Gabrielli@arm.comsystem.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 1907404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation 1917404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation 1927404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation 1937404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation 1947404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation 1957404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation 1967404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation 1977404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation 1987404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation 1997404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation 2007404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation 2017404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 2027404SAli.Saidi@ARM.comsystem.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 2037404SAli.Saidi@ARM.comsystem.physmem.totQLat 5392000 # Total ticks spent queuing 2047404SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM 2057404SAli.Saidi@ARM.comsystem.physmem.totBusLat 2355000 # Total ticks spent in databus transfers 2067404SAli.Saidi@ARM.comsystem.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst 2077404SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 2087404SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst 2097404SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s 2107404SAli.Saidi@ARM.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 2117404SAli.Saidi@ARM.comsystem.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s 2127404SAli.Saidi@ARM.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2137404SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 2147404SAli.Saidi@ARM.comsystem.physmem.busUtil 11.13 # Data bus utilization in percentage 2157404SAli.Saidi@ARM.comsystem.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads 2167404SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 2177404SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing 2187404SAli.Saidi@ARM.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 2197404SAli.Saidi@ARM.comsystem.physmem.readRowHits 356 # Number of row buffer hits during reads 2207946SGiacomo.Gabrielli@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 2217946SGiacomo.Gabrielli@arm.comsystem.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 2227404SAli.Saidi@ARM.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 2237404SAli.Saidi@ARM.comsystem.physmem.avgGap 44762.21 # Average gap between requests 2247404SAli.Saidi@ARM.comsystem.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined 2257404SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::IDLE 11000 # Time in different power states 2267404SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 2277404SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 2287404SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::ACT 15315250 # Time in different power states 2297404SAli.Saidi@ARM.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 2307694SAli.Saidi@ARM.comsystem.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) 2317694SAli.Saidi@ARM.comsystem.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) 2327694SAli.Saidi@ARM.comsystem.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) 2337694SAli.Saidi@ARM.comsystem.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) 2347694SAli.Saidi@ARM.comsystem.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) 2357694SAli.Saidi@ARM.comsystem.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) 2367694SAli.Saidi@ARM.comsystem.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 2377694SAli.Saidi@ARM.comsystem.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 2387694SAli.Saidi@ARM.comsystem.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) 2397436Sdam.sunwoo@arm.comsystem.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) 2407436Sdam.sunwoo@arm.comsystem.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) 2417436Sdam.sunwoo@arm.comsystem.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) 2427436Sdam.sunwoo@arm.comsystem.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) 2437436Sdam.sunwoo@arm.comsystem.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) 2447436Sdam.sunwoo@arm.comsystem.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) 2457436Sdam.sunwoo@arm.comsystem.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) 2467436Sdam.sunwoo@arm.comsystem.physmem.averagePower::0 790.713406 # Core power per rank (mW) 2477436Sdam.sunwoo@arm.comsystem.physmem.averagePower::1 944.255803 # Core power per rank (mW) 2487436Sdam.sunwoo@arm.comsystem.membus.trans_dist::ReadReq 421 # Transaction distribution 2497436Sdam.sunwoo@arm.comsystem.membus.trans_dist::ReadResp 421 # Transaction distribution 2507436Sdam.sunwoo@arm.comsystem.membus.trans_dist::ReadExReq 50 # Transaction distribution 2517436Sdam.sunwoo@arm.comsystem.membus.trans_dist::ReadExResp 50 # Transaction distribution 2527436Sdam.sunwoo@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) 2537436Sdam.sunwoo@arm.comsystem.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) 2547436Sdam.sunwoo@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) 2557436Sdam.sunwoo@arm.comsystem.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) 2567436Sdam.sunwoo@arm.comsystem.membus.snoops 0 # Total snoops (count) 2577436Sdam.sunwoo@arm.comsystem.membus.snoop_fanout::samples 471 # Request fanout histogram 2587436Sdam.sunwoo@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 2597436Sdam.sunwoo@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 2607404SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2617404SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram 2629015Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 2639015Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2649015Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 2659015Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 2669015Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 471 # Request fanout histogram 2679015Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) 2689015Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 2699015Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) 2709015Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 20.9 # Layer utilization (%) 2719015Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2729015Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2146 # Number of BP lookups 2739015Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted 2749015Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect 2759015Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups 2769015Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 528 # Number of BTB hits 2779015Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2789015Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage 2799015Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. 2809015Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 2819015Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 2829015Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 2839015Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 2849015Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 2859015Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 2869015Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 2879015Sandreas.hansson@arm.comsystem.cpu.dtb.hits 0 # DTB hits 2889015Sandreas.hansson@arm.comsystem.cpu.dtb.misses 0 # DTB misses 2899015Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 2909015Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 2919015Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 2929015Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 2939015Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 2949015Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 2959015Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 2967439Sdam.sunwoo@arm.comsystem.cpu.itb.hits 0 # DTB hits 2977439Sdam.sunwoo@arm.comsystem.cpu.itb.misses 0 # DTB misses 2987439Sdam.sunwoo@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 2997439Sdam.sunwoo@arm.comsystem.cpu.workload.num_syscalls 7 # Number of system calls 3007439Sdam.sunwoo@arm.comsystem.cpu.numCycles 42328 # number of cpu cycles simulated 3017439Sdam.sunwoo@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3027439Sdam.sunwoo@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 3037439Sdam.sunwoo@arm.comsystem.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss 3047439Sdam.sunwoo@arm.comsystem.cpu.fetch.Insts 13064 # Number of instructions fetch has processed 3057439Sdam.sunwoo@arm.comsystem.cpu.fetch.Branches 2146 # Number of branches that fetch encountered 3067439Sdam.sunwoo@arm.comsystem.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken 3077439Sdam.sunwoo@arm.comsystem.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked 3087439Sdam.sunwoo@arm.comsystem.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing 3097439Sdam.sunwoo@arm.comsystem.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps 3107439Sdam.sunwoo@arm.comsystem.cpu.fetch.CacheLines 2037 # Number of cache lines fetched 3117439Sdam.sunwoo@arm.comsystem.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed 3127439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) 3137439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) 3147439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) 3157439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 3167439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) 3177439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) 3187439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) 3197439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) 3207439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) 3217439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) 3227439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) 3237439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) 3247439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) 3257439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3267439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3277439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 3287439Sdam.sunwoo@arm.comsystem.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) 3297439Sdam.sunwoo@arm.comsystem.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle 3307439Sdam.sunwoo@arm.comsystem.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle 3318733Sgeoffrey.blake@arm.comsystem.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle 3328733Sgeoffrey.blake@arm.comsystem.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked 3338733Sgeoffrey.blake@arm.comsystem.cpu.decode.RunCycles 2791 # Number of cycles decode is running 3347439Sdam.sunwoo@arm.comsystem.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking 3357439Sdam.sunwoo@arm.comsystem.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing 3367439Sdam.sunwoo@arm.comsystem.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch 3377439Sdam.sunwoo@arm.comsystem.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 3387439Sdam.sunwoo@arm.comsystem.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode 3397439Sdam.sunwoo@arm.comsystem.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode 3407439Sdam.sunwoo@arm.comsystem.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 3417439Sdam.sunwoo@arm.comsystem.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle 3427439Sdam.sunwoo@arm.comsystem.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking 3437439Sdam.sunwoo@arm.comsystem.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst 3447439Sdam.sunwoo@arm.comsystem.cpu.rename.RunCycles 2743 # Number of cycles rename is running 3457439Sdam.sunwoo@arm.comsystem.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking 3467439Sdam.sunwoo@arm.comsystem.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename 3477439Sdam.sunwoo@arm.comsystem.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 3487439Sdam.sunwoo@arm.comsystem.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 3497439Sdam.sunwoo@arm.comsystem.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full 3507439Sdam.sunwoo@arm.comsystem.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full 3517439Sdam.sunwoo@arm.comsystem.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed 3527653Sgene.wu@arm.comsystem.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made 3537653Sgene.wu@arm.comsystem.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups 3547653Sgene.wu@arm.comsystem.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 3557653Sgene.wu@arm.comsystem.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed 3567653Sgene.wu@arm.comsystem.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing 3577653Sgene.wu@arm.comsystem.cpu.rename.serializingInsts 13 # count of serializing insts renamed 3587439Sdam.sunwoo@arm.comsystem.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 3597728SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 298 # count of insts added to the skid buffer 3607728SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. 3618902Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. 3627728SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 3637728SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. 3647404SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) 3659015Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ 3667404SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8280 # Number of instructions issued 3677404SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 3687404SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling 3697404SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph 3707404SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 3717404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle 3727404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle 3737439Sdam.sunwoo@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle 3747437Sdam.sunwoo@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3757728SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle 3767728SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle 3777728SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle 3788832SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle 3798832SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle 3808832SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle 3817404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle 3827404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle 3837404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle 3847404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3857404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3867404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3877404SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle 3887404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3897404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available 3907404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available 3917404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available 3927733SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available 3937748SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available 3948922Swilliam.wang@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available 3958922Swilliam.wang@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available 3967404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available 3977404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 3988733Sgeoffrey.blake@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available 3997404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available 4007404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available 4017439Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available 4027439Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available 4037404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available 4047404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available 4057404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available 4067404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available 4077437Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available 4087437Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available 4097404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available 4107404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available 4117437Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available 4127437Sdam.sunwoo@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available 4137404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available 4147728SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available 4157728SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available 4167728SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available 4177404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 4187728SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available 4197404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available 4207404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4217404SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4227404SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 4237404SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued 4247404SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued 4257404SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued 452system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued 453system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 456system.cpu.iq.FU_type_0::total 8280 # Type of FU issued 457system.cpu.iq.rate 0.195615 # Inst issue rate 458system.cpu.iq.fu_busy_cnt 197 # FU busy when requested 459system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) 460system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads 461system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes 462system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses 463system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 464system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 465system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 466system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses 467system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 468system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores 469system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 470system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed 471system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed 472system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 473system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed 474system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 475system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 476system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 477system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 478system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 479system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing 480system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking 481system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 482system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ 483system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch 484system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions 485system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions 486system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 487system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 488system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall 489system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 490system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 491system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly 492system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute 493system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions 494system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed 495system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute 496system.cpu.iew.exec_swp 0 # number of swp insts executed 497system.cpu.iew.exec_nop 1553 # number of nop insts executed 498system.cpu.iew.exec_refs 3252 # number of memory reference insts executed 499system.cpu.iew.exec_branches 1379 # Number of branches executed 500system.cpu.iew.exec_stores 1058 # Number of stores executed 501system.cpu.iew.exec_rate 0.187984 # Inst execution rate 502system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit 503system.cpu.iew.wb_count 7468 # cumulative count of insts written-back 504system.cpu.iew.wb_producers 2915 # num instructions producing a value 505system.cpu.iew.wb_consumers 4399 # num instructions consuming a value 506system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 507system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle 508system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back 509system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 510system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit 511system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 512system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted 513system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle 530system.cpu.commit.committedInsts 5623 # Number of instructions committed 531system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed 532system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 533system.cpu.commit.refs 2033 # Number of memory references committed 534system.cpu.commit.loads 1132 # Number of loads committed 535system.cpu.commit.membars 0 # Number of memory barriers committed 536system.cpu.commit.branches 883 # Number of branches committed 537system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 538system.cpu.commit.int_insts 4942 # Number of committed integer instructions. 539system.cpu.commit.function_calls 85 # Number of function calls committed. 540system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction 541system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction 542system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction 543system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction 544system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction 545system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction 546system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction 547system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction 548system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction 549system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 570system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 571system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 572system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 573system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 574system.cpu.commit.op_class_0::total 5623 # Class of committed instruction 575system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 576system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 577system.cpu.rob.rob_reads 23983 # The number of ROB reads 578system.cpu.rob.rob_writes 22065 # The number of ROB writes 579system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself 580system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling 581system.cpu.committedInsts 4986 # Number of Instructions Simulated 582system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated 583system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction 584system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads 585system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle 586system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads 587system.cpu.int_regfile_reads 10767 # number of integer regfile reads 588system.cpu.int_regfile_writes 5247 # number of integer regfile writes 589system.cpu.fp_regfile_reads 3 # number of floating regfile reads 590system.cpu.fp_regfile_writes 1 # number of floating regfile writes 591system.cpu.misc_regfile_reads 164 # number of misc regfile reads 592system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 596system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) 597system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 598system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) 599system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) 600system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 601system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) 602system.cpu.toL2Bus.snoops 0 # Total snoops (count) 603system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 612system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram 614system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 620system.cpu.icache.tags.replacements 17 # number of replacements 621system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use 622system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. 623system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. 624system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. 625system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor 627system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy 628system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy 629system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 631system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id 632system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id 633system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses 634system.cpu.icache.tags.data_accesses 4407 # Number of data accesses 635system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits 636system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits 637system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits 638system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits 639system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits 640system.cpu.icache.overall_hits::total 1593 # number of overall hits 641system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses 642system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses 643system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses 644system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses 645system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses 646system.cpu.icache.overall_misses::total 444 # number of overall misses 647system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles 648system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles 649system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles 650system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles 651system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles 652system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles 653system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses 656system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses 657system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses 658system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses 659system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses 661system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses 662system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses 663system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses 664system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency 666system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency 667system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 668system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency 671system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 672system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 674system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 675system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 676system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu.icache.fast_writes 0 # number of fast writes performed 678system.cpu.icache.cache_copies 0 # number of cache copies performed 679system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits 680system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits 681system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits 682system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits 683system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits 684system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits 685system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses 686system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses 687system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses 688system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses 689system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses 690system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses 691system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses 698system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses 699system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses 700system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency 709system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 710system.cpu.l2cache.tags.replacements 0 # number of replacements 711system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use 712system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. 715system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 722system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 724system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id 725system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses 726system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 727system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 728system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 729system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 730system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 731system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 732system.cpu.l2cache.overall_hits::total 3 # number of overall hits 733system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses 734system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 735system.cpu.l2cache.ReadReq_misses::total 421 # number of ReadReq misses 736system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 737system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 738system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses 739system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 740system.cpu.l2cache.demand_misses::total 471 # number of demand (read+write) misses 741system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses 742system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 743system.cpu.l2cache.overall_misses::total 471 # number of overall misses 744system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles 745system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles 746system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles 747system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles 748system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles 749system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles 750system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles 751system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles 752system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles 753system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles 754system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles 755system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) 756system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 757system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 758system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 760system.cpu.l2cache.demand_accesses::cpu.inst 333 # number of demand (read+write) accesses 761system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::total 474 # number of demand (read+write) accesses 763system.cpu.l2cache.overall_accesses::cpu.inst 333 # number of overall (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::total 474 # number of overall (read+write) accesses 766system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.990991 # miss rate for ReadReq accesses 767system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 768system.cpu.l2cache.ReadReq_miss_rate::total 0.992925 # miss rate for ReadReq accesses 769system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 771system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses 772system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 773system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses 774system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses 775system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 776system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses 777system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency 778system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency 779system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency 780system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency 781system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency 782system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 783system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 784system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency 785system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 786system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 787system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency 788system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 789system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 791system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 793system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 794system.cpu.l2cache.fast_writes 0 # number of fast writes performed 795system.cpu.l2cache.cache_copies 0 # number of cache copies performed 796system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses 797system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 798system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses 799system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 800system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 801system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses 802system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 803system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses 804system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses 805system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 806system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses 807system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles 809system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles 811system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles 818system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses 819system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 820system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses 821system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 822system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 823system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses 824system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 825system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses 826system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses 827system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 828system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses 829system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency 830system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency 831system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency 832system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency 833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 835system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 836system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 838system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 839system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency 840system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 841system.cpu.dcache.tags.replacements 0 # number of replacements 842system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use 843system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. 844system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 845system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. 846system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor 848system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy 849system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy 850system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 851system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 852system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id 853system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 854system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 855system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 856system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits 857system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits 858system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits 859system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits 860system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits 861system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits 862system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits 863system.cpu.dcache.overall_hits::total 2445 # number of overall hits 864system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses 865system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses 866system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses 867system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses 868system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses 869system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses 870system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses 871system.cpu.dcache.overall_misses::total 515 # number of overall misses 872system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles 873system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles 874system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles 875system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles 876system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles 877system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles 878system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles 879system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles 880system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) 881system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) 882system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 883system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 884system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses 885system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses 886system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses 887system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses 888system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses 889system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses 890system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses 891system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses 892system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses 893system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses 894system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses 895system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses 896system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency 897system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency 898system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency 899system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency 900system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 901system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency 902system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 903system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency 904system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 905system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 906system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 907system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 908system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 909system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 910system.cpu.dcache.fast_writes 0 # number of fast writes performed 911system.cpu.dcache.cache_copies 0 # number of cache copies performed 912system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 913system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 914system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits 915system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits 916system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 917system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 918system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 919system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 920system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 921system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 922system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 923system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 924system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 925system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 926system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 927system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 928system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles 929system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles 930system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles 931system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles 932system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles 933system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles 934system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles 935system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles 936system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses 937system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses 938system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 939system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 940system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses 941system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses 942system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses 943system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses 944system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency 945system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency 946system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency 947system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency 948system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 949system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency 950system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 951system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency 952system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 953 954---------- End Simulation Statistics ---------- 955