stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21611500 # Number of ticks simulated 5final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 87050 # Simulator instruction rate (inst/s) 8host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 364707967 # Simulator tick rate (ticks/s) 10host_mem_usage 288672 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30656 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 479 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 997987183 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 420516854 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1418504037 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 997987183 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 997987183 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 997987183 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 420516854 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1418504037 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 479 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 479 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30656 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30656 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 30 # Per bank write bursts 45system.physmem.perBankRdBursts::1 0 # Per bank write bursts 46system.physmem.perBankRdBursts::2 1 # Per bank write bursts 47system.physmem.perBankRdBursts::3 0 # Per bank write bursts 48system.physmem.perBankRdBursts::4 7 # Per bank write bursts 49system.physmem.perBankRdBursts::5 3 # Per bank write bursts 50system.physmem.perBankRdBursts::6 13 # Per bank write bursts 51system.physmem.perBankRdBursts::7 54 # Per bank write bursts 52system.physmem.perBankRdBursts::8 64 # Per bank write bursts 53system.physmem.perBankRdBursts::9 77 # Per bank write bursts 54system.physmem.perBankRdBursts::10 43 # Per bank write bursts 55system.physmem.perBankRdBursts::11 20 # Per bank write bursts 56system.physmem.perBankRdBursts::12 51 # Per bank write bursts 57system.physmem.perBankRdBursts::13 29 # Per bank write bursts 58system.physmem.perBankRdBursts::14 80 # Per bank write bursts 59system.physmem.perBankRdBursts::15 7 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 21538500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 479 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 255.412844 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 174.780194 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 251.892291 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 32 29.36% 29.36% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation 202system.physmem.totQLat 5601000 # Total ticks spent queuing 203system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 11.08 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 360 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 44965.55 # Average gap between requests 223system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 229system.membus.trans_dist::ReadReq 428 # Transaction distribution 230system.membus.trans_dist::ReadResp 428 # Transaction distribution 231system.membus.trans_dist::ReadExReq 51 # Transaction distribution 232system.membus.trans_dist::ReadExResp 51 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) 235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) 236system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) 237system.membus.snoops 0 # Total snoops (count) 238system.membus.snoop_fanout::samples 479 # Request fanout histogram 239system.membus.snoop_fanout::mean 0 # Request fanout histogram 240system.membus.snoop_fanout::stdev 0 # Request fanout histogram 241system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 242system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram 243system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::min_value 0 # Request fanout histogram 246system.membus.snoop_fanout::max_value 0 # Request fanout histogram 247system.membus.snoop_fanout::total 479 # Request fanout histogram 248system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 249system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 250system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) 251system.membus.respLayer1.utilization 20.8 # Layer utilization (%) 252system.cpu_clk_domain.clock 500 # Clock period in ticks 253system.cpu.branchPred.lookups 2196 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 564 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 33.176471 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 277 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 69 # Number of incorrect RAS predictions. 262system.cpu.dtb.read_hits 0 # DTB read hits 263system.cpu.dtb.read_misses 0 # DTB read misses 264system.cpu.dtb.read_accesses 0 # DTB read accesses 265system.cpu.dtb.write_hits 0 # DTB write hits 266system.cpu.dtb.write_misses 0 # DTB write misses 267system.cpu.dtb.write_accesses 0 # DTB write accesses 268system.cpu.dtb.hits 0 # DTB hits 269system.cpu.dtb.misses 0 # DTB misses 270system.cpu.dtb.accesses 0 # DTB accesses 271system.cpu.itb.read_hits 0 # DTB read hits 272system.cpu.itb.read_misses 0 # DTB read misses 273system.cpu.itb.read_accesses 0 # DTB read accesses 274system.cpu.itb.write_hits 0 # DTB write hits 275system.cpu.itb.write_misses 0 # DTB write misses 276system.cpu.itb.write_accesses 0 # DTB write accesses 277system.cpu.itb.hits 0 # DTB hits 278system.cpu.itb.misses 0 # DTB misses 279system.cpu.itb.accesses 0 # DTB accesses 280system.cpu.workload.num_syscalls 8 # Number of system calls 281system.cpu.numCycles 43224 # number of cpu cycles simulated 282system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 284system.cpu.fetch.icacheStallCycles 9138 # Number of cycles fetch is stalled on an Icache miss 285system.cpu.fetch.Insts 13312 # Number of instructions fetch has processed 286system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered 287system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 288system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked 289system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing 290system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps 291system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched 292system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed 293system.cpu.fetch.rateDist::samples 14703 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::mean 0.905393 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::stdev 2.198604 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::0 11282 76.73% 76.73% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::1 1513 10.29% 87.02% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::2 130 0.88% 87.91% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::3 159 1.08% 88.99% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::4 291 1.98% 90.97% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::5 99 0.67% 91.64% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::6 152 1.03% 92.67% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::7 125 0.85% 93.53% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::8 952 6.47% 100.00% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::total 14703 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.branchRate 0.050805 # Number of branch fetches per cycle 311system.cpu.fetch.rate 0.307977 # Number of inst fetches per cycle 312system.cpu.decode.IdleCycles 8679 # Number of cycles decode is idle 313system.cpu.decode.BlockedCycles 2634 # Number of cycles decode is blocked 314system.cpu.decode.RunCycles 2860 # Number of cycles decode is running 315system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking 316system.cpu.decode.SquashCycles 400 # Number of cycles decode is squashing 317system.cpu.decode.BranchResolved 179 # Number of times decode resolved a branch 318system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction 319system.cpu.decode.DecodedInsts 12297 # Number of instructions handled by decode 320system.cpu.decode.SquashedInsts 180 # Number of squashed instructions handled by decode 321system.cpu.rename.SquashCycles 400 # Number of cycles rename is squashing 322system.cpu.rename.IdleCycles 8850 # Number of cycles rename is idle 323system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking 324system.cpu.rename.serializeStallCycles 975 # count of cycles rename stalled for serializing inst 325system.cpu.rename.RunCycles 2807 # Number of cycles rename is running 326system.cpu.rename.UnblockCycles 1169 # Number of cycles rename is unblocking 327system.cpu.rename.RenamedInsts 11801 # Number of instructions processed by rename 328system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 329system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 330system.cpu.rename.LQFullEvents 281 # Number of times rename has blocked due to LQ full 331system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full 332system.cpu.rename.RenamedOperands 7107 # Number of destination operands rename has renamed 333system.cpu.rename.RenameLookups 13927 # Number of register rename lookups that rename has made 334system.cpu.rename.int_rename_lookups 13678 # Number of integer rename lookups 335system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 336system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed 337system.cpu.rename.UndoneMaps 3709 # Number of HB maps that are undone due to squashing 338system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 339system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 340system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer 341system.cpu.memDep0.insertedLoads 2543 # Number of loads inserted to the mem dependence unit. 342system.cpu.memDep0.insertedStores 1213 # Number of stores inserted to the mem dependence unit. 343system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 344system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 345system.cpu.iq.iqInstsAdded 9299 # Number of instructions added to the IQ (excludes non-spec) 346system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 347system.cpu.iq.iqInstsIssued 8548 # Number of instructions issued 348system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued 349system.cpu.iq.iqSquashedInstsExamined 3486 # Number of squashed instructions iterated over during squash; mainly for profiling 350system.cpu.iq.iqSquashedOperandsExamined 1874 # Number of squashed operands that are examined and possibly removed from graph 351system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 352system.cpu.iq.issued_per_cycle::samples 14703 # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::mean 0.581378 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::stdev 1.331585 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::0 11282 76.73% 76.73% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::1 1346 9.15% 85.89% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::2 761 5.18% 91.06% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::3 427 2.90% 93.97% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::4 364 2.48% 96.44% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::5 316 2.15% 98.59% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::6 114 0.78% 99.37% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::7 65 0.44% 99.81% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::total 14703 # Number of insts issued each cycle 369system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 370system.cpu.iq.fu_full::IntAlu 8 3.96% 3.96% # attempts to use FU when none available 371system.cpu.iq.fu_full::IntMult 0 0.00% 3.96% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntDiv 0 0.00% 3.96% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.96% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.96% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.96% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatMult 0 0.00% 3.96% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.96% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.96% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.96% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.96% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.96% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.96% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.96% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.96% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMult 0 0.00% 3.96% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.96% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdShift 0 0.00% 3.96% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.96% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.96% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.96% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.96% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.96% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.96% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.96% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.96% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.96% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.96% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.96% # attempts to use FU when none available 399system.cpu.iq.fu_full::MemRead 135 66.83% 70.79% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemWrite 59 29.21% 100.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 404system.cpu.iq.FU_type_0::IntAlu 5034 58.89% 58.89% # Type of FU issued 405system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.95% # Type of FU issued 406system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued 433system.cpu.iq.FU_type_0::MemRead 2396 28.03% 87.03% # Type of FU issued 434system.cpu.iq.FU_type_0::MemWrite 1109 12.97% 100.00% # Type of FU issued 435system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 436system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::total 8548 # Type of FU issued 438system.cpu.iq.rate 0.197761 # Inst issue rate 439system.cpu.iq.fu_busy_cnt 202 # FU busy when requested 440system.cpu.iq.fu_busy_rate 0.023631 # FU busy rate (busy events/executed inst) 441system.cpu.iq.int_inst_queue_reads 32026 # Number of integer instruction queue reads 442system.cpu.iq.int_inst_queue_writes 12803 # Number of integer instruction queue writes 443system.cpu.iq.int_inst_queue_wakeup_accesses 7708 # Number of integer instruction queue wakeup accesses 444system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 445system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 446system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 447system.cpu.iq.int_alu_accesses 8748 # Number of integer alu accesses 448system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 449system.cpu.iew.lsq.thread0.forwLoads 86 # Number of loads that had data forwarded from stores 450system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 451system.cpu.iew.lsq.thread0.squashedLoads 1380 # Number of loads squashed 452system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 453system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations 454system.cpu.iew.lsq.thread0.squashedStores 288 # Number of stores squashed 455system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 456system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 457system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 458system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 459system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 460system.cpu.iew.iewSquashCycles 400 # Number of cycles IEW is squashing 461system.cpu.iew.iewBlockCycles 479 # Number of cycles IEW is blocking 462system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 463system.cpu.iew.iewDispatchedInsts 10879 # Number of instructions dispatched to IQ 464system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch 465system.cpu.iew.iewDispLoadInsts 2543 # Number of dispatched load instructions 466system.cpu.iew.iewDispStoreInsts 1213 # Number of dispatched store instructions 467system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 468system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 469system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 470system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 471system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly 472system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly 473system.cpu.iew.branchMispredicts 464 # Number of branch mispredicts detected at execute 474system.cpu.iew.iewExecutedInsts 8213 # Number of executed instructions 475system.cpu.iew.iewExecLoadInsts 2257 # Number of load instructions executed 476system.cpu.iew.iewExecSquashedInsts 335 # Number of squashed instructions skipped in execute 477system.cpu.iew.exec_swp 0 # number of swp insts executed 478system.cpu.iew.exec_nop 1568 # number of nop insts executed 479system.cpu.iew.exec_refs 3348 # number of memory reference insts executed 480system.cpu.iew.exec_branches 1425 # Number of branches executed 481system.cpu.iew.exec_stores 1091 # Number of stores executed 482system.cpu.iew.exec_rate 0.190010 # Inst execution rate 483system.cpu.iew.wb_sent 7817 # cumulative count of insts sent to commit 484system.cpu.iew.wb_count 7710 # cumulative count of insts written-back 485system.cpu.iew.wb_producers 2989 # num instructions producing a value 486system.cpu.iew.wb_consumers 4523 # num instructions consuming a value 487system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 488system.cpu.iew.wb_rate 0.178373 # insts written-back per cycle 489system.cpu.iew.wb_fanout 0.660845 # average fanout of values written-back 490system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 491system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit 492system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 493system.cpu.commit.branchMispredicts 392 # The number of times a branch was mispredicted 494system.cpu.commit.committed_per_cycle::samples 13824 # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::mean 0.420501 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::stdev 1.238844 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::0 11590 83.84% 83.84% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::1 886 6.41% 90.25% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::2 537 3.88% 94.13% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::3 260 1.88% 96.01% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::4 148 1.07% 97.08% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::5 189 1.37% 98.45% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::6 68 0.49% 98.94% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::7 40 0.29% 99.23% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::8 106 0.77% 100.00% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::total 13824 # Number of insts commited each cycle 511system.cpu.commit.committedInsts 5813 # Number of instructions committed 512system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 513system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 514system.cpu.commit.refs 2088 # Number of memory references committed 515system.cpu.commit.loads 1163 # Number of loads committed 516system.cpu.commit.membars 0 # Number of memory barriers committed 517system.cpu.commit.branches 915 # Number of branches committed 518system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 519system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 520system.cpu.commit.function_calls 87 # Number of function calls committed. 521system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction 522system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction 523system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction 524system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction 525system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction 526system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction 551system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction 552system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction 553system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::total 5813 # Class of committed instruction 556system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 557system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 558system.cpu.rob.rob_reads 24581 # The number of ROB reads 559system.cpu.rob.rob_writes 22642 # The number of ROB writes 560system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself 561system.cpu.idleCycles 28521 # Total number of cycles that the CPU has spent unscheduled due to idling 562system.cpu.committedInsts 5156 # Number of Instructions Simulated 563system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 564system.cpu.cpi 8.383243 # CPI: Cycles Per Instruction 565system.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads 566system.cpu.ipc 0.119286 # IPC: Instructions Per Cycle 567system.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads 568system.cpu.int_regfile_reads 11114 # number of integer regfile reads 569system.cpu.int_regfile_writes 5412 # number of integer regfile writes 570system.cpu.fp_regfile_reads 3 # number of floating regfile reads 571system.cpu.fp_regfile_writes 1 # number of floating regfile writes 572system.cpu.misc_regfile_reads 164 # number of misc regfile reads 573system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.snoops 0 # Total snoops (count) 584system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 595system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 596system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 597system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) 598system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 599system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 600system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 601system.cpu.icache.tags.replacements 17 # number of replacements 602system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 613system.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id 614system.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 4476 # Number of data accesses 616system.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits 617system.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits 618system.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits 619system.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits 620system.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits 621system.cpu.icache.overall_hits::total 1615 # number of overall hits 622system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses 623system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses 624system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses 625system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses 626system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses 627system.cpu.icache.overall_misses::total 453 # number of overall misses 628system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles 629system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles 630system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles 631system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles 632system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles 633system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles 634system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 635system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 637system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 638system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 639system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 640system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses 642system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses 643system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses 644system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses 645system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses 646system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency 647system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency 648system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 649system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency 652system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 653system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 655system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked 657system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.icache.fast_writes 0 # number of fast writes performed 659system.cpu.icache.cache_copies 0 # number of cache copies performed 660system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits 661system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits 662system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits 663system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits 664system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 665system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 666system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses 667system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses 668system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses 669system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses 670system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses 671system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses 672system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles 673system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles 674system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles 678system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses 680system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses 681system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses 682system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses 683system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency 690system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 691system.cpu.l2cache.tags.replacements 0 # number of replacements 692system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use 693system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 694system.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. 695system.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. 696system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 697system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 428 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013062 # Percentage of cache occupancy per task id 706system.cpu.l2cache.tags.tag_accesses 4335 # Number of tag accesses 707system.cpu.l2cache.tags.data_accesses 4335 # Number of data accesses 708system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 709system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 710system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 711system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 712system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 713system.cpu.l2cache.overall_hits::total 3 # number of overall hits 714system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses 715system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 716system.cpu.l2cache.ReadReq_misses::total 428 # number of ReadReq misses 717system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 718system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 719system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses 720system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::total 479 # number of demand (read+write) misses 722system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses 723system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 724system.cpu.l2cache.overall_misses::total 479 # number of overall misses 725system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles 726system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles 727system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles 728system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles 729system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles 730system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles 731system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles 732system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles 733system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles 734system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles 735system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles 736system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) 737system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 738system.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) 739system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses 742system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses 744system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses 745system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 746system.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses 747system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991176 # miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 749system.cpu.l2cache.ReadReq_miss_rate::total 0.993039 # miss rate for ReadReq accesses 750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991176 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::total 0.993776 # miss rate for demand accesses 755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses 758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency 761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency 763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency 769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.l2cache.fast_writes 0 # number of fast writes performed 776system.cpu.l2cache.cache_copies 0 # number of cache copies performed 777system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 778system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 779system.cpu.l2cache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 780system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 781system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 782system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 783system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.demand_mshr_misses::total 479 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 786system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 787system.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses 788system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles 789system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles 791system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles 792system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles 793system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles 794system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles 795system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles 796system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles 797system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles 798system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles 799system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 801system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses 802system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 803system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 806system.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 # mshr miss rate for demand accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 809system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses 810system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency 811system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency 812system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency 813system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency 821system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 822system.cpu.dcache.tags.replacements 0 # number of replacements 823system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use 824system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. 825system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 826system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. 827system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 828system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor 829system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy 830system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy 831system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 832system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 833system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 834system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 835system.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses 836system.cpu.dcache.tags.data_accesses 6220 # Number of data accesses 837system.cpu.dcache.ReadReq_hits::cpu.data 1945 # number of ReadReq hits 838system.cpu.dcache.ReadReq_hits::total 1945 # number of ReadReq hits 839system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 840system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 841system.cpu.dcache.demand_hits::cpu.data 2508 # number of demand (read+write) hits 842system.cpu.dcache.demand_hits::total 2508 # number of demand (read+write) hits 843system.cpu.dcache.overall_hits::cpu.data 2508 # number of overall hits 844system.cpu.dcache.overall_hits::total 2508 # number of overall hits 845system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 846system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 847system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 848system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 849system.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses 850system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses 851system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses 852system.cpu.dcache.overall_misses::total 531 # number of overall misses 853system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles 854system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles 855system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles 857system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles 858system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles 859system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles 860system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles 861system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) 862system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses 866system.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses 867system.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses 868system.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses 869system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses 870system.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses 871system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 872system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 873system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses 874system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses 875system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses 876system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses 877system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency 878system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency 879system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency 881system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 882system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency 883system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency 885system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 886system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 888system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 890system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 891system.cpu.dcache.fast_writes 0 # number of fast writes performed 892system.cpu.dcache.cache_copies 0 # number of cache copies performed 893system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits 894system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 895system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 896system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 897system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits 898system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits 899system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits 900system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits 901system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 902system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 903system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 905system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 906system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 907system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 908system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses 909system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles 910system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles 917system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses 918system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses 922system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses 923system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses 924system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses 925system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency 927system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency 929system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency 931system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency 933system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 934 935---------- End Simulation Statistics ---------- 936