config.ini revision 10242:cb4e86c17767
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dtb=system.cpu.dtb 72eventq_index=0 73fetchBufferSize=64 74fetchToDecodeDelay=1 75fetchTrapLatency=1 76fetchWidth=8 77forwardComSize=5 78fuPool=system.cpu.fuPool 79function_trace=false 80function_trace_start=0 81iewToCommitDelay=1 82iewToDecodeDelay=1 83iewToFetchDelay=1 84iewToRenameDelay=1 85interrupts=system.cpu.interrupts 86isa=system.cpu.isa 87issueToExecuteDelay=1 88issueWidth=8 89itb=system.cpu.itb 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysCCRegs=0 97numPhysFloatRegs=256 98numPhysIntRegs=256 99numROBEntries=192 100numRobs=1 101numThreads=1 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109simpoint_start_insts= 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 119socket_id=0 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload=system.cpu.workload 129dcache_port=system.cpu.dcache.cpu_side 130icache_port=system.cpu.icache.cpu_side 131 132[system.cpu.branchPred] 133type=BranchPredictor 134BTBEntries=4096 135BTBTagSize=16 136RASSize=16 137choiceCtrBits=2 138choicePredictorSize=8192 139eventq_index=0 140globalCtrBits=2 141globalPredictorSize=8192 142instShiftAmt=2 143localCtrBits=2 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu.dcache] 150type=BaseCache 151children=tags 152addr_ranges=0:18446744073709551615 153assoc=2 154clk_domain=system.cpu_clk_domain 155eventq_index=0 156forward_snoops=true 157hit_latency=2 158is_top_level=true 159max_miss_count=0 160mshrs=4 161prefetch_on_access=false 162prefetcher=Null 163response_latency=2 164sequential_access=false 165size=262144 166system=system 167tags=system.cpu.dcache.tags 168tgts_per_mshr=20 169two_queue=false 170write_buffers=8 171cpu_side=system.cpu.dcache_port 172mem_side=system.cpu.toL2Bus.slave[1] 173 174[system.cpu.dcache.tags] 175type=LRU 176assoc=2 177block_size=64 178clk_domain=system.cpu_clk_domain 179eventq_index=0 180hit_latency=2 181sequential_access=false 182size=262144 183 184[system.cpu.dtb] 185type=MipsTLB 186eventq_index=0 187size=64 188 189[system.cpu.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 193eventq_index=0 194 195[system.cpu.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 199eventq_index=0 200opList=system.cpu.fuPool.FUList0.opList 201 202[system.cpu.fuPool.FUList0.opList] 203type=OpDesc 204eventq_index=0 205issueLat=1 206opClass=IntAlu 207opLat=1 208 209[system.cpu.fuPool.FUList1] 210type=FUDesc 211children=opList0 opList1 212count=2 213eventq_index=0 214opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 215 216[system.cpu.fuPool.FUList1.opList0] 217type=OpDesc 218eventq_index=0 219issueLat=1 220opClass=IntMult 221opLat=3 222 223[system.cpu.fuPool.FUList1.opList1] 224type=OpDesc 225eventq_index=0 226issueLat=19 227opClass=IntDiv 228opLat=20 229 230[system.cpu.fuPool.FUList2] 231type=FUDesc 232children=opList0 opList1 opList2 233count=4 234eventq_index=0 235opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 236 237[system.cpu.fuPool.FUList2.opList0] 238type=OpDesc 239eventq_index=0 240issueLat=1 241opClass=FloatAdd 242opLat=2 243 244[system.cpu.fuPool.FUList2.opList1] 245type=OpDesc 246eventq_index=0 247issueLat=1 248opClass=FloatCmp 249opLat=2 250 251[system.cpu.fuPool.FUList2.opList2] 252type=OpDesc 253eventq_index=0 254issueLat=1 255opClass=FloatCvt 256opLat=2 257 258[system.cpu.fuPool.FUList3] 259type=FUDesc 260children=opList0 opList1 opList2 261count=2 262eventq_index=0 263opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 264 265[system.cpu.fuPool.FUList3.opList0] 266type=OpDesc 267eventq_index=0 268issueLat=1 269opClass=FloatMult 270opLat=4 271 272[system.cpu.fuPool.FUList3.opList1] 273type=OpDesc 274eventq_index=0 275issueLat=12 276opClass=FloatDiv 277opLat=12 278 279[system.cpu.fuPool.FUList3.opList2] 280type=OpDesc 281eventq_index=0 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290eventq_index=0 291opList=system.cpu.fuPool.FUList4.opList 292 293[system.cpu.fuPool.FUList4.opList] 294type=OpDesc 295eventq_index=0 296issueLat=1 297opClass=MemRead 298opLat=1 299 300[system.cpu.fuPool.FUList5] 301type=FUDesc 302children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 303count=4 304eventq_index=0 305opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 306 307[system.cpu.fuPool.FUList5.opList00] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList01] 315type=OpDesc 316eventq_index=0 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList02] 322type=OpDesc 323eventq_index=0 324issueLat=1 325opClass=SimdAlu 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList03] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=SimdCmp 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList04] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=SimdCvt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList05] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=SimdMisc 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList06] 350type=OpDesc 351eventq_index=0 352issueLat=1 353opClass=SimdMult 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList07] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=SimdMultAcc 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList08] 364type=OpDesc 365eventq_index=0 366issueLat=1 367opClass=SimdShift 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList09] 371type=OpDesc 372eventq_index=0 373issueLat=1 374opClass=SimdShiftAcc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList10] 378type=OpDesc 379eventq_index=0 380issueLat=1 381opClass=SimdSqrt 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList11] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=SimdFloatAdd 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList12] 392type=OpDesc 393eventq_index=0 394issueLat=1 395opClass=SimdFloatAlu 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList13] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdFloatCmp 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList14] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdFloatCvt 410opLat=1 411 412[system.cpu.fuPool.FUList5.opList15] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdFloatDiv 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList16] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdFloatMisc 424opLat=1 425 426[system.cpu.fuPool.FUList5.opList17] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList18] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList19] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdFloatSqrt 445opLat=1 446 447[system.cpu.fuPool.FUList6] 448type=FUDesc 449children=opList 450count=0 451eventq_index=0 452opList=system.cpu.fuPool.FUList6.opList 453 454[system.cpu.fuPool.FUList6.opList] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=MemWrite 459opLat=1 460 461[system.cpu.fuPool.FUList7] 462type=FUDesc 463children=opList0 opList1 464count=4 465eventq_index=0 466opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 467 468[system.cpu.fuPool.FUList7.opList0] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=MemRead 473opLat=1 474 475[system.cpu.fuPool.FUList7.opList1] 476type=OpDesc 477eventq_index=0 478issueLat=1 479opClass=MemWrite 480opLat=1 481 482[system.cpu.fuPool.FUList8] 483type=FUDesc 484children=opList 485count=1 486eventq_index=0 487opList=system.cpu.fuPool.FUList8.opList 488 489[system.cpu.fuPool.FUList8.opList] 490type=OpDesc 491eventq_index=0 492issueLat=3 493opClass=IprAccess 494opLat=3 495 496[system.cpu.icache] 497type=BaseCache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=2 501clk_domain=system.cpu_clk_domain 502eventq_index=0 503forward_snoops=true 504hit_latency=2 505is_top_level=true 506max_miss_count=0 507mshrs=4 508prefetch_on_access=false 509prefetcher=Null 510response_latency=2 511sequential_access=false 512size=131072 513system=system 514tags=system.cpu.icache.tags 515tgts_per_mshr=20 516two_queue=false 517write_buffers=8 518cpu_side=system.cpu.icache_port 519mem_side=system.cpu.toL2Bus.slave[0] 520 521[system.cpu.icache.tags] 522type=LRU 523assoc=2 524block_size=64 525clk_domain=system.cpu_clk_domain 526eventq_index=0 527hit_latency=2 528sequential_access=false 529size=131072 530 531[system.cpu.interrupts] 532type=MipsInterrupts 533eventq_index=0 534 535[system.cpu.isa] 536type=MipsISA 537eventq_index=0 538num_threads=1 539num_vpes=1 540system=system 541 542[system.cpu.itb] 543type=MipsTLB 544eventq_index=0 545size=64 546 547[system.cpu.l2cache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=8 552clk_domain=system.cpu_clk_domain 553eventq_index=0 554forward_snoops=true 555hit_latency=20 556is_top_level=false 557max_miss_count=0 558mshrs=20 559prefetch_on_access=false 560prefetcher=Null 561response_latency=20 562sequential_access=false 563size=2097152 564system=system 565tags=system.cpu.l2cache.tags 566tgts_per_mshr=12 567two_queue=false 568write_buffers=8 569cpu_side=system.cpu.toL2Bus.master[0] 570mem_side=system.membus.slave[1] 571 572[system.cpu.l2cache.tags] 573type=LRU 574assoc=8 575block_size=64 576clk_domain=system.cpu_clk_domain 577eventq_index=0 578hit_latency=20 579sequential_access=false 580size=2097152 581 582[system.cpu.toL2Bus] 583type=CoherentBus 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586header_cycles=1 587system=system 588use_default_range=false 589width=32 590master=system.cpu.l2cache.cpu_side 591slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 592 593[system.cpu.tracer] 594type=ExeTracer 595eventq_index=0 596 597[system.cpu.workload] 598type=LiveProcess 599cmd=hello 600cwd= 601egid=100 602env= 603errout=cerr 604euid=100 605eventq_index=0 606executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello 607gid=100 608input=cin 609max_stack_size=67108864 610output=cout 611pid=100 612ppid=99 613simpoint=0 614system=system 615uid=100 616 617[system.cpu_clk_domain] 618type=SrcClockDomain 619clock=500 620eventq_index=0 621voltage_domain=system.voltage_domain 622 623[system.membus] 624type=CoherentBus 625clk_domain=system.clk_domain 626eventq_index=0 627header_cycles=1 628system=system 629use_default_range=false 630width=8 631master=system.physmem.port 632slave=system.system_port system.cpu.l2cache.mem_side 633 634[system.physmem] 635type=DRAMCtrl 636activation_limit=4 637addr_mapping=RoRaBaChCo 638banks_per_rank=8 639burst_length=8 640channels=1 641clk_domain=system.clk_domain 642conf_table_reported=true 643device_bus_width=8 644device_rowbuffer_size=1024 645devices_per_rank=8 646eventq_index=0 647in_addr_map=true 648max_accesses_per_row=16 649mem_sched_policy=frfcfs 650min_writes_per_switch=16 651null=false 652page_policy=open_adaptive 653range=0:134217727 654ranks_per_channel=2 655read_buffer_size=32 656static_backend_latency=10000 657static_frontend_latency=10000 658tBURST=5000 659tCK=1250 660tCL=13750 661tRAS=35000 662tRCD=13750 663tREFI=7800000 664tRFC=260000 665tRP=13750 666tRRD=6000 667tRTP=7500 668tRTW=2500 669tWR=15000 670tWTR=7500 671tXAW=30000 672write_buffer_size=64 673write_high_thresh_perc=85 674write_low_thresh_perc=50 675port=system.membus.master[0] 676 677[system.voltage_domain] 678type=VoltageDomain 679eventq_index=0 680voltage=1.000000 681 682