config.ini revision 11570:4aac82f10951
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dstage2_mmu=system.cpu.dstage2_mmu 68dtb=system.cpu.dtb 69eventq_index=0 70function_trace=false 71function_trace_start=0 72interrupts=system.cpu.interrupts 73isa=system.cpu.isa 74istage2_mmu=system.cpu.istage2_mmu 75itb=system.cpu.itb 76max_insts_all_threads=0 77max_insts_any_thread=0 78max_loads_all_threads=0 79max_loads_any_thread=0 80numThreads=1 81p_state_clk_gate_bins=20 82p_state_clk_gate_max=1000000000000 83p_state_clk_gate_min=1000 84power_model=Null 85profile=0 86progress_interval=0 87simpoint_start_insts= 88socket_id=0 89switched_out=false 90system=system 91tracer=system.cpu.tracer 92workload=system.cpu.workload 93dcache_port=system.cpu.dcache.cpu_side 94icache_port=system.cpu.icache.cpu_side 95 96[system.cpu.dcache] 97type=Cache 98children=tags 99addr_ranges=0:18446744073709551615 100assoc=2 101clk_domain=system.cpu_clk_domain 102clusivity=mostly_incl 103default_p_state=UNDEFINED 104demand_mshr_reserve=1 105eventq_index=0 106hit_latency=2 107is_read_only=false 108max_miss_count=0 109mshrs=4 110p_state_clk_gate_bins=20 111p_state_clk_gate_max=1000000000000 112p_state_clk_gate_min=1000 113power_model=Null 114prefetch_on_access=false 115prefetcher=Null 116response_latency=2 117sequential_access=false 118size=262144 119system=system 120tags=system.cpu.dcache.tags 121tgts_per_mshr=20 122write_buffers=8 123writeback_clean=false 124cpu_side=system.cpu.dcache_port 125mem_side=system.cpu.toL2Bus.slave[1] 126 127[system.cpu.dcache.tags] 128type=LRU 129assoc=2 130block_size=64 131clk_domain=system.cpu_clk_domain 132default_p_state=UNDEFINED 133eventq_index=0 134hit_latency=2 135p_state_clk_gate_bins=20 136p_state_clk_gate_max=1000000000000 137p_state_clk_gate_min=1000 138power_model=Null 139sequential_access=false 140size=262144 141 142[system.cpu.dstage2_mmu] 143type=ArmStage2MMU 144children=stage2_tlb 145eventq_index=0 146stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 147sys=system 148tlb=system.cpu.dtb 149 150[system.cpu.dstage2_mmu.stage2_tlb] 151type=ArmTLB 152children=walker 153eventq_index=0 154is_stage2=true 155size=32 156walker=system.cpu.dstage2_mmu.stage2_tlb.walker 157 158[system.cpu.dstage2_mmu.stage2_tlb.walker] 159type=ArmTableWalker 160clk_domain=system.cpu_clk_domain 161default_p_state=UNDEFINED 162eventq_index=0 163is_stage2=true 164num_squash_per_cycle=2 165p_state_clk_gate_bins=20 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null 169sys=system 170 171[system.cpu.dtb] 172type=ArmTLB 173children=walker 174eventq_index=0 175is_stage2=false 176size=64 177walker=system.cpu.dtb.walker 178 179[system.cpu.dtb.walker] 180type=ArmTableWalker 181clk_domain=system.cpu_clk_domain 182default_p_state=UNDEFINED 183eventq_index=0 184is_stage2=false 185num_squash_per_cycle=2 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null 190sys=system 191port=system.cpu.toL2Bus.slave[3] 192 193[system.cpu.icache] 194type=Cache 195children=tags 196addr_ranges=0:18446744073709551615 197assoc=2 198clk_domain=system.cpu_clk_domain 199clusivity=mostly_incl 200default_p_state=UNDEFINED 201demand_mshr_reserve=1 202eventq_index=0 203hit_latency=2 204is_read_only=true 205max_miss_count=0 206mshrs=4 207p_state_clk_gate_bins=20 208p_state_clk_gate_max=1000000000000 209p_state_clk_gate_min=1000 210power_model=Null 211prefetch_on_access=false 212prefetcher=Null 213response_latency=2 214sequential_access=false 215size=131072 216system=system 217tags=system.cpu.icache.tags 218tgts_per_mshr=20 219write_buffers=8 220writeback_clean=true 221cpu_side=system.cpu.icache_port 222mem_side=system.cpu.toL2Bus.slave[0] 223 224[system.cpu.icache.tags] 225type=LRU 226assoc=2 227block_size=64 228clk_domain=system.cpu_clk_domain 229default_p_state=UNDEFINED 230eventq_index=0 231hit_latency=2 232p_state_clk_gate_bins=20 233p_state_clk_gate_max=1000000000000 234p_state_clk_gate_min=1000 235power_model=Null 236sequential_access=false 237size=131072 238 239[system.cpu.interrupts] 240type=ArmInterrupts 241eventq_index=0 242 243[system.cpu.isa] 244type=ArmISA 245decoderFlavour=Generic 246eventq_index=0 247fpsid=1090793632 248id_aa64afr0_el1=0 249id_aa64afr1_el1=0 250id_aa64dfr0_el1=1052678 251id_aa64dfr1_el1=0 252id_aa64isar0_el1=0 253id_aa64isar1_el1=0 254id_aa64mmfr0_el1=15728642 255id_aa64mmfr1_el1=0 256id_aa64pfr0_el1=17 257id_aa64pfr1_el1=0 258id_isar0=34607377 259id_isar1=34677009 260id_isar2=555950401 261id_isar3=17899825 262id_isar4=268501314 263id_isar5=0 264id_mmfr0=270536963 265id_mmfr1=0 266id_mmfr2=19070976 267id_mmfr3=34611729 268id_pfr0=49 269id_pfr1=4113 270midr=1091551472 271pmu=Null 272system=system 273 274[system.cpu.istage2_mmu] 275type=ArmStage2MMU 276children=stage2_tlb 277eventq_index=0 278stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 279sys=system 280tlb=system.cpu.itb 281 282[system.cpu.istage2_mmu.stage2_tlb] 283type=ArmTLB 284children=walker 285eventq_index=0 286is_stage2=true 287size=32 288walker=system.cpu.istage2_mmu.stage2_tlb.walker 289 290[system.cpu.istage2_mmu.stage2_tlb.walker] 291type=ArmTableWalker 292clk_domain=system.cpu_clk_domain 293default_p_state=UNDEFINED 294eventq_index=0 295is_stage2=true 296num_squash_per_cycle=2 297p_state_clk_gate_bins=20 298p_state_clk_gate_max=1000000000000 299p_state_clk_gate_min=1000 300power_model=Null 301sys=system 302 303[system.cpu.itb] 304type=ArmTLB 305children=walker 306eventq_index=0 307is_stage2=false 308size=64 309walker=system.cpu.itb.walker 310 311[system.cpu.itb.walker] 312type=ArmTableWalker 313clk_domain=system.cpu_clk_domain 314default_p_state=UNDEFINED 315eventq_index=0 316is_stage2=false 317num_squash_per_cycle=2 318p_state_clk_gate_bins=20 319p_state_clk_gate_max=1000000000000 320p_state_clk_gate_min=1000 321power_model=Null 322sys=system 323port=system.cpu.toL2Bus.slave[2] 324 325[system.cpu.l2cache] 326type=Cache 327children=tags 328addr_ranges=0:18446744073709551615 329assoc=8 330clk_domain=system.cpu_clk_domain 331clusivity=mostly_incl 332default_p_state=UNDEFINED 333demand_mshr_reserve=1 334eventq_index=0 335hit_latency=20 336is_read_only=false 337max_miss_count=0 338mshrs=20 339p_state_clk_gate_bins=20 340p_state_clk_gate_max=1000000000000 341p_state_clk_gate_min=1000 342power_model=Null 343prefetch_on_access=false 344prefetcher=Null 345response_latency=20 346sequential_access=false 347size=2097152 348system=system 349tags=system.cpu.l2cache.tags 350tgts_per_mshr=12 351write_buffers=8 352writeback_clean=false 353cpu_side=system.cpu.toL2Bus.master[0] 354mem_side=system.membus.slave[1] 355 356[system.cpu.l2cache.tags] 357type=LRU 358assoc=8 359block_size=64 360clk_domain=system.cpu_clk_domain 361default_p_state=UNDEFINED 362eventq_index=0 363hit_latency=20 364p_state_clk_gate_bins=20 365p_state_clk_gate_max=1000000000000 366p_state_clk_gate_min=1000 367power_model=Null 368sequential_access=false 369size=2097152 370 371[system.cpu.toL2Bus] 372type=CoherentXBar 373children=snoop_filter 374clk_domain=system.cpu_clk_domain 375default_p_state=UNDEFINED 376eventq_index=0 377forward_latency=0 378frontend_latency=1 379p_state_clk_gate_bins=20 380p_state_clk_gate_max=1000000000000 381p_state_clk_gate_min=1000 382point_of_coherency=false 383power_model=Null 384response_latency=1 385snoop_filter=system.cpu.toL2Bus.snoop_filter 386snoop_response_latency=1 387system=system 388use_default_range=false 389width=32 390master=system.cpu.l2cache.cpu_side 391slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 392 393[system.cpu.toL2Bus.snoop_filter] 394type=SnoopFilter 395eventq_index=0 396lookup_latency=0 397max_capacity=8388608 398system=system 399 400[system.cpu.tracer] 401type=ExeTracer 402eventq_index=0 403 404[system.cpu.workload] 405type=LiveProcess 406cmd=hello 407cwd= 408drivers= 409egid=100 410env= 411errout=cerr 412euid=100 413eventq_index=0 414executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello 415gid=100 416input=cin 417kvmInSE=false 418max_stack_size=67108864 419output=cout 420pid=100 421ppid=99 422simpoint=0 423system=system 424uid=100 425useArchPT=false 426 427[system.cpu_clk_domain] 428type=SrcClockDomain 429clock=500 430domain_id=-1 431eventq_index=0 432init_perf_level=0 433voltage_domain=system.voltage_domain 434 435[system.dvfs_handler] 436type=DVFSHandler 437domains= 438enable=false 439eventq_index=0 440sys_clk_domain=system.clk_domain 441transition_latency=100000000 442 443[system.membus] 444type=CoherentXBar 445clk_domain=system.clk_domain 446default_p_state=UNDEFINED 447eventq_index=0 448forward_latency=4 449frontend_latency=3 450p_state_clk_gate_bins=20 451p_state_clk_gate_max=1000000000000 452p_state_clk_gate_min=1000 453point_of_coherency=true 454power_model=Null 455response_latency=2 456snoop_filter=Null 457snoop_response_latency=4 458system=system 459use_default_range=false 460width=16 461master=system.physmem.port 462slave=system.system_port system.cpu.l2cache.mem_side 463 464[system.physmem] 465type=SimpleMemory 466bandwidth=73.000000 467clk_domain=system.clk_domain 468conf_table_reported=true 469default_p_state=UNDEFINED 470eventq_index=0 471in_addr_map=true 472latency=30000 473latency_var=0 474null=false 475p_state_clk_gate_bins=20 476p_state_clk_gate_max=1000000000000 477p_state_clk_gate_min=1000 478power_model=Null 479range=0:134217727 480port=system.membus.master[0] 481 482[system.voltage_domain] 483type=VoltageDomain 484eventq_index=0 485voltage=1.000000 486 487