stats.txt revision 8889:2e38fd9937a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2875500 # Number of ticks simulated 5final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 76819 # Simulator instruction rate (inst/s) 8host_op_rate 95818 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47998674 # Simulator tick rate (ticks/s) 10host_mem_usage 212240 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 22944 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 3648 # Number of bytes written to this memory 17system.physmem.num_reads 5771 # Number of read requests responded to by this memory 18system.physmem.num_writes 924 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 25system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 26system.cpu.checker.dtb.read_hits 0 # DTB read hits 27system.cpu.checker.dtb.read_misses 0 # DTB read misses 28system.cpu.checker.dtb.write_hits 0 # DTB write hits 29system.cpu.checker.dtb.write_misses 0 # DTB write misses 30system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 37system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 38system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 40system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 41system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 42system.cpu.checker.dtb.hits 0 # DTB hits 43system.cpu.checker.dtb.misses 0 # DTB misses 44system.cpu.checker.dtb.accesses 0 # DTB accesses 45system.cpu.checker.itb.inst_hits 0 # ITB inst hits 46system.cpu.checker.itb.inst_misses 0 # ITB inst misses 47system.cpu.checker.itb.read_hits 0 # DTB read hits 48system.cpu.checker.itb.read_misses 0 # DTB read misses 49system.cpu.checker.itb.write_hits 0 # DTB write hits 50system.cpu.checker.itb.write_misses 0 # DTB write misses 51system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.checker.itb.read_accesses 0 # DTB read accesses 61system.cpu.checker.itb.write_accesses 0 # DTB write accesses 62system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.checker.itb.hits 0 # DTB hits 64system.cpu.checker.itb.misses 0 # DTB misses 65system.cpu.checker.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 13 # Number of system calls 67system.cpu.checker.numCycles 0 # number of cpu cycles simulated 68system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.itb.inst_hits 0 # ITB inst hits 92system.cpu.itb.inst_misses 0 # ITB inst misses 93system.cpu.itb.read_hits 0 # DTB read hits 94system.cpu.itb.read_misses 0 # DTB read misses 95system.cpu.itb.write_hits 0 # DTB write hits 96system.cpu.itb.write_misses 0 # DTB write misses 97system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 98system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 99system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 100system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 101system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 102system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 103system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 104system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 105system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 106system.cpu.itb.read_accesses 0 # DTB read accesses 107system.cpu.itb.write_accesses 0 # DTB write accesses 108system.cpu.itb.inst_accesses 0 # ITB inst accesses 109system.cpu.itb.hits 0 # DTB hits 110system.cpu.itb.misses 0 # DTB misses 111system.cpu.itb.accesses 0 # DTB accesses 112system.cpu.numCycles 5752 # number of cpu cycles simulated 113system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 114system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 115system.cpu.committedInsts 4600 # Number of instructions committed 116system.cpu.committedOps 5739 # Number of ops (including micro ops) committed 117system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses 118system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 119system.cpu.num_func_calls 185 # number of times a function call or return occured 120system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls 121system.cpu.num_int_insts 4985 # number of integer instructions 122system.cpu.num_fp_insts 16 # number of float instructions 123system.cpu.num_int_register_reads 25237 # number of times the integer registers were read 124system.cpu.num_int_register_writes 5345 # number of times the integer registers were written 125system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 126system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 127system.cpu.num_mem_refs 2139 # number of memory refs 128system.cpu.num_load_insts 1201 # Number of load instructions 129system.cpu.num_store_insts 938 # Number of store instructions 130system.cpu.num_idle_cycles 0 # Number of idle cycles 131system.cpu.num_busy_cycles 5752 # Number of busy cycles 132system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0 # Percentage of idle cycles 134 135---------- End Simulation Statistics ---------- 136