linux/simple-atomic-dummychecker/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000003
sim_ticks                                     2695000
final_tick                                    2695000
sim_freq                                 1000000000000
host_inst_rate                                 413531
host_op_rate                                   483368
host_tick_rate                              241807981
host_mem_usage                                 270560
host_seconds                                     0.01
sim_insts                                        4592
sim_ops                                          5378
system.voltage_domain.voltage                       1
system.clk_domain.clock                          1000
system.physmem.pwrStateResidencyTicks::UNDEFINED      2695000
system.physmem.bytes_read::cpu.inst             18420
system.physmem.bytes_read::cpu.data              4491
system.physmem.bytes_read::total                22911
system.physmem.bytes_inst_read::cpu.inst        18420
system.physmem.bytes_inst_read::total           18420
system.physmem.bytes_written::cpu.data           3648
system.physmem.bytes_written::total              3648
system.physmem.num_reads::cpu.inst               4605
system.physmem.num_reads::cpu.data               1003
system.physmem.num_reads::total                  5608
system.physmem.num_writes::cpu.data               924
system.physmem.num_writes::total                  924
system.physmem.bw_read::cpu.inst           6834879406
system.physmem.bw_read::cpu.data           1666419295
system.physmem.bw_read::total              8501298701
system.physmem.bw_inst_read::cpu.inst      6834879406
system.physmem.bw_inst_read::total         6834879406
system.physmem.bw_write::cpu.data          1353617811
system.physmem.bw_write::total             1353617811
system.physmem.bw_total::cpu.inst          6834879406
system.physmem.bw_total::cpu.data          3020037106
system.physmem.bw_total::total             9854916512
system.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu_clk_domain.clock                       500
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits            0
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb            0
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva            0
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid            0
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries            0
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults            0
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults            0
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults            0
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults            0
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0
system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0
system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.checker.dtb.walker.walks                 0
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total            0
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total            0
system.cpu.checker.dtb.walker.walkRequestOrigin::total            0
system.cpu.checker.dtb.inst_hits                    0
system.cpu.checker.dtb.inst_misses                  0
system.cpu.checker.dtb.read_hits                    0
system.cpu.checker.dtb.read_misses                  0
system.cpu.checker.dtb.write_hits                   0
system.cpu.checker.dtb.write_misses                 0
system.cpu.checker.dtb.flush_tlb                    0
system.cpu.checker.dtb.flush_tlb_mva                0
system.cpu.checker.dtb.flush_tlb_mva_asid            0
system.cpu.checker.dtb.flush_tlb_asid               0
system.cpu.checker.dtb.flush_entries                0
system.cpu.checker.dtb.align_faults                 0
system.cpu.checker.dtb.prefetch_faults              0
system.cpu.checker.dtb.domain_faults                0
system.cpu.checker.dtb.perms_faults                 0
system.cpu.checker.dtb.read_accesses                0
system.cpu.checker.dtb.write_accesses               0
system.cpu.checker.dtb.inst_accesses                0
system.cpu.checker.dtb.hits                         0
system.cpu.checker.dtb.misses                       0
system.cpu.checker.dtb.accesses                     0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses            0
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits            0
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses            0
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb            0
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva            0
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid            0
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries            0
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults            0
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults            0
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults            0
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults            0
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses            0
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses            0
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
system.cpu.checker.istage2_mmu.stage2_tlb.hits            0
system.cpu.checker.istage2_mmu.stage2_tlb.misses            0
system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0
system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.checker.itb.walker.walks                 0
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total            0
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total            0
system.cpu.checker.itb.walker.walkRequestOrigin::total            0
system.cpu.checker.itb.inst_hits                    0
system.cpu.checker.itb.inst_misses                  0
system.cpu.checker.itb.read_hits                    0
system.cpu.checker.itb.read_misses                  0
system.cpu.checker.itb.write_hits                   0
system.cpu.checker.itb.write_misses                 0
system.cpu.checker.itb.flush_tlb                    0
system.cpu.checker.itb.flush_tlb_mva                0
system.cpu.checker.itb.flush_tlb_mva_asid            0
system.cpu.checker.itb.flush_tlb_asid               0
system.cpu.checker.itb.flush_entries                0
system.cpu.checker.itb.align_faults                 0
system.cpu.checker.itb.prefetch_faults              0
system.cpu.checker.itb.domain_faults                0
system.cpu.checker.itb.perms_faults                 0
system.cpu.checker.itb.read_accesses                0
system.cpu.checker.itb.write_accesses               0
system.cpu.checker.itb.inst_accesses                0
system.cpu.checker.itb.hits                         0
system.cpu.checker.itb.misses                       0
system.cpu.checker.itb.accesses                     0
system.cpu.workload.numSyscalls                    13
system.cpu.checker.pwrStateResidencyTicks::ON      2695000
system.cpu.checker.numCycles                        0
system.cpu.checker.numWorkItemsStarted              0
system.cpu.checker.numWorkItemsCompleted            0
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
system.cpu.dstage2_mmu.stage2_tlb.hits              0
system.cpu.dstage2_mmu.stage2_tlb.misses            0
system.cpu.dstage2_mmu.stage2_tlb.accesses            0
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.dtb.walker.walks                         0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0
system.cpu.dtb.walker.walkRequestOrigin::total            0
system.cpu.dtb.inst_hits                            0
system.cpu.dtb.inst_misses                          0
system.cpu.dtb.read_hits                            0
system.cpu.dtb.read_misses                          0
system.cpu.dtb.write_hits                           0
system.cpu.dtb.write_misses                         0
system.cpu.dtb.flush_tlb                            0
system.cpu.dtb.flush_tlb_mva                        0
system.cpu.dtb.flush_tlb_mva_asid                   0
system.cpu.dtb.flush_tlb_asid                       0
system.cpu.dtb.flush_entries                        0
system.cpu.dtb.align_faults                         0
system.cpu.dtb.prefetch_faults                      0
system.cpu.dtb.domain_faults                        0
system.cpu.dtb.perms_faults                         0
system.cpu.dtb.read_accesses                        0
system.cpu.dtb.write_accesses                       0
system.cpu.dtb.inst_accesses                        0
system.cpu.dtb.hits                                 0
system.cpu.dtb.misses                               0
system.cpu.dtb.accesses                             0
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0
system.cpu.istage2_mmu.stage2_tlb.read_hits            0
system.cpu.istage2_mmu.stage2_tlb.read_misses            0
system.cpu.istage2_mmu.stage2_tlb.write_hits            0
system.cpu.istage2_mmu.stage2_tlb.write_misses            0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0
system.cpu.istage2_mmu.stage2_tlb.align_faults            0
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
system.cpu.istage2_mmu.stage2_tlb.hits              0
system.cpu.istage2_mmu.stage2_tlb.misses            0
system.cpu.istage2_mmu.stage2_tlb.accesses            0
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED      2695000
system.cpu.itb.walker.walks                         0
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0
system.cpu.itb.walker.walkRequestOrigin::total            0
system.cpu.itb.inst_hits                            0
system.cpu.itb.inst_misses                          0
system.cpu.itb.read_hits                            0
system.cpu.itb.read_misses                          0
system.cpu.itb.write_hits                           0
system.cpu.itb.write_misses                         0
system.cpu.itb.flush_tlb                            0
system.cpu.itb.flush_tlb_mva                        0
system.cpu.itb.flush_tlb_mva_asid                   0
system.cpu.itb.flush_tlb_asid                       0
system.cpu.itb.flush_entries                        0
system.cpu.itb.align_faults                         0
system.cpu.itb.prefetch_faults                      0
system.cpu.itb.domain_faults                        0
system.cpu.itb.perms_faults                         0
system.cpu.itb.read_accesses                        0
system.cpu.itb.write_accesses                       0
system.cpu.itb.inst_accesses                        0
system.cpu.itb.hits                                 0
system.cpu.itb.misses                               0
system.cpu.itb.accesses                             0
system.cpu.pwrStateResidencyTicks::ON         2695000
system.cpu.numCycles                             5391
system.cpu.numWorkItemsStarted                      0
system.cpu.numWorkItemsCompleted                    0
system.cpu.committedInsts                        4592
system.cpu.committedOps                          5378
system.cpu.num_int_alu_accesses                  4624
system.cpu.num_fp_alu_accesses                     16
system.cpu.num_func_calls                         203
system.cpu.num_conditional_control_insts          722
system.cpu.num_int_insts                         4624
system.cpu.num_fp_insts                            16
system.cpu.num_int_register_reads                7572
system.cpu.num_int_register_writes               2728
system.cpu.num_fp_register_reads                   16
system.cpu.num_fp_register_writes                   0
system.cpu.num_cc_register_reads                16175
system.cpu.num_cc_register_writes                2432
system.cpu.num_mem_refs                          1965
system.cpu.num_load_insts                        1027
system.cpu.num_store_insts                        938
system.cpu.num_idle_cycles                          0
system.cpu.num_busy_cycles                       5391
system.cpu.not_idle_fraction                        1
system.cpu.idle_fraction                            0
system.cpu.Branches                              1008
system.cpu.op_class::No_OpClass                     0      0.00%      0.00%
system.cpu.op_class::IntAlu                      3419     63.42%     63.42%
system.cpu.op_class::IntMult                        4      0.07%     63.49%
system.cpu.op_class::IntDiv                         0      0.00%     63.49%
system.cpu.op_class::FloatAdd                       0      0.00%     63.49%
system.cpu.op_class::FloatCmp                       0      0.00%     63.49%
system.cpu.op_class::FloatCvt                       0      0.00%     63.49%
system.cpu.op_class::FloatMult                      0      0.00%     63.49%
system.cpu.op_class::FloatMultAcc                   0      0.00%     63.49%
system.cpu.op_class::FloatDiv                       0      0.00%     63.49%
system.cpu.op_class::FloatMisc                      0      0.00%     63.49%
system.cpu.op_class::FloatSqrt                      0      0.00%     63.49%
system.cpu.op_class::SimdAdd                        0      0.00%     63.49%
system.cpu.op_class::SimdAddAcc                     0      0.00%     63.49%
system.cpu.op_class::SimdAlu                        0      0.00%     63.49%
system.cpu.op_class::SimdCmp                        0      0.00%     63.49%
system.cpu.op_class::SimdCvt                        0      0.00%     63.49%
system.cpu.op_class::SimdMisc                       0      0.00%     63.49%
system.cpu.op_class::SimdMult                       0      0.00%     63.49%
system.cpu.op_class::SimdMultAcc                    0      0.00%     63.49%
system.cpu.op_class::SimdShift                      0      0.00%     63.49%
system.cpu.op_class::SimdShiftAcc                   0      0.00%     63.49%
system.cpu.op_class::SimdSqrt                       0      0.00%     63.49%
system.cpu.op_class::SimdFloatAdd                   0      0.00%     63.49%
system.cpu.op_class::SimdFloatAlu                   0      0.00%     63.49%
system.cpu.op_class::SimdFloatCmp                   0      0.00%     63.49%
system.cpu.op_class::SimdFloatCvt                   0      0.00%     63.49%
system.cpu.op_class::SimdFloatDiv                   0      0.00%     63.49%
system.cpu.op_class::SimdFloatMisc                  3      0.06%     63.55%
system.cpu.op_class::SimdFloatMult                  0      0.00%     63.55%
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     63.55%
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     63.55%
system.cpu.op_class::MemRead                     1027     19.05%     82.60%
system.cpu.op_class::MemWrite                     922     17.10%     99.70%
system.cpu.op_class::FloatMemRead                   0      0.00%     99.70%
system.cpu.op_class::FloatMemWrite                 16      0.30%    100.00%
system.cpu.op_class::IprAccess                      0      0.00%    100.00%
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00%
system.cpu.op_class::total                       5391
system.membus.snoop_filter.tot_requests             0
system.membus.snoop_filter.hit_single_requests            0
system.membus.snoop_filter.hit_multi_requests            0
system.membus.snoop_filter.tot_snoops               0
system.membus.snoop_filter.hit_single_snoops            0
system.membus.snoop_filter.hit_multi_snoops            0
system.membus.pwrStateResidencyTicks::UNDEFINED      2695000
system.membus.trans_dist::ReadReq                5597
system.membus.trans_dist::ReadResp               5608
system.membus.trans_dist::WriteReq                913
system.membus.trans_dist::WriteResp               913
system.membus.trans_dist::LoadLockedReq            11
system.membus.trans_dist::StoreCondReq             11
system.membus.trans_dist::StoreCondResp            11
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9210
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854
system.membus.pkt_count::total                  13064
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18420
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139
system.membus.pkt_size::total                   26559
system.membus.snoops                                0
system.membus.snoopTraffic                          0
system.membus.snoop_fanout::samples              6532
system.membus.snoop_fanout::mean                    0
system.membus.snoop_fanout::stdev                   0
system.membus.snoop_fanout::underflows              0      0.00%      0.00%
system.membus.snoop_fanout::0                    6532    100.00%    100.00%
system.membus.snoop_fanout::1                       0      0.00%    100.00%
system.membus.snoop_fanout::overflows               0      0.00%    100.00%
system.membus.snoop_fanout::min_value               0
system.membus.snoop_fanout::max_value               0
system.membus.snoop_fanout::total                6532

---------- End Simulation Statistics   ----------