stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2870500 # Number of ticks simulated 5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 61907 # Simulator instruction rate (inst/s) 8host_op_rate 77238 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38693079 # Simulator tick rate (ticks/s) 10host_mem_usage 237008 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9251001568 # Throughput (bytes/s) 39system.membus.data_through_bus 26555 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 43system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 44system.cpu.checker.dtb.read_hits 0 # DTB read hits 45system.cpu.checker.dtb.read_misses 0 # DTB read misses 46system.cpu.checker.dtb.write_hits 0 # DTB write hits 47system.cpu.checker.dtb.write_misses 0 # DTB write misses 48system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 58system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 59system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 60system.cpu.checker.dtb.hits 0 # DTB hits 61system.cpu.checker.dtb.misses 0 # DTB misses 62system.cpu.checker.dtb.accesses 0 # DTB accesses 63system.cpu.checker.itb.inst_hits 0 # ITB inst hits 64system.cpu.checker.itb.inst_misses 0 # ITB inst misses 65system.cpu.checker.itb.read_hits 0 # DTB read hits 66system.cpu.checker.itb.read_misses 0 # DTB read misses 67system.cpu.checker.itb.write_hits 0 # DTB write hits 68system.cpu.checker.itb.write_misses 0 # DTB write misses 69system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 73system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 74system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 75system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.checker.itb.read_accesses 0 # DTB read accesses 79system.cpu.checker.itb.write_accesses 0 # DTB write accesses 80system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 81system.cpu.checker.itb.hits 0 # DTB hits 82system.cpu.checker.itb.misses 0 # DTB misses 83system.cpu.checker.itb.accesses 0 # DTB accesses 84system.cpu.workload.num_syscalls 13 # Number of system calls 85system.cpu.checker.numCycles 0 # number of cpu cycles simulated 86system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 87system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 88system.cpu.dtb.inst_hits 0 # ITB inst hits 89system.cpu.dtb.inst_misses 0 # ITB inst misses 90system.cpu.dtb.read_hits 0 # DTB read hits 91system.cpu.dtb.read_misses 0 # DTB read misses 92system.cpu.dtb.write_hits 0 # DTB write hits 93system.cpu.dtb.write_misses 0 # DTB write misses 94system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 95system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 96system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 97system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 98system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 99system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 100system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 101system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 102system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 103system.cpu.dtb.read_accesses 0 # DTB read accesses 104system.cpu.dtb.write_accesses 0 # DTB write accesses 105system.cpu.dtb.inst_accesses 0 # ITB inst accesses 106system.cpu.dtb.hits 0 # DTB hits 107system.cpu.dtb.misses 0 # DTB misses 108system.cpu.dtb.accesses 0 # DTB accesses 109system.cpu.itb.inst_hits 0 # ITB inst hits 110system.cpu.itb.inst_misses 0 # ITB inst misses 111system.cpu.itb.read_hits 0 # DTB read hits 112system.cpu.itb.read_misses 0 # DTB read misses 113system.cpu.itb.write_hits 0 # DTB write hits 114system.cpu.itb.write_misses 0 # DTB write misses 115system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 116system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 117system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 118system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 119system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 120system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 121system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 122system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 123system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 124system.cpu.itb.read_accesses 0 # DTB read accesses 125system.cpu.itb.write_accesses 0 # DTB write accesses 126system.cpu.itb.inst_accesses 0 # ITB inst accesses 127system.cpu.itb.hits 0 # DTB hits 128system.cpu.itb.misses 0 # DTB misses 129system.cpu.itb.accesses 0 # DTB accesses 130system.cpu.numCycles 5742 # number of cpu cycles simulated 131system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 132system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 133system.cpu.committedInsts 4591 # Number of instructions committed 134system.cpu.committedOps 5729 # Number of ops (including micro ops) committed 135system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 136system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 137system.cpu.num_func_calls 203 # number of times a function call or return occured 138system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 139system.cpu.num_int_insts 4976 # number of integer instructions 140system.cpu.num_fp_insts 16 # number of float instructions 141system.cpu.num_int_register_reads 25195 # number of times the integer registers were read 142system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 143system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 144system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 145system.cpu.num_mem_refs 2138 # number of memory refs 146system.cpu.num_load_insts 1200 # Number of load instructions 147system.cpu.num_store_insts 938 # Number of store instructions 148system.cpu.num_idle_cycles 0 # Number of idle cycles 149system.cpu.num_busy_cycles 5742 # Number of busy cycles 150system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 151system.cpu.idle_fraction 0 # Percentage of idle cycles 152 153---------- End Simulation Statistics ---------- 154