stats.txt revision 9459:8ca90cef0183
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 13354000 # Number of ticks simulated 5final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 53438 # Simulator instruction rate (inst/s) 8host_op_rate 66670 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 155374810 # Simulator tick rate (ticks/s) 10host_mem_usage 242400 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1303579452 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 584693725 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1888273177 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1303579452 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1303579452 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1303579452 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 584693725 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1888273177 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 73system.physmem.totGap 13296500 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes 82system.physmem.readPktSize::8 0 # Categorize read packet sizes 83system.physmem.writePktSize::0 0 # categorize write packet sizes 84system.physmem.writePktSize::1 0 # categorize write packet sizes 85system.physmem.writePktSize::2 0 # categorize write packet sizes 86system.physmem.writePktSize::3 0 # categorize write packet sizes 87system.physmem.writePktSize::4 0 # categorize write packet sizes 88system.physmem.writePktSize::5 0 # categorize write packet sizes 89system.physmem.writePktSize::6 0 # categorize write packet sizes 90system.physmem.writePktSize::7 0 # categorize write packet sizes 91system.physmem.writePktSize::8 0 # categorize write packet sizes 92system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 101system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 134system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 169system.physmem.totBusLat 1576000 # Total cycles spent in databus access 170system.physmem.totBankLat 6524000 # Total cycles spent in bank access 171system.physmem.avgQLat 6245.92 # Average queueing delay per request 172system.physmem.avgBankLat 16558.38 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26804.30 # Average memory access latency 175system.physmem.avgRdBW 1888.27 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 1888.27 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 11.80 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.79 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 319 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap 33747.46 # Average gap between requests 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 196system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 197system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 198system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 199system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 200system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 201system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 202system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 203system.cpu.dtb.read_accesses 0 # DTB read accesses 204system.cpu.dtb.write_accesses 0 # DTB write accesses 205system.cpu.dtb.inst_accesses 0 # ITB inst accesses 206system.cpu.dtb.hits 0 # DTB hits 207system.cpu.dtb.misses 0 # DTB misses 208system.cpu.dtb.accesses 0 # DTB accesses 209system.cpu.itb.inst_hits 0 # ITB inst hits 210system.cpu.itb.inst_misses 0 # ITB inst misses 211system.cpu.itb.read_hits 0 # DTB read hits 212system.cpu.itb.read_misses 0 # DTB read misses 213system.cpu.itb.write_hits 0 # DTB write hits 214system.cpu.itb.write_misses 0 # DTB write misses 215system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 216system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 217system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 218system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 219system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 220system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 221system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 222system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 13 # Number of system calls 231system.cpu.numCycles 26709 # number of cpu cycles simulated 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.BPredUnit.lookups 2501 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 242system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss 243system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing 248system.cpu.fetch.BlockedCycles 2216 # Number of cycles fetch has spent blocked 249system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched 250system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 251system.cpu.fetch.rateDist::samples 12880 # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::mean 1.183618 # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::stdev 2.594570 # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::0 10229 79.42% 79.42% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::1 225 1.75% 81.16% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::2 203 1.58% 82.74% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::3 224 1.74% 84.48% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::4 223 1.73% 86.21% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::5 273 2.12% 88.33% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::6 95 0.74% 89.07% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::7 149 1.16% 90.23% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::8 1259 9.77% 100.00% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::total 12880 # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.branchRate 0.093639 # Number of branch fetches per cycle 269system.cpu.fetch.rate 0.449661 # Number of inst fetches per cycle 270system.cpu.decode.IdleCycles 6875 # Number of cycles decode is idle 271system.cpu.decode.BlockedCycles 2529 # Number of cycles decode is blocked 272system.cpu.decode.RunCycles 2444 # Number of cycles decode is running 273system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 274system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 275system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch 276system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 277system.cpu.decode.DecodedInsts 13347 # Number of instructions handled by decode 278system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 279system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 280system.cpu.rename.IdleCycles 7140 # Number of cycles rename is idle 281system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 282system.cpu.rename.serializeStallCycles 1992 # count of cycles rename stalled for serializing inst 283system.cpu.rename.RunCycles 2245 # Number of cycles rename is running 284system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 285system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename 286system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 287system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 288system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 289system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed 290system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made 291system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups 292system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 293system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 294system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing 295system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 296system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 297system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer 298system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. 299system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. 300system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 301system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 302system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) 303system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 304system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 305system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 306system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling 307system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph 308system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 309system.cpu.iq.issued_per_cycle::samples 12880 # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::mean 0.697826 # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::stdev 1.403354 # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::0 9299 72.20% 72.20% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::1 1308 10.16% 82.35% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::2 806 6.26% 88.61% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::3 539 4.18% 92.80% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::4 466 3.62% 96.41% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::5 270 2.10% 98.51% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::6 122 0.95% 99.46% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::total 12880 # Number of insts issued each cycle 326system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 327system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 328system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 329system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 335system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 356system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 357system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 358system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 359system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 360system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 361system.cpu.iq.FU_type_0::IntAlu 5406 60.15% 60.15% # Type of FU issued 362system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.22% # Type of FU issued 363system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued 367system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued 368system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued 369system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.22% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.22% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.26% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.26% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.26% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.26% # Type of FU issued 390system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.39% # Type of FU issued 391system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued 392system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 393system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 394system.cpu.iq.FU_type_0::total 8988 # Type of FU issued 395system.cpu.iq.rate 0.336516 # Inst issue rate 396system.cpu.iq.fu_busy_cnt 228 # FU busy when requested 397system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) 398system.cpu.iq.int_inst_queue_reads 31164 # Number of integer instruction queue reads 399system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes 400system.cpu.iq.int_inst_queue_wakeup_accesses 8089 # Number of integer instruction queue wakeup accesses 401system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 402system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 403system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 404system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 405system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 406system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 407system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 408system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 409system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 410system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations 411system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed 412system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 413system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 414system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 415system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 416system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 417system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 418system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 419system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 420system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ 421system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch 422system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions 423system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions 424system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 425system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 426system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 427system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations 428system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly 429system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly 430system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute 431system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions 432system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 433system.cpu.iew.iewExecSquashedInsts 425 # Number of squashed instructions skipped in execute 434system.cpu.iew.exec_swp 0 # number of swp insts executed 435system.cpu.iew.exec_nop 0 # number of nop insts executed 436system.cpu.iew.exec_refs 3303 # number of memory reference insts executed 437system.cpu.iew.exec_branches 1443 # Number of branches executed 438system.cpu.iew.exec_stores 1167 # Number of stores executed 439system.cpu.iew.exec_rate 0.320604 # Inst execution rate 440system.cpu.iew.wb_sent 8264 # cumulative count of insts sent to commit 441system.cpu.iew.wb_count 8105 # cumulative count of insts written-back 442system.cpu.iew.wb_producers 3904 # num instructions producing a value 443system.cpu.iew.wb_consumers 7842 # num instructions consuming a value 444system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 445system.cpu.iew.wb_rate 0.303456 # insts written-back per cycle 446system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back 447system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 448system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit 449system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 450system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted 451system.cpu.commit.committed_per_cycle::samples 11917 # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::mean 0.480742 # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::stdev 1.314534 # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::0 9632 80.83% 80.83% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::1 1071 8.99% 89.81% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::2 396 3.32% 93.14% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::3 259 2.17% 95.31% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::4 183 1.54% 96.84% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::total 11917 # Number of insts commited each cycle 468system.cpu.commit.committedInsts 4591 # Number of instructions committed 469system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 470system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 471system.cpu.commit.refs 2138 # Number of memory references committed 472system.cpu.commit.loads 1200 # Number of loads committed 473system.cpu.commit.membars 12 # Number of memory barriers committed 474system.cpu.commit.branches 1007 # Number of branches committed 475system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 476system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 477system.cpu.commit.function_calls 82 # Number of function calls committed. 478system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 479system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 480system.cpu.rob.rob_reads 22955 # The number of ROB reads 481system.cpu.rob.rob_writes 23605 # The number of ROB writes 482system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 483system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling 484system.cpu.committedInsts 4591 # Number of Instructions Simulated 485system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 486system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 487system.cpu.cpi 5.817687 # CPI: Cycles Per Instruction 488system.cpu.cpi_total 5.817687 # CPI: Total CPI of All Threads 489system.cpu.ipc 0.171890 # IPC: Instructions Per Cycle 490system.cpu.ipc_total 0.171890 # IPC: Total IPC of All Threads 491system.cpu.int_regfile_reads 39368 # number of integer regfile reads 492system.cpu.int_regfile_writes 8018 # number of integer regfile writes 493system.cpu.fp_regfile_reads 16 # number of floating regfile reads 494system.cpu.misc_regfile_reads 2982 # number of misc regfile reads 495system.cpu.misc_regfile_writes 24 # number of misc regfile writes 496system.cpu.icache.replacements 3 # number of replacements 497system.cpu.icache.tagsinuse 147.647008 # Cycle average of tags in use 498system.cpu.icache.total_refs 1597 # Total number of references to valid blocks. 499system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. 500system.cpu.icache.avg_refs 5.487973 # Average number of references to valid blocks. 501system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 502system.cpu.icache.occ_blocks::cpu.inst 147.647008 # Average occupied blocks per requestor 503system.cpu.icache.occ_percent::cpu.inst 0.072093 # Average percentage of cache occupancy 504system.cpu.icache.occ_percent::total 0.072093 # Average percentage of cache occupancy 505system.cpu.icache.ReadReq_hits::cpu.inst 1597 # number of ReadReq hits 506system.cpu.icache.ReadReq_hits::total 1597 # number of ReadReq hits 507system.cpu.icache.demand_hits::cpu.inst 1597 # number of demand (read+write) hits 508system.cpu.icache.demand_hits::total 1597 # number of demand (read+write) hits 509system.cpu.icache.overall_hits::cpu.inst 1597 # number of overall hits 510system.cpu.icache.overall_hits::total 1597 # number of overall hits 511system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 512system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 513system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 514system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 515system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 516system.cpu.icache.overall_misses::total 359 # number of overall misses 517system.cpu.icache.ReadReq_miss_latency::cpu.inst 17287500 # number of ReadReq miss cycles 518system.cpu.icache.ReadReq_miss_latency::total 17287500 # number of ReadReq miss cycles 519system.cpu.icache.demand_miss_latency::cpu.inst 17287500 # number of demand (read+write) miss cycles 520system.cpu.icache.demand_miss_latency::total 17287500 # number of demand (read+write) miss cycles 521system.cpu.icache.overall_miss_latency::cpu.inst 17287500 # number of overall miss cycles 522system.cpu.icache.overall_miss_latency::total 17287500 # number of overall miss cycles 523system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) 524system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 525system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses 526system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses 527system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses 528system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses 529system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183538 # miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_miss_rate::total 0.183538 # miss rate for ReadReq accesses 531system.cpu.icache.demand_miss_rate::cpu.inst 0.183538 # miss rate for demand accesses 532system.cpu.icache.demand_miss_rate::total 0.183538 # miss rate for demand accesses 533system.cpu.icache.overall_miss_rate::cpu.inst 0.183538 # miss rate for overall accesses 534system.cpu.icache.overall_miss_rate::total 0.183538 # miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48154.596100 # average ReadReq miss latency 536system.cpu.icache.ReadReq_avg_miss_latency::total 48154.596100 # average ReadReq miss latency 537system.cpu.icache.demand_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 538system.cpu.icache.demand_avg_miss_latency::total 48154.596100 # average overall miss latency 539system.cpu.icache.overall_avg_miss_latency::cpu.inst 48154.596100 # average overall miss latency 540system.cpu.icache.overall_avg_miss_latency::total 48154.596100 # average overall miss latency 541system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 542system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 543system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 544system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 545system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 546system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 547system.cpu.icache.fast_writes 0 # number of fast writes performed 548system.cpu.icache.cache_copies 0 # number of cache copies performed 549system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 550system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 551system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 552system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 553system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 554system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 555system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 556system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 557system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 558system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 559system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 560system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses 561system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14218500 # number of ReadReq MSHR miss cycles 562system.cpu.icache.ReadReq_mshr_miss_latency::total 14218500 # number of ReadReq MSHR miss cycles 563system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14218500 # number of demand (read+write) MSHR miss cycles 564system.cpu.icache.demand_mshr_miss_latency::total 14218500 # number of demand (read+write) MSHR miss cycles 565system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14218500 # number of overall MSHR miss cycles 566system.cpu.icache.overall_mshr_miss_latency::total 14218500 # number of overall MSHR miss cycles 567system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses 568system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses 569system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses 570system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses 571system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses 572system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses 573system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48860.824742 # average ReadReq mshr miss latency 574system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48860.824742 # average ReadReq mshr miss latency 575system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 576system.cpu.icache.demand_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency 577system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48860.824742 # average overall mshr miss latency 578system.cpu.icache.overall_avg_mshr_miss_latency::total 48860.824742 # average overall mshr miss latency 579system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 580system.cpu.l2cache.replacements 0 # number of replacements 581system.cpu.l2cache.tagsinuse 185.926666 # Cycle average of tags in use 582system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. 583system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 584system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. 585system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 586system.cpu.l2cache.occ_blocks::cpu.inst 139.061385 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_blocks::cpu.data 46.865282 # Average occupied blocks per requestor 588system.cpu.l2cache.occ_percent::cpu.inst 0.004244 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.001430 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.005674 # Average percentage of cache occupancy 591system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 594system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 595system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 596system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 597system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 598system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 599system.cpu.l2cache.overall_hits::total 39 # number of overall hits 600system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 601system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 602system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 603system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 604system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 605system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 606system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 607system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 608system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 609system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 610system.cpu.l2cache.overall_misses::total 399 # number of overall misses 611system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles 612system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles 613system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles 614system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 615system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 616system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 617system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 618system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 619system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 620system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 621system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles 622system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 623system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 624system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 625system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 626system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 627system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 628system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 629system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 630system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 631system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 632system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses 633system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses 634system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 635system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses 636system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 637system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 638system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses 639system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 640system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses 641system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses 642system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 643system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses 644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 645system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 646system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 647system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 648system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 649system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 650system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 651system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency 652system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 653system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency 655system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 656system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 659system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 661system.cpu.l2cache.fast_writes 0 # number of fast writes performed 662system.cpu.l2cache.cache_copies 0 # number of cache copies performed 663system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 664system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 665system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 672system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 673system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 674system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 675system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 676system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 678system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 679system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 680system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles 681system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 684system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 685system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 686system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 687system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 688system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 689system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 690system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles 691system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses 692system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 693system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses 694system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 695system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 696system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses 697system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 698system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses 699system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses 700system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 701system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses 702system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 703system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 704system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 705system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 706system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 707system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 708system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 709system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 710system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 711system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 712system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 713system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 714system.cpu.dcache.replacements 0 # number of replacements 715system.cpu.dcache.tagsinuse 86.800851 # Cycle average of tags in use 716system.cpu.dcache.total_refs 2395 # Total number of references to valid blocks. 717system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 718system.cpu.dcache.avg_refs 16.404110 # Average number of references to valid blocks. 719system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 720system.cpu.dcache.occ_blocks::cpu.data 86.800851 # Average occupied blocks per requestor 721system.cpu.dcache.occ_percent::cpu.data 0.021192 # Average percentage of cache occupancy 722system.cpu.dcache.occ_percent::total 0.021192 # Average percentage of cache occupancy 723system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits 724system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits 725system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 726system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 731system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits 732system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits 733system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits 734system.cpu.dcache.overall_hits::total 2373 # number of overall hits 735system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 736system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 737system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 739system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 740system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 741system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 742system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 743system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 744system.cpu.dcache.overall_misses::total 498 # number of overall misses 745system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles 746system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles 747system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 749system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 751system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles 755system.cpu.dcache.ReadReq_accesses::cpu.data 1958 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1958 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 760system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 762system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 763system.cpu.dcache.demand_accesses::cpu.data 2871 # number of demand (read+write) accesses 764system.cpu.dcache.demand_accesses::total 2871 # number of demand (read+write) accesses 765system.cpu.dcache.overall_accesses::cpu.data 2871 # number of overall (read+write) accesses 766system.cpu.dcache.overall_accesses::total 2871 # number of overall (read+write) accesses 767system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097549 # miss rate for ReadReq accesses 768system.cpu.dcache.ReadReq_miss_rate::total 0.097549 # miss rate for ReadReq accesses 769system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 770system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 773system.cpu.dcache.demand_miss_rate::cpu.data 0.173459 # miss rate for demand accesses 774system.cpu.dcache.demand_miss_rate::total 0.173459 # miss rate for demand accesses 775system.cpu.dcache.overall_miss_rate::cpu.data 0.173459 # miss rate for overall accesses 776system.cpu.dcache.overall_miss_rate::total 0.173459 # miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 778system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency 779system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 783system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 784system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency 787system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 788system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.dcache.fast_writes 0 # number of fast writes performed 794system.cpu.dcache.cache_copies 0 # number of cache copies performed 795system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 796system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 797system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 798system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 799system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 800system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 801system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 802system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 803system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 804system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 809system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 810system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 811system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 812system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 813system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 814system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles 815system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 816system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054137 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054137 # mshr miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 825system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for demand accesses 826system.cpu.dcache.demand_mshr_miss_rate::total 0.051202 # mshr miss rate for demand accesses 827system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051202 # mshr miss rate for overall accesses 828system.cpu.dcache.overall_mshr_miss_rate::total 0.051202 # mshr miss rate for overall accesses 829system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency 831system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 832system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 834system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 836system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 837system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 838 839---------- End Simulation Statistics ---------- 840