stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 49511 # Simulator instruction rate (inst/s) 8host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 110854808 # Simulator tick rate (ticks/s) 10host_mem_usage 229756 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25664 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 401 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls 73system.cpu.numCycles 20608 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.BPredUnit.lookups 2552 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 82system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps 93system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched 94system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed 95system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle 113system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle 114system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle 115system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked 116system.cpu.decode.RunCycles 2624 # Number of cycles decode is running 117system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking 118system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing 119system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch 120system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction 121system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode 122system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode 123system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing 124system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle 125system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking 126system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst 127system.cpu.rename.RunCycles 2398 # Number of cycles rename is running 128system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking 129system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename 130system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full 131system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full 132system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed 133system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made 134system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups 135system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups 136system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed 137system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing 138system.cpu.rename.serializingInsts 44 # count of serializing insts renamed 139system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed 140system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer 141system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. 142system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. 143system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. 144system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. 145system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) 146system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ 147system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued 148system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued 149system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling 150system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph 151system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 152system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle 169system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 170system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available 171system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available 172system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 199system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available 200system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available 201system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 202system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 203system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 204system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued 205system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued 206system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued 233system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued 234system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued 235system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 236system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 237system.cpu.iq.FU_type_0::total 9165 # Type of FU issued 238system.cpu.iq.rate 0.444730 # Inst issue rate 239system.cpu.iq.fu_busy_cnt 215 # FU busy when requested 240system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) 241system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads 242system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes 243system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses 244system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 245system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 246system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 247system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses 248system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 249system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 250system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 251system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed 252system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 253system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 254system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed 255system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 256system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 257system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 258system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 259system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 260system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing 261system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking 262system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking 263system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ 264system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch 265system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions 266system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions 267system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 268system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 269system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 270system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 271system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly 272system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly 273system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute 274system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions 275system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed 276system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute 277system.cpu.iew.exec_swp 0 # number of swp insts executed 278system.cpu.iew.exec_nop 1 # number of nop insts executed 279system.cpu.iew.exec_refs 3351 # number of memory reference insts executed 280system.cpu.iew.exec_branches 1406 # Number of branches executed 281system.cpu.iew.exec_stores 1199 # Number of stores executed 282system.cpu.iew.exec_rate 0.420565 # Inst execution rate 283system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit 284system.cpu.iew.wb_count 8167 # cumulative count of insts written-back 285system.cpu.iew.wb_producers 3874 # num instructions producing a value 286system.cpu.iew.wb_consumers 7832 # num instructions consuming a value 287system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 288system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle 289system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back 290system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 291system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions 292system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions 293system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit 294system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 295system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted 296system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle 313system.cpu.commit.committedInsts 4600 # Number of instructions committed 314system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed 315system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 316system.cpu.commit.refs 2139 # Number of memory references committed 317system.cpu.commit.loads 1201 # Number of loads committed 318system.cpu.commit.membars 12 # Number of memory barriers committed 319system.cpu.commit.branches 945 # Number of branches committed 320system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 321system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 322system.cpu.commit.function_calls 82 # Number of function calls committed. 323system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached 324system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 325system.cpu.rob.rob_reads 22629 # The number of ROB reads 326system.cpu.rob.rob_writes 24771 # The number of ROB writes 327system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself 328system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling 329system.cpu.committedInsts 4600 # Number of Instructions Simulated 330system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated 331system.cpu.committedInsts_total 4600 # Number of Instructions Simulated 332system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction 333system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads 334system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle 335system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads 336system.cpu.int_regfile_reads 39716 # number of integer regfile reads 337system.cpu.int_regfile_writes 8038 # number of integer regfile writes 338system.cpu.fp_regfile_reads 16 # number of floating regfile reads 339system.cpu.misc_regfile_reads 16043 # number of misc regfile reads 340system.cpu.misc_regfile_writes 24 # number of misc regfile writes 341system.cpu.icache.replacements 2 # number of replacements 342system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use 343system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. 344system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 345system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. 346system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 347system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor 348system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy 349system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy 350system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits 351system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits 352system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits 353system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits 354system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits 355system.cpu.icache.overall_hits::total 1665 # number of overall hits 356system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses 357system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses 358system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses 359system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses 360system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses 361system.cpu.icache.overall_misses::total 366 # number of overall misses 362system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles 363system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles 364system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles 365system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles 366system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles 367system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles 368system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) 369system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) 370system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses 371system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses 372system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses 373system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses 374system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses 376system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses 377system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses 378system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses 379system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses 380system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency 381system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency 382system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 383system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency 384system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency 386system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu.icache.fast_writes 0 # number of fast writes performed 393system.cpu.icache.cache_copies 0 # number of cache copies performed 394system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 395system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 396system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 397system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 398system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 399system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits 400system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 401system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 402system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 403system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 404system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 405system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 406system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles 407system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles 408system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles 409system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles 410system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles 411system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles 412system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses 413system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses 414system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses 415system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses 416system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses 417system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses 418system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency 419system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency 420system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency 421system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency 422system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency 423system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency 424system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 425system.cpu.dcache.replacements 0 # number of replacements 426system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use 427system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. 428system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 429system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. 430system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 431system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor 432system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy 433system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy 434system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits 435system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits 436system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits 437system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits 438system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 439system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 440system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 441system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 442system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits 443system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits 444system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits 445system.cpu.dcache.overall_hits::total 2405 # number of overall hits 446system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 447system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 448system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses 449system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses 450system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 451system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 452system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses 453system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses 454system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses 455system.cpu.dcache.overall_misses::total 474 # number of overall misses 456system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles 457system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles 458system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles 459system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles 460system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 461system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles 462system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles 463system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles 464system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles 465system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles 466system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 471system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 472system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 473system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 474system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses 475system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses 476system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses 477system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses 478system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses 479system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses 480system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses 481system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses 482system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 483system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 484system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses 485system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses 486system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses 487system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses 488system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency 489system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency 490system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 491system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency 492system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 493system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 507system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 508system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 509system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 510system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 511system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 520system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 521system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 522system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 523system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 524system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles 531system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles 532system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 536system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses 537system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses 538system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses 539system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency 541system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency 543system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency 545system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency 548system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 549system.cpu.l2cache.replacements 0 # number of replacements 550system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use 551system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 552system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. 553system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. 554system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 555system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor 556system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor 557system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy 559system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy 560system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 562system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 563system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 564system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 565system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 566system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 567system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 568system.cpu.l2cache.overall_hits::total 40 # number of overall hits 569system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 570system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 571system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses 572system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 573system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 574system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 575system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses 576system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses 577system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 578system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses 579system.cpu.l2cache.overall_misses::total 405 # number of overall misses 580system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles 581system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles 582system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles 583system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles 584system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles 587system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles 590system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles 591system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 592system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) 593system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) 594system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 595system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 596system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 598system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 599system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 600system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 601system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 602system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses 603system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses 604system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses 605system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 606system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 607system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses 608system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses 609system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses 610system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses 611system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses 612system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses 613system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency 614system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency 615system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency 616system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency 617system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency 618system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 619system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 620system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency 621system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed 632system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 633system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 634system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 635system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 636system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 637system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses 641system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 643system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses 666system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses 667system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses 669system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses 670system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency 682system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 683 684---------- End Simulation Statistics ---------- 685