stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10001500 # Number of ticks simulated 5final_tick 10001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 15723 # Simulator instruction rate (inst/s) 8host_tick_rate 27400304 # Simulator tick rate (ticks/s) 9host_mem_usage 218472 # Number of bytes of host memory used 10host_seconds 0.37 # Real time elapsed on the host 11sim_insts 5739 # Number of instructions simulated 12system.physmem.bytes_read 25856 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 404 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2585212218 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 1785332200 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 2585212218 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.inst_hits 0 # ITB inst hits 22system.cpu.dtb.inst_misses 0 # ITB inst misses 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.write_hits 0 # DTB write hits 26system.cpu.dtb.write_misses 0 # DTB write misses 27system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 28system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 32system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36system.cpu.dtb.read_accesses 0 # DTB read accesses 37system.cpu.dtb.write_accesses 0 # DTB write accesses 38system.cpu.dtb.inst_accesses 0 # ITB inst accesses 39system.cpu.dtb.hits 0 # DTB hits 40system.cpu.dtb.misses 0 # DTB misses 41system.cpu.dtb.accesses 0 # DTB accesses 42system.cpu.itb.inst_hits 0 # ITB inst hits 43system.cpu.itb.inst_misses 0 # ITB inst misses 44system.cpu.itb.read_hits 0 # DTB read hits 45system.cpu.itb.read_misses 0 # DTB read misses 46system.cpu.itb.write_hits 0 # DTB write hits 47system.cpu.itb.write_misses 0 # DTB write misses 48system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.itb.read_accesses 0 # DTB read accesses 58system.cpu.itb.write_accesses 0 # DTB write accesses 59system.cpu.itb.inst_accesses 0 # ITB inst accesses 60system.cpu.itb.hits 0 # DTB hits 61system.cpu.itb.misses 0 # DTB misses 62system.cpu.itb.accesses 0 # DTB accesses 63system.cpu.workload.num_syscalls 13 # Number of system calls 64system.cpu.numCycles 20004 # number of cpu cycles simulated 65system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 66system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 67system.cpu.BPredUnit.lookups 2398 # Number of BP lookups 68system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted 69system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect 70system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups 71system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits 72system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 73system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. 74system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. 75system.cpu.fetch.icacheStallCycles 6120 # Number of cycles fetch is stalled on an Icache miss 76system.cpu.fetch.Insts 12134 # Number of instructions fetch has processed 77system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered 78system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken 79system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked 80system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing 81system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked 82system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 83system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps 84system.cpu.fetch.CacheLines 1920 # Number of cache lines fetched 85system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed 86system.cpu.fetch.rateDist::samples 11510 # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::mean 1.338054 # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::stdev 2.716635 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::0 8816 76.59% 76.59% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::3 225 1.95% 82.29% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::4 227 1.97% 84.27% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::5 313 2.72% 86.99% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::total 11510 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.branchRate 0.119876 # Number of branch fetches per cycle 104system.cpu.fetch.rate 0.606579 # Number of inst fetches per cycle 105system.cpu.decode.IdleCycles 6265 # Number of cycles decode is idle 106system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked 107system.cpu.decode.RunCycles 2491 # Number of cycles decode is running 108system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking 109system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing 110system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch 111system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction 112system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode 113system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode 114system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing 115system.cpu.rename.IdleCycles 6541 # Number of cycles rename is idle 116system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking 117system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst 118system.cpu.rename.RunCycles 2270 # Number of cycles rename is running 119system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking 120system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename 121system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full 122system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed 123system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made 124system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups 125system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups 126system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed 127system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing 128system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 129system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed 130system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer 131system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. 132system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. 133system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. 134system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 135system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) 136system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 137system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued 138system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued 139system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling 140system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph 141system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 142system.cpu.iq.issued_per_cycle::samples 11510 # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::mean 0.756386 # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::stdev 1.438063 # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::0 8025 69.72% 69.72% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::total 11510 # Number of insts issued each cycle 159system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 160system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available 161system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available 162system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available 163system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available 164system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available 165system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available 166system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available 189system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available 190system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available 191system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 192system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 193system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 194system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued 195system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued 196system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued 197system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued 198system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued 199system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued 200system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued 223system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued 224system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued 225system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 226system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 227system.cpu.iq.FU_type_0::total 8706 # Type of FU issued 228system.cpu.iq.rate 0.435213 # Inst issue rate 229system.cpu.iq.fu_busy_cnt 203 # FU busy when requested 230system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) 231system.cpu.iq.int_inst_queue_reads 29184 # Number of integer instruction queue reads 232system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes 233system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses 234system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 235system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 236system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 237system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses 238system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 239system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores 240system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 241system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed 242system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 243system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations 244system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed 245system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 246system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 247system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 248system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 249system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 250system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing 251system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking 252system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking 253system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ 254system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch 255system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions 256system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions 257system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 258system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 259system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 260system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations 261system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly 262system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly 263system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute 264system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions 265system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed 266system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute 267system.cpu.iew.exec_swp 0 # number of swp insts executed 268system.cpu.iew.exec_nop 1 # number of nop insts executed 269system.cpu.iew.exec_refs 3178 # number of memory reference insts executed 270system.cpu.iew.exec_branches 1354 # Number of branches executed 271system.cpu.iew.exec_stores 1169 # Number of stores executed 272system.cpu.iew.exec_rate 0.414017 # Inst execution rate 273system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit 274system.cpu.iew.wb_count 7840 # cumulative count of insts written-back 275system.cpu.iew.wb_producers 3690 # num instructions producing a value 276system.cpu.iew.wb_consumers 7291 # num instructions consuming a value 277system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 278system.cpu.iew.wb_rate 0.391922 # insts written-back per cycle 279system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back 280system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 281system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions 282system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit 283system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 284system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted 285system.cpu.commit.committed_per_cycle::samples 10624 # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::mean 0.540192 # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::stdev 1.352731 # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::0 8288 78.01% 78.01% # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::2 420 3.95% 92.21% # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::total 10624 # Number of insts commited each cycle 302system.cpu.commit.count 5739 # Number of instructions committed 303system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 304system.cpu.commit.refs 2139 # Number of memory references committed 305system.cpu.commit.loads 1201 # Number of loads committed 306system.cpu.commit.membars 12 # Number of memory barriers committed 307system.cpu.commit.branches 945 # Number of branches committed 308system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 309system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 310system.cpu.commit.function_calls 82 # Number of function calls committed. 311system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached 312system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 313system.cpu.rob.rob_reads 21207 # The number of ROB reads 314system.cpu.rob.rob_writes 22566 # The number of ROB writes 315system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself 316system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling 317system.cpu.committedInsts 5739 # Number of Instructions Simulated 318system.cpu.committedInsts_total 5739 # Number of Instructions Simulated 319system.cpu.cpi 3.485625 # CPI: Cycles Per Instruction 320system.cpu.cpi_total 3.485625 # CPI: Total CPI of All Threads 321system.cpu.ipc 0.286893 # IPC: Instructions Per Cycle 322system.cpu.ipc_total 0.286893 # IPC: Total IPC of All Threads 323system.cpu.int_regfile_reads 37816 # number of integer regfile reads 324system.cpu.int_regfile_writes 7658 # number of integer regfile writes 325system.cpu.fp_regfile_reads 16 # number of floating regfile reads 326system.cpu.misc_regfile_reads 14993 # number of misc regfile reads 327system.cpu.misc_regfile_writes 24 # number of misc regfile writes 328system.cpu.icache.replacements 2 # number of replacements 329system.cpu.icache.tagsinuse 148.864335 # Cycle average of tags in use 330system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. 331system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. 332system.cpu.icache.avg_refs 5.252525 # Average number of references to valid blocks. 333system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 334system.cpu.icache.occ_blocks::0 148.864335 # Average occupied blocks per context 335system.cpu.icache.occ_percent::0 0.072688 # Average percentage of cache occupancy 336system.cpu.icache.ReadReq_hits 1560 # number of ReadReq hits 337system.cpu.icache.demand_hits 1560 # number of demand (read+write) hits 338system.cpu.icache.overall_hits 1560 # number of overall hits 339system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses 340system.cpu.icache.demand_misses 360 # number of demand (read+write) misses 341system.cpu.icache.overall_misses 360 # number of overall misses 342system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles 343system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles 344system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles 345system.cpu.icache.ReadReq_accesses 1920 # number of ReadReq accesses(hits+misses) 346system.cpu.icache.demand_accesses 1920 # number of demand (read+write) accesses 347system.cpu.icache.overall_accesses 1920 # number of overall (read+write) accesses 348system.cpu.icache.ReadReq_miss_rate 0.187500 # miss rate for ReadReq accesses 349system.cpu.icache.demand_miss_rate 0.187500 # miss rate for demand accesses 350system.cpu.icache.overall_miss_rate 0.187500 # miss rate for overall accesses 351system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency 352system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency 353system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency 354system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 355system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 356system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 357system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 358system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 359system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 360system.cpu.icache.fast_writes 0 # number of fast writes performed 361system.cpu.icache.cache_copies 0 # number of cache copies performed 362system.cpu.icache.writebacks 0 # number of writebacks 363system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits 364system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits 365system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits 366system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses 367system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses 368system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses 369system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 370system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 374system.cpu.icache.ReadReq_mshr_miss_rate 0.154688 # mshr miss rate for ReadReq accesses 375system.cpu.icache.demand_mshr_miss_rate 0.154688 # mshr miss rate for demand accesses 376system.cpu.icache.overall_mshr_miss_rate 0.154688 # mshr miss rate for overall accesses 377system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency 378system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency 379system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency 380system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 381system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 382system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 383system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 384system.cpu.dcache.replacements 0 # number of replacements 385system.cpu.dcache.tagsinuse 89.089443 # Cycle average of tags in use 386system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. 387system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. 388system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. 389system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 390system.cpu.dcache.occ_blocks::0 89.089443 # Average occupied blocks per context 391system.cpu.dcache.occ_percent::0 0.021750 # Average percentage of cache occupancy 392system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits 393system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits 394system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits 395system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits 396system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits 397system.cpu.dcache.overall_hits 2311 # number of overall hits 398system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses 399system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses 400system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses 401system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses 402system.cpu.dcache.overall_misses 473 # number of overall misses 403system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles 404system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles 405system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles 406system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles 407system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles 408system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses) 409system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) 410system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) 411system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) 412system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses 413system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses 414system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses 415system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses 416system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses 417system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses 418system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses 419system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency 420system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency 421system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency 422system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency 424system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 430system.cpu.dcache.fast_writes 0 # number of fast writes performed 431system.cpu.dcache.cache_copies 0 # number of cache copies performed 432system.cpu.dcache.writebacks 0 # number of writebacks 433system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits 434system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits 435system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits 436system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits 437system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits 438system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses 440system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses 441system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses 442system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 443system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles 444system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles 445system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles 446system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles 447system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 448system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses 449system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses 450system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency 454system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency 455system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency 456system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 457system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 458system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 459system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 460system.cpu.l2cache.replacements 0 # number of replacements 461system.cpu.l2cache.tagsinuse 188.120549 # Cycle average of tags in use 462system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. 463system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. 464system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. 465system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 466system.cpu.l2cache.occ_blocks::0 188.120549 # Average occupied blocks per context 467system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy 468system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits 469system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits 470system.cpu.l2cache.overall_hits 42 # number of overall hits 471system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses 472system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses 473system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses 474system.cpu.l2cache.overall_misses 409 # number of overall misses 475system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles 476system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles 477system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles 478system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles 479system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) 480system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) 481system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses 482system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses 483system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses 484system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 485system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses 486system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses 487system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency 488system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency 489system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency 490system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency 491system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 492system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 493system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 495system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 496system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 497system.cpu.l2cache.fast_writes 0 # number of fast writes performed 498system.cpu.l2cache.cache_copies 0 # number of cache copies performed 499system.cpu.l2cache.writebacks 0 # number of writebacks 500system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits 501system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits 502system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits 503system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses 504system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses 505system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses 506system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses 507system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 508system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles 509system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles 510system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles 511system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles 512system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 513system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses 514system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 515system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses 516system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses 517system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency 518system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency 519system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency 520system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency 521system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 522system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 523system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 524system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 525 526---------- End Simulation Statistics ---------- 527