stats.txt revision 9378
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49348SAli.Saidi@ARM.comsim_ticks 13371000 # Number of ticks simulated 59348SAli.Saidi@ARM.comfinal_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79378Snilay@cs.wisc.eduhost_inst_rate 36978 # Simulator instruction rate (inst/s) 89378Snilay@cs.wisc.eduhost_op_rate 46127 # Simulator op (including micro ops) rate (op/s) 99378Snilay@cs.wisc.eduhost_tick_rate 107546339 # Simulator tick rate (ticks/s) 109378Snilay@cs.wisc.eduhost_mem_usage 272728 # Number of bytes of host memory used 119348SAli.Saidi@ARM.comhost_seconds 0.12 # Real time elapsed on the host 129265SAli.Saidi@ARM.comsim_insts 4596 # Number of instructions simulated 139265SAli.Saidi@ARM.comsim_ops 5734 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 159312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 25216 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 209312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 219348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 394 # Number of read requests responded to by this memory 229348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) 239348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) 249348SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) 259348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) 269348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) 279348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) 289348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) 299348SAli.Saidi@ARM.comsystem.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.readReqs 394 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329348SAli.Saidi@ARM.comsystem.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 339348SAli.Saidi@ARM.comsystem.physmem.bytesRead 25216 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis 409348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis 419348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis 429348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis 439322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis 449348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis 479312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis 489312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 16 # Track reads on a per bank basis 499312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis 539348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739348SAli.Saidi@ARM.comsystem.physmem.totGap 13312500 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 394 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see 1029322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 1039348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 1049348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 1059348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 1069348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 1079348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.totQLat 2460894 # Total cycles spent in queuing delays 1689348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 1699348SAli.Saidi@ARM.comsystem.physmem.totBusLat 1576000 # Total cycles spent in databus access 1709348SAli.Saidi@ARM.comsystem.physmem.totBankLat 6524000 # Total cycles spent in bank access 1719348SAli.Saidi@ARM.comsystem.physmem.avgQLat 6245.92 # Average queueing delay per request 1729348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 16558.38 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 26804.30 # Average memory access latency 1759348SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779348SAli.Saidi@ARM.comsystem.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809348SAli.Saidi@ARM.comsystem.physmem.busUtil 11.79 # Data bus utilization in percentage 1819348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.79 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839348SAli.Saidi@ARM.comsystem.physmem.readRowHits 319 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879348SAli.Saidi@ARM.comsystem.physmem.avgGap 33788.07 # Average gap between requests 1888317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 1898317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 1908317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 1918317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 1928317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 1938317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 1947860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 1957860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1967860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1978317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1988317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 1998317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2008317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2018317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2028317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2038317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2048317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2058317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2067860SN/Asystem.cpu.dtb.hits 0 # DTB hits 2077860SN/Asystem.cpu.dtb.misses 0 # DTB misses 2088317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2098317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 2108317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 2118317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2128317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2138317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2148317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2158317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 2168317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2178317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2188317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2198317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2208317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2218317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2228317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2238317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2248317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2258317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2268317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 2278317SN/Asystem.cpu.itb.hits 0 # DTB hits 2288317SN/Asystem.cpu.itb.misses 0 # DTB misses 2298317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2308317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 2319348SAli.Saidi@ARM.comsystem.cpu.numCycles 26743 # number of cpu cycles simulated 2328317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2338317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2349348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2505 # Number of BP lookups 2359348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted 2369348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect 2379322Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups 2389348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 707 # Number of BTB hits 2398317SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2409348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. 2419348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. 2429348SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss 2439348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 12026 # Number of instructions fetch has processed 2449348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 2459348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken 2469348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked 2479348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing 2489348SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked 2499079SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2509348SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 1960 # Number of cache lines fetched 2519348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 2529348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) 2539348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) 2549348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) 2557860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2569348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) 2579348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) 2589348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) 2599348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) 2609348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) 2619348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) 2629348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) 2639348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) 2649348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) 2657860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2667860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2677860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2689348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) 2699348SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle 2709348SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle 2719348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle 2729348SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked 2739348SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2446 # Number of cycles decode is running 2749348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 2759348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 2769348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch 2779348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 2789348SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode 2799348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 2809348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 2819348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle 2829348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 2839348SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst 2849348SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2247 # Number of cycles rename is running 2859348SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 2869348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename 2879348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 2889348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 2899348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 2909348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed 2919348SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made 2929348SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups 2939348SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 2949265SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 2959348SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing 2969348SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 44 # count of serializing insts renamed 2979348SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 2989348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 683 # count of insts added to the skid buffer 2999348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. 3009348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. 3019348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. 3029348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 3039348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) 3049348SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 3059348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 3069348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 3079348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling 3089348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph 3099348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed 3109348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle 3119348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle 3129348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle 3138241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3149348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle 3159348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle 3169348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle 3179348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle 3189348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle 3199348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle 3209348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle 3219348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 3229348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 3238241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3248241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3258241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3269348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle 3278317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3289348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 3299348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 3309348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 3319348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3329348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3339348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3349348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available 3359348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3369348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 3379348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available 3389348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available 3399348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available 3409348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available 3419348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available 3429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available 3439348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available 3449348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available 3459348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available 3469348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available 3479348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available 3489348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available 3499348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available 3509348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available 3519348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available 3529348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available 3539348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available 3549348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available 3559348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available 3569348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available 3579348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available 3589348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available 3598317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3608317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3618317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3629348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued 3639348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued 3649348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued 3659348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued 3669348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued 3679348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued 3689348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued 3699348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued 3709348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued 3719348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued 3729348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued 3739348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued 3749348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued 3759348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued 3769348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued 3779348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued 3789348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued 3799348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued 3809348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued 3819348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued 3829348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued 3839348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued 3849348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued 3859348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued 3869348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued 3879348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued 3889348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued 3899348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued 3909348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued 3919348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued 3929348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued 3938317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3948317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3959348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 8988 # Type of FU issued 3969348SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.336088 # Inst issue rate 3979348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 228 # FU busy when requested 3989348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) 3999348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads 4009348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes 4019348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses 4028632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 4039322Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 4048317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 4059348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 4068632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 4079348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores 4088317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4099348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed 4109312Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 4119348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 4129348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed 4138317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4148317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4158632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 4169348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 4178317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4189348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 4199348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 4209348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 4219348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ 4229348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch 4239348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions 4249348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions 4259348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 4269348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 4279285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4289348SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 4299348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 4309348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 4319348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute 4329348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions 4339348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 4349348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute 4358317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4369348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 4379348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3300 # number of memory reference insts executed 4389348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1446 # Number of branches executed 4399348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1164 # Number of stores executed 4409348SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.320233 # Inst execution rate 4419348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit 4429348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 8109 # cumulative count of insts written-back 4439348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 3899 # num instructions producing a value 4449348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 7837 # num instructions consuming a value 4458317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4469348SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.303220 # insts written-back per cycle 4479348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back 4488317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4499348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit 4509265SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 4519348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 4529348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle 4539348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle 4549348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle 4558317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4569348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle 4579348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle 4589348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle 4599348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle 4609348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle 4619348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle 4629348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle 4639348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle 4649348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle 4658317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4668317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4678317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4689348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle 4699265SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4596 # Number of instructions committed 4709265SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 4718317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4729265SAli.Saidi@ARM.comsystem.cpu.commit.refs 2140 # Number of memory references committed 4739265SAli.Saidi@ARM.comsystem.cpu.commit.loads 1201 # Number of loads committed 4748317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 4759265SAli.Saidi@ARM.comsystem.cpu.commit.branches 1008 # Number of branches committed 4768317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 4779265SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4980 # Number of committed integer instructions. 4788317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 4799348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 4808317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4819348SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 22988 # The number of ROB reads 4829348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 23599 # The number of ROB writes 4839348SAli.Saidi@ARM.comsystem.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself 4849348SAli.Saidi@ARM.comsystem.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling 4859265SAli.Saidi@ARM.comsystem.cpu.committedInsts 4596 # Number of Instructions Simulated 4869265SAli.Saidi@ARM.comsystem.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 4879265SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4596 # Number of Instructions Simulated 4889348SAli.Saidi@ARM.comsystem.cpu.cpi 5.818755 # CPI: Cycles Per Instruction 4899348SAli.Saidi@ARM.comsystem.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads 4909348SAli.Saidi@ARM.comsystem.cpu.ipc 0.171858 # IPC: Instructions Per Cycle 4919348SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads 4929348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 39369 # number of integer regfile reads 4939348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 8027 # number of integer regfile writes 4948632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 4959378Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 2981 # number of misc regfile reads 4969265SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 26 # number of misc regfile writes 4979312Sandreas.hansson@arm.comsystem.cpu.icache.replacements 4 # number of replacements 4989348SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use 4999348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1601 # Total number of references to valid blocks. 5009348SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. 5019348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. 5028317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5039348SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor 5049348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy 5059348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy 5069348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 5079348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 5089348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 5099348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 5109348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 5119348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1601 # number of overall hits 5129348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 5139348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 5149348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 5159348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 5169348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 5179348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 359 # number of overall misses 5189348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles 5199348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles 5209348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles 5219348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles 5229348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles 5239348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles 5249348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) 5259348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) 5269348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses 5279348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses 5289348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses 5299348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses 5309348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses 5319348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses 5329348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses 5339348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses 5349348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses 5359348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses 5369348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency 5379348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency 5389348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency 5399348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency 5409348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency 5419348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency 5429322Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 5438317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5449322Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 5458317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5469322Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 5478983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5488317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5498317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5509348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits 5519348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits 5529348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits 5539348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits 5549348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits 5559348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits 5569348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses 5579348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses 5589348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses 5599348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses 5609348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses 5619348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses 5629348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles 5639348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles 5649348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles 5659348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles 5669348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles 5679348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles 5689348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses 5699348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses 5709348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses 5719348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses 5729348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses 5739348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses 5749348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency 5759348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency 5769348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency 5779348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency 5789348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency 5799348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency 5808317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5819378Snilay@cs.wisc.edusystem.cpu.dcache.replacements 0 # number of replacements 5829378Snilay@cs.wisc.edusystem.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use 5839378Snilay@cs.wisc.edusystem.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. 5849378Snilay@cs.wisc.edusystem.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 5859378Snilay@cs.wisc.edusystem.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. 5869378Snilay@cs.wisc.edusystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5879378Snilay@cs.wisc.edusystem.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor 5889378Snilay@cs.wisc.edusystem.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy 5899378Snilay@cs.wisc.edusystem.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy 5909378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits 5919378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits 5929378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 5939378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 5949378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 5959378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 5969378Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 5979378Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 5989378Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits 5999378Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits 6009378Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits 6019378Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 2371 # number of overall hits 6029378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses 6039378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses 6049378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 6059378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 6069378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 6079378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 6089378Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 6099378Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 6109378Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 6119378Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 498 # number of overall misses 6129378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles 6139378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles 6149378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 6159378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 6169378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 6179378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 6189378Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles 6199378Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles 6209378Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles 6219378Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles 6229378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 6239378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 6249378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 6259378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 6269378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 6279378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 6289378Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 6299378Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 6309378Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 6319378Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 6329378Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 6339378Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 6349378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses 6359378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses 6369378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 6379378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 6389378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 6399378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 6409378Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses 6419378Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses 6429378Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses 6439378Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses 6449378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency 6459378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency 6469378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 6479378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 6489378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 6499378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 6509378Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency 6519378Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency 6529378Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency 6539378Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency 6549378Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 6559378Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6569378Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 6579378Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 6589378Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 6599378Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6609378Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 6619378Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 6629378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits 6639378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits 6649378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 6659378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 6669378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 6679378Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 6689378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 6699378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 6709378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 6719378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits 6729378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 6739378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 6749378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 6759378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 6769378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 6779378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 6789378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 6799378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 6809378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles 6819378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles 6829378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 6839378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles 6849378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles 6859378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles 6869378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles 6879378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles 6889378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 6899378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 6909378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 6919378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 6929378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 6939378Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 6949378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 6959378Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 6969378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency 6979378Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency 6989378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 6999378Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency 7009378Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency 7019378Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency 7029378Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency 7039378Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency 7049378Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7058317SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 7069348SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use 7079348SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 7089348SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 7099348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. 7108317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7119348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor 7129348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor 7139348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy 7149348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy 7159322Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy 7169322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 7179348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 7189348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 7199322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 7209348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 7219348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 7229322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 7239348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 7249348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 40 # number of overall hits 7259348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 7269348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 7279348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 7289348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 7299348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 7309348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 7319322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 7329348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 7339348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 7349322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 7359348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 399 # number of overall misses 7369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles 7379348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles 7389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles 7399348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 7409348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 7419348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles 7429348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles 7439348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles 7449348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles 7459348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles 7469348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles 7479348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) 7489322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 7499348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 7509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 7519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 7529348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses 7539348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 7549348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 7559348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses 7569348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 7579348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 7589348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses 7599348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 7609348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses 7618835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7629055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 7639348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses 7649348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 7659348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses 7669348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses 7679348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 7689348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses 7699348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency 7709348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency 7719348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency 7729348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 7739348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 7749348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency 7759348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency 7769348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency 7779348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency 7789348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency 7799348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency 7808317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7818317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7828317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7838317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7848983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7858983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7868317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7877860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7889348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 7899348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 7909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 7919348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 7929348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 7939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 7949348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 7959322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 7969348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 7979348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 7989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 7999348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 8009348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 8019348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 8029348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 8039348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 8049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 8059348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles 8069348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles 8079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles 8089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 8099348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 8109348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles 8119348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles 8129348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles 8139348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles 8149348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles 8159348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles 8169348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses 8179322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 8189348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses 8198835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8209055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 8219348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses 8229348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 8239348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses 8249348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses 8259348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 8269348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses 8279348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency 8289348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency 8299348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency 8309348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 8319348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 8329348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency 8339348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency 8349348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency 8359348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency 8369348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency 8379348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency 8387860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8397860SN/A 8407860SN/A---------- End Simulation Statistics ---------- 841