stats.txt revision 9285
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000010 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 10412000 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 10412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79285Sandreas.hansson@arm.comhost_inst_rate 40558 # Simulator instruction rate (inst/s) 89285Sandreas.hansson@arm.comhost_op_rate 50593 # Simulator op (including micro ops) rate (op/s) 99285Sandreas.hansson@arm.comhost_tick_rate 91854675 # Simulator tick rate (ticks/s) 109285Sandreas.hansson@arm.comhost_mem_usage 232720 # Number of bytes of host memory used 119285Sandreas.hansson@arm.comhost_seconds 0.11 # Real time elapsed on the host 129265SAli.Saidi@ARM.comsim_insts 4596 # Number of instructions simulated 139265SAli.Saidi@ARM.comsim_ops 5734 # Number of ops (including micro ops) simulated 149285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory 159285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory 169285Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 25600 # Number of bytes read from this memory 179285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory 189285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory 199285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory 209285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory 219285Sandreas.hansson@arm.comsystem.physmem.num_reads::total 400 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1702650788 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 756050711 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2458701498 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1702650788 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1702650788 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1702650788 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 756050711 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2458701498 # Total bandwidth to/from this memory (bytes/s) 308317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 318317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 328317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 338317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 348317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 358317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 367860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 377860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 387860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 398317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 418317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 428317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 438317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 448317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 468317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 478317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 487860SN/Asystem.cpu.dtb.hits 0 # DTB hits 497860SN/Asystem.cpu.dtb.misses 0 # DTB misses 508317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 518317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 528317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 538317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 548317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 558317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 568317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 578317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 588317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 608317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 618317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 628317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 638317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 648317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 658317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 668317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 678317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 688317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 698317SN/Asystem.cpu.itb.hits 0 # DTB hits 708317SN/Asystem.cpu.itb.misses 0 # DTB misses 718317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 728317SN/Asystem.cpu.workload.num_syscalls 13 # Number of system calls 739285Sandreas.hansson@arm.comsystem.cpu.numCycles 20825 # number of cpu cycles simulated 748317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 758317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 769285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2492 # Number of BP lookups 779285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1785 # Number of conditional branches predicted 789285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 490 # Number of conditional branches incorrect 799285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 1982 # Number of BTB lookups 809285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 699 # Number of BTB hits 818317SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 829285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 261 # Number of times the RAS was used to get a target. 839265SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. 849285Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 6546 # Number of cycles fetch is stalled on an Icache miss 859285Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 12176 # Number of instructions fetch has processed 869285Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2492 # Number of branches that fetch encountered 879285Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 960 # Number of branches that fetch has predicted taken 889285Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked 899285Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1597 # Number of cycles fetch has spent squashing 909285Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 2014 # Number of cycles fetch has spent blocked 919079SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 929285Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 1932 # Number of cache lines fetched 939285Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed 949285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 12289 # Number of instructions fetched each cycle (Total) 959285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.242575 # Number of instructions fetched each cycle (Total) 969285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.647072 # Number of instructions fetched each cycle (Total) 977860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 989285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 9645 78.48% 78.48% # Number of instructions fetched each cycle (Total) 999285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 219 1.78% 80.27% # Number of instructions fetched each cycle (Total) 1009285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 197 1.60% 81.87% # Number of instructions fetched each cycle (Total) 1019285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 227 1.85% 83.72% # Number of instructions fetched each cycle (Total) 1029285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 211 1.72% 85.43% # Number of instructions fetched each cycle (Total) 1039285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 285 2.32% 87.75% # Number of instructions fetched each cycle (Total) 1049285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 100 0.81% 88.57% # Number of instructions fetched each cycle (Total) 1059285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 133 1.08% 89.65% # Number of instructions fetched each cycle (Total) 1069285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1272 10.35% 100.00% # Number of instructions fetched each cycle (Total) 1077860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1087860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1097860SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1109285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 12289 # Number of instructions fetched each cycle (Total) 1119285Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.119664 # Number of branch fetches per cycle 1129285Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.584682 # Number of inst fetches per cycle 1139285Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 6694 # Number of cycles decode is idle 1149285Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2170 # Number of cycles decode is blocked 1159285Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2432 # Number of cycles decode is running 1169285Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 67 # Number of cycles decode is unblocking 1179285Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 926 # Number of cycles decode is squashing 1189285Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 377 # Number of times decode resolved a branch 1199096Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 1209285Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 13288 # Number of instructions handled by decode 1219285Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 560 # Number of squashed instructions handled by decode 1229285Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 926 # Number of cycles rename is squashing 1239285Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 6959 # Number of cycles rename is idle 1249285Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking 1259285Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 1561 # count of cycles rename stalled for serializing inst 1269285Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2229 # Number of cycles rename is running 1279285Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 222 # Number of cycles rename is unblocking 1289285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 12442 # Number of instructions processed by rename 1299285Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full 1309285Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 182 # Number of times rename has blocked due to LSQ full 1319285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 12452 # Number of destination operands rename has renamed 1329285Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 56629 # Number of register rename lookups that rename has made 1339285Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 56357 # Number of integer rename lookups 1349265SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups 1359265SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed 1369285Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6771 # Number of HB maps that are undone due to squashing 1379285Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 47 # count of serializing insts renamed 1389285Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed 1399285Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 672 # count of insts added to the skid buffer 1409285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2727 # Number of loads inserted to the mem dependence unit. 1419285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1576 # Number of stores inserted to the mem dependence unit. 1429285Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 42 # Number of conflicting loads. 1439285Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. 1449285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 11136 # Number of instructions added to the IQ (excludes non-spec) 1459265SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ 1469285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 8838 # Number of instructions issued 1479285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 1489285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5149 # Number of squashed instructions iterated over during squash; mainly for profiling 1499285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 14358 # Number of squashed operands that are examined and possibly removed from graph 1509265SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 1519285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 12289 # Number of insts issued each cycle 1529285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.719180 # Number of insts issued each cycle 1539285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.401668 # Number of insts issued each cycle 1548241SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1559285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 8691 70.72% 70.72% # Number of insts issued each cycle 1569285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1369 11.14% 81.86% # Number of insts issued each cycle 1579285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 785 6.39% 88.25% # Number of insts issued each cycle 1589285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 562 4.57% 92.82% # Number of insts issued each cycle 1599285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 445 3.62% 96.44% # Number of insts issued each cycle 1609285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 257 2.09% 98.54% # Number of insts issued each cycle 1619285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 123 1.00% 99.54% # Number of insts issued each cycle 1629285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 46 0.37% 99.91% # Number of insts issued each cycle 1639285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle 1648241SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1658241SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1668241SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1679285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 12289 # Number of insts issued each cycle 1688317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1699285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 4 1.81% 1.81% # attempts to use FU when none available 1709285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 1.81% # attempts to use FU when none available 1719285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 1.81% # attempts to use FU when none available 1729285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 1.81% # attempts to use FU when none available 1739285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 1.81% # attempts to use FU when none available 1749285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 1.81% # attempts to use FU when none available 1759285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 1.81% # attempts to use FU when none available 1769285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 1.81% # attempts to use FU when none available 1779285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 1789285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 1.81% # attempts to use FU when none available 1799285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.81% # attempts to use FU when none available 1809285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 1.81% # attempts to use FU when none available 1819285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 1.81% # attempts to use FU when none available 1829285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 1.81% # attempts to use FU when none available 1839285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 1.81% # attempts to use FU when none available 1849285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 1.81% # attempts to use FU when none available 1859285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.81% # attempts to use FU when none available 1869285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 1.81% # attempts to use FU when none available 1879285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.81% # attempts to use FU when none available 1889285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.81% # attempts to use FU when none available 1899285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.81% # attempts to use FU when none available 1909285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.81% # attempts to use FU when none available 1919285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.81% # attempts to use FU when none available 1929285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.81% # attempts to use FU when none available 1939285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.81% # attempts to use FU when none available 1949285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.81% # attempts to use FU when none available 1959285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.81% # attempts to use FU when none available 1969285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.81% # attempts to use FU when none available 1979285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.81% # attempts to use FU when none available 1989285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 143 64.71% 66.52% # attempts to use FU when none available 1999285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 74 33.48% 100.00% # attempts to use FU when none available 2008317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2018317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2028317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 2039285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 5335 60.36% 60.36% # Type of FU issued 2049285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 8 0.09% 60.45% # Type of FU issued 2059285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued 2069285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued 2079285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued 2089285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued 2099285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued 2109285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued 2119285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued 2129285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued 2139285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued 2149285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued 2159285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued 2169285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued 2179285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued 2189285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued 2199285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued 2209285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued 2219285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued 2229285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued 2239285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued 2249285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued 2259285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued 2269285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued 2279285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued 2289285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued 2299285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued 2309285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued 2319285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued 2329285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2273 25.72% 86.21% # Type of FU issued 2339285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1219 13.79% 100.00% # Type of FU issued 2348317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2358317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2369285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 8838 # Type of FU issued 2379285Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.424394 # Inst issue rate 2389285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 221 # FU busy when requested 2399285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.025006 # FU busy rate (busy events/executed inst) 2409285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 30263 # Number of integer instruction queue reads 2419285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 16340 # Number of integer instruction queue writes 2429285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 7981 # Number of integer instruction queue wakeup accesses 2438632SN/Asystem.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 2449265SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 2458317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 2469285Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 9039 # Number of integer alu accesses 2478632SN/Asystem.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 2489285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores 2498317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2509285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1526 # Number of loads squashed 2519285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed 2528844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2539285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 637 # Number of stores squashed 2548317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2558317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2568632SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 2578317SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2588317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2599285Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 926 # Number of cycles IEW is squashing 2609285Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 243 # Number of cycles IEW is blocking 2619285Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking 2629285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 11191 # Number of instructions dispatched to IQ 2639285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch 2649285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2727 # Number of dispatched load instructions 2659285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1576 # Number of dispatched store instructions 2669265SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions 2679285Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall 2689285Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2698844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2709285Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 2719285Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 282 # Number of branches that were predicted not taken incorrectly 2729285Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute 2739285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 8434 # Number of executed instructions 2749285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2079 # Number of load instructions executed 2759285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute 2768317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2779079SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 2789285Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3246 # number of memory reference insts executed 2799285Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1415 # Number of branches executed 2809285Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1167 # Number of stores executed 2819285Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.404994 # Inst execution rate 2829285Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 8148 # cumulative count of insts sent to commit 2839285Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 7997 # cumulative count of insts written-back 2849285Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 3850 # num instructions producing a value 2859285Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7766 # num instructions consuming a value 2868317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2879285Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.384010 # insts written-back per cycle 2889285Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.495751 # average fanout of values written-back 2898317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2909285Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 5462 # The number of squashed insts skipped by commit 2919265SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 2929285Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 2939285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 11364 # Number of insts commited each cycle 2949285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.504576 # Number of insts commited each cycle 2959285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.339059 # Number of insts commited each cycle 2968317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2979285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 9062 79.74% 79.74% # Number of insts commited each cycle 2989285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1091 9.60% 89.34% # Number of insts commited each cycle 2999285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 395 3.48% 92.82% # Number of insts commited each cycle 3009285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 263 2.31% 95.13% # Number of insts commited each cycle 3019285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 177 1.56% 96.69% # Number of insts commited each cycle 3029285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 168 1.48% 98.17% # Number of insts commited each cycle 3039285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 53 0.47% 98.64% # Number of insts commited each cycle 3049285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 42 0.37% 99.01% # Number of insts commited each cycle 3059285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 113 0.99% 100.00% # Number of insts commited each cycle 3068317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3078317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3088317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3099285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 11364 # Number of insts commited each cycle 3109265SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 4596 # Number of instructions committed 3119265SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed 3128317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3139265SAli.Saidi@ARM.comsystem.cpu.commit.refs 2140 # Number of memory references committed 3149265SAli.Saidi@ARM.comsystem.cpu.commit.loads 1201 # Number of loads committed 3158317SN/Asystem.cpu.commit.membars 12 # Number of memory barriers committed 3169265SAli.Saidi@ARM.comsystem.cpu.commit.branches 1008 # Number of branches committed 3178317SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 3189265SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 4980 # Number of committed integer instructions. 3198317SN/Asystem.cpu.commit.function_calls 82 # Number of function calls committed. 3209285Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached 3218317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3229285Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 22290 # The number of ROB reads 3239285Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 23328 # The number of ROB writes 3249285Sandreas.hansson@arm.comsystem.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself 3259285Sandreas.hansson@arm.comsystem.cpu.idleCycles 8536 # Total number of cycles that the CPU has spent unscheduled due to idling 3269265SAli.Saidi@ARM.comsystem.cpu.committedInsts 4596 # Number of Instructions Simulated 3279265SAli.Saidi@ARM.comsystem.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 3289265SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 4596 # Number of Instructions Simulated 3299285Sandreas.hansson@arm.comsystem.cpu.cpi 4.531114 # CPI: Cycles Per Instruction 3309285Sandreas.hansson@arm.comsystem.cpu.cpi_total 4.531114 # CPI: Total CPI of All Threads 3319285Sandreas.hansson@arm.comsystem.cpu.ipc 0.220696 # IPC: Instructions Per Cycle 3329285Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.220696 # IPC: Total IPC of All Threads 3339285Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 38756 # number of integer regfile reads 3349285Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7886 # number of integer regfile writes 3358632SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 3369285Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 15116 # number of misc regfile reads 3379265SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 26 # number of misc regfile writes 3389285Sandreas.hansson@arm.comsystem.cpu.icache.replacements 3 # number of replacements 3399285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 150.292417 # Cycle average of tags in use 3409285Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1564 # Total number of references to valid blocks. 3419285Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 3429285Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 5.283784 # Average number of references to valid blocks. 3438317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3449285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 150.292417 # Average occupied blocks per requestor 3459285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.073385 # Average percentage of cache occupancy 3469285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.073385 # Average percentage of cache occupancy 3479285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1564 # number of ReadReq hits 3489285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1564 # number of ReadReq hits 3499285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1564 # number of demand (read+write) hits 3509285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1564 # number of demand (read+write) hits 3519285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1564 # number of overall hits 3529285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1564 # number of overall hits 3539285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses 3549285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses 3559285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses 3569285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses 3579285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses 3589285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 368 # number of overall misses 3599285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 12876500 # number of ReadReq miss cycles 3609285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 12876500 # number of ReadReq miss cycles 3619285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 12876500 # number of demand (read+write) miss cycles 3629285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 12876500 # number of demand (read+write) miss cycles 3639285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 12876500 # number of overall miss cycles 3649285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 12876500 # number of overall miss cycles 3659285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 1932 # number of ReadReq accesses(hits+misses) 3669285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 1932 # number of ReadReq accesses(hits+misses) 3679285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 1932 # number of demand (read+write) accesses 3689285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 1932 # number of demand (read+write) accesses 3699285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 1932 # number of overall (read+write) accesses 3709285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 1932 # number of overall (read+write) accesses 3719285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.190476 # miss rate for ReadReq accesses 3729285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.190476 # miss rate for ReadReq accesses 3739285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.190476 # miss rate for demand accesses 3749285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.190476 # miss rate for demand accesses 3759285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.190476 # miss rate for overall accesses 3769285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.190476 # miss rate for overall accesses 3779285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34990.489130 # average ReadReq miss latency 3789285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 34990.489130 # average ReadReq miss latency 3799285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 3809285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 34990.489130 # average overall miss latency 3819285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 34990.489130 # average overall miss latency 3829285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 34990.489130 # average overall miss latency 3838317SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3848317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3858317SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3868317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3878983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3888983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3898317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3908317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3919285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 72 # number of ReadReq MSHR hits 3929285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 3939285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 72 # number of demand (read+write) MSHR hits 3949285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 3959285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 72 # number of overall MSHR hits 3969285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 72 # number of overall MSHR hits 3979285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 3989285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 3999285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 4009285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 4019285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 4029285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 4039285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10420500 # number of ReadReq MSHR miss cycles 4049285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 10420500 # number of ReadReq MSHR miss cycles 4059285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 10420500 # number of demand (read+write) MSHR miss cycles 4069285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 10420500 # number of demand (read+write) MSHR miss cycles 4079285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 10420500 # number of overall MSHR miss cycles 4089285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 10420500 # number of overall MSHR miss cycles 4099285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for ReadReq accesses 4109285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.153209 # mshr miss rate for ReadReq accesses 4119285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for demand accesses 4129285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.153209 # mshr miss rate for demand accesses 4139285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153209 # mshr miss rate for overall accesses 4149285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.153209 # mshr miss rate for overall accesses 4159285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35204.391892 # average ReadReq mshr miss latency 4169285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35204.391892 # average ReadReq mshr miss latency 4179285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 4189285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 4199285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35204.391892 # average overall mshr miss latency 4209285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 35204.391892 # average overall mshr miss latency 4218317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4228317SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4239285Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 86.816564 # Cycle average of tags in use 4249285Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. 4259285Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. 4269285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 15.857143 # Average number of references to valid blocks. 4278317SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4289285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 86.816564 # Average occupied blocks per requestor 4299285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.021195 # Average percentage of cache occupancy 4309285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.021195 # Average percentage of cache occupancy 4319285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1709 # number of ReadReq hits 4329285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1709 # number of ReadReq hits 4339285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits 4349285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits 4359265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 4369265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 4379265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 4389265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits 4399285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2306 # number of demand (read+write) hits 4409285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2306 # number of demand (read+write) hits 4419285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2306 # number of overall hits 4429285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2306 # number of overall hits 4439285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses 4449285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses 4459285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses 4469285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses 4478835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 4488835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 4499265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses 4509265SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses 4519265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses 4529265SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 502 # number of overall misses 4539285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 6202500 # number of ReadReq miss cycles 4549285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 6202500 # number of ReadReq miss cycles 4559285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 11056500 # number of WriteReq miss cycles 4569285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 11056500 # number of WriteReq miss cycles 4579285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 75000 # number of LoadLockedReq miss cycles 4589285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 75000 # number of LoadLockedReq miss cycles 4599285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 17259000 # number of demand (read+write) miss cycles 4609285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 17259000 # number of demand (read+write) miss cycles 4619285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 17259000 # number of overall miss cycles 4629285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 17259000 # number of overall miss cycles 4639285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) 4649285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) 4658835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 4668835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 4679265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 4689265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 4699265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 4709265SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) 4719285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2808 # number of demand (read+write) accesses 4729285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2808 # number of demand (read+write) accesses 4739285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2808 # number of overall (read+write) accesses 4749285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2808 # number of overall (read+write) accesses 4759285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098153 # miss rate for ReadReq accesses 4769285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.098153 # miss rate for ReadReq accesses 4779285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses 4789285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses 4799265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 4809265SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 4819285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.178775 # miss rate for demand accesses 4829285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses 4839285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.178775 # miss rate for overall accesses 4849285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses 4859285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33346.774194 # average ReadReq miss latency 4869285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 33346.774194 # average ReadReq miss latency 4879285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34988.924051 # average WriteReq miss latency 4889285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 34988.924051 # average WriteReq miss latency 4899285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37500 # average LoadLockedReq miss latency 4909285Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37500 # average LoadLockedReq miss latency 4919285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 4929285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 34380.478088 # average overall miss latency 4939285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34380.478088 # average overall miss latency 4949285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 34380.478088 # average overall miss latency 4958317SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4968317SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4978317SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4988317SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4998983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5008983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5018317SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 5028317SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 5039285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 5049285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 5059285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 5069285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits 5078835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 5088835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 5099285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 5109285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 5119285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 5129285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 5139285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 5149285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 5158835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 5168835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 5179285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 5189285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 5199285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 5209285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 5219285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3549000 # number of ReadReq MSHR miss cycles 5229285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3549000 # number of ReadReq MSHR miss cycles 5239285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1700000 # number of WriteReq MSHR miss cycles 5249285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1700000 # number of WriteReq MSHR miss cycles 5259285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 5249000 # number of demand (read+write) MSHR miss cycles 5269285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 5249000 # number of demand (read+write) MSHR miss cycles 5279285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 5249000 # number of overall MSHR miss cycles 5289285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 5249000 # number of overall MSHR miss cycles 5299285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055409 # mshr miss rate for ReadReq accesses 5309285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055409 # mshr miss rate for ReadReq accesses 5318835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 5329055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 5339285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for demand accesses 5349285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.052350 # mshr miss rate for demand accesses 5359285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052350 # mshr miss rate for overall accesses 5369285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.052350 # mshr miss rate for overall accesses 5379285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33800 # average ReadReq mshr miss latency 5389285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33800 # average ReadReq mshr miss latency 5399285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40476.190476 # average WriteReq mshr miss latency 5409285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40476.190476 # average WriteReq mshr miss latency 5419285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 5429285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 5439285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35707.482993 # average overall mshr miss latency 5449285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 35707.482993 # average overall mshr miss latency 5458317SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5468317SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5479285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 188.003042 # Cycle average of tags in use 5489285Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. 5499285Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. 5509285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.103352 # Average number of references to valid blocks. 5518317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5529285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 141.702568 # Average occupied blocks per requestor 5539285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 46.300474 # Average occupied blocks per requestor 5549285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004324 # Average percentage of cache occupancy 5559285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001413 # Average percentage of cache occupancy 5569285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.005737 # Average percentage of cache occupancy 5579285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 5589265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 5599285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 5609285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 5619265SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 5629285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 5639285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 5649265SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 5659285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 37 # number of overall hits 5669285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 5679285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 5689285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 364 # number of ReadReq misses 5698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 5708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 5719285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 5729285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 5739285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 406 # number of demand (read+write) misses 5749285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses 5759285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 5769285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 406 # number of overall misses 5779285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10097000 # number of ReadReq miss cycles 5789285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3413000 # number of ReadReq miss cycles 5799285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 13510000 # number of ReadReq miss cycles 5809285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1657000 # number of ReadExReq miss cycles 5819285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1657000 # number of ReadExReq miss cycles 5829285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 10097000 # number of demand (read+write) miss cycles 5839285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 5070000 # number of demand (read+write) miss cycles 5849285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 15167000 # number of demand (read+write) miss cycles 5859285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 10097000 # number of overall miss cycles 5869285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 5070000 # number of overall miss cycles 5879285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 15167000 # number of overall miss cycles 5889285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 5899285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 5909285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 5918835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 5928835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 5939285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 5949285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 5959285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses 5969285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 5979285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 5989285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses 5999285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942568 # miss rate for ReadReq accesses 6009285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 6019285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.907731 # miss rate for ReadReq accesses 6028835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6039055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6049285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.942568 # miss rate for demand accesses 6059285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 6069285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.916479 # miss rate for demand accesses 6079285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.942568 # miss rate for overall accesses 6089285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 6099285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.916479 # miss rate for overall accesses 6109285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36189.964158 # average ReadReq miss latency 6119285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40152.941176 # average ReadReq miss latency 6129285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 37115.384615 # average ReadReq miss latency 6139285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39452.380952 # average ReadExReq miss latency 6149285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 39452.380952 # average ReadExReq miss latency 6159285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 6169285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 6179285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37357.142857 # average overall miss latency 6189285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36189.964158 # average overall miss latency 6199285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 39921.259843 # average overall miss latency 6209285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37357.142857 # average overall miss latency 6218317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6228317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6238317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6248317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6258983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6268983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6278317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6287860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6299096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 6308844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 6319096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 6329096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 6338844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 6349096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 6359096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 6368844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 6379096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 6389285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 277 # number of ReadReq MSHR misses 6399285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 6409285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses 6418835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 6428835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 6439285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses 6449285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses 6459285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses 6469285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses 6479285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses 6489285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses 6499285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9207000 # number of ReadReq MSHR miss cycles 6509285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036500 # number of ReadReq MSHR miss cycles 6519285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 12243500 # number of ReadReq MSHR miss cycles 6529265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles 6539265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles 6549285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9207000 # number of demand (read+write) MSHR miss cycles 6559285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4564000 # number of demand (read+write) MSHR miss cycles 6569285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 13771000 # number of demand (read+write) MSHR miss cycles 6579285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9207000 # number of overall MSHR miss cycles 6589285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4564000 # number of overall MSHR miss cycles 6599285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 13771000 # number of overall MSHR miss cycles 6609285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for ReadReq accesses 6619285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.771429 # mshr miss rate for ReadReq accesses 6629285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892768 # mshr miss rate for ReadReq accesses 6638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6649055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6659285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for demand accesses 6669285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for demand accesses 6679285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.902935 # mshr miss rate for demand accesses 6689285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935811 # mshr miss rate for overall accesses 6699285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for overall accesses 6709285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.902935 # mshr miss rate for overall accesses 6719285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33238.267148 # average ReadReq mshr miss latency 6729285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37487.654321 # average ReadReq mshr miss latency 6739285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34199.720670 # average ReadReq mshr miss latency 6749265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency 6759265SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency 6769285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 6779285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 6789285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 6799285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33238.267148 # average overall mshr miss latency 6809285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37105.691057 # average overall mshr miss latency 6819285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34427.500000 # average overall mshr miss latency 6827860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6837860SN/A 6847860SN/A---------- End Simulation Statistics ---------- 685